AngeloJacobo
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c11d90440e
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fixed mtb computation
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2024-12-29 22:11:26 +08:00 |
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AngeloJacobo
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1afd06542f
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make mtb mcp to meet timing
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2024-12-29 21:58:26 +08:00 |
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AngeloJacobo
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ab1a5b9f81
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make spd read display better
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2024-12-29 21:40:53 +08:00 |
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AngeloJacobo
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6ead81ba48
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fixed stuck on addr 21, and fixed dual rank
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2024-12-29 21:33:58 +08:00 |
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AngeloJacobo
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f636dcbd2e
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bring all timing parameters to top
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2024-12-29 21:22:52 +08:00 |
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AngeloJacobo
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d424bcdf4e
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add option to debug all registers in ILA
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2024-12-29 20:59:57 +08:00 |
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AngeloJacobo
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7acaf34b44
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added uart to display spd report
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2024-12-29 20:41:17 +08:00 |
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AngeloJacobo
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75857a0af0
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read bytes 0 to 63 of spd then store (sim passing)
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2024-12-29 14:47:57 +08:00 |
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AngeloJacobo
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fbc4b5ff9a
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added initial files for spd
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2024-12-29 12:18:37 +08:00 |
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AngeloJacobo
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3b2ef2afa8
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odt[1] generated by separate oserdes to make it routable
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2024-12-21 18:24:12 +08:00 |
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AngeloJacobo
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7367182640
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dual rank enabled is now passing formal and simulation!
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2024-12-20 18:56:21 +08:00 |
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AngeloJacobo
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4fdaace899
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add dual-rank feature (PHY ongoing changes)
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2024-12-02 11:28:21 +08:00 |
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AngeloJacobo
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05589c3f83
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added self-refresh to vivado IP GUI, tested self-refresh on hardware with microblaze
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2024-11-24 17:40:21 +08:00 |
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AngeloJacobo
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e08612658b
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self-refresh feature done, passing simulation and formal
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2024-11-24 14:31:20 +08:00 |
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AngeloJacobo
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1078e2ffe0
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Revert "add self-refresh option, passing Simulation, ongoing formal"
This reverts commit a5e2adf4a4.
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2024-11-23 11:43:05 +08:00 |
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AngeloJacobo
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a5e2adf4a4
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add self-refresh option, passing Simulation, ongoing formal
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2024-11-17 20:47:14 +08:00 |
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AngeloJacobo
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c58a9d70e6
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add self-refresh feature (untested)
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2024-11-03 14:52:32 +08:00 |
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AngeloJacobo
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65bcf2f621
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add option to skip internal test for Microblaze use
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2024-10-26 09:07:24 +08:00 |
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AngeloJacobo
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e89b06defd
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paremeterized IOSERDES loopback option
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2024-10-13 16:42:31 +08:00 |
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Angelo Jacobo
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95820556c2
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replace ioserdes loopback with logic
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2024-10-12 09:43:27 +08:00 |
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Angelo Jacobo
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aa68c22169
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turn off ECC test by default
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2024-09-01 09:04:45 +08:00 |
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AngeloJacobo
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fc963c3c23
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simulation and formal are now passing for all ECC types
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2024-07-28 17:36:37 +08:00 |
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AngeloJacobo
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f80d4ac21b
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simulation passing for ECC_ENABLE = 3
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2024-07-15 18:31:49 +08:00 |
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AngeloJacobo
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de85925681
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add support for ECC_ENABLE = 3
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2024-07-06 21:24:01 +08:00 |
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AngeloJacobo
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71b0383cda
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add support for other memory address mapping (row_bank_col = 0,1, or 2)
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2024-07-06 09:01:34 +08:00 |
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AngeloJacobo
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c81c51c9f4
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add support for ECC = 1 and 2, passing simulation and formal verification
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2024-06-29 19:36:01 +08:00 |
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AngeloJacobo
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f2805d0e90
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resolve verilator lint flags
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2024-06-24 17:16:26 +08:00 |
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AngeloJacobo
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7d93717b72
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add initial ECC, ECC_ENABLE = 2 working
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2024-06-17 16:25:06 +08:00 |
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AngeloJacobo
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0ca641799d
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add bit files for example demo
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2024-06-10 16:44:41 +08:00 |
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AngeloJacobo
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8fb24dd180
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add copyright on headers
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2024-06-09 12:01:30 +08:00 |
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AngeloJacobo
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2333095668
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clean repo
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2024-06-09 11:31:58 +08:00 |
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Angelo Jacobo
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1ce369cc1f
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Merge pull request #6 from AngeloJacobo/kimos_dev
add support for kimos project
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2024-06-09 10:52:18 +08:00 |
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AngeloJacobo
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a1b15fb9d6
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elevate DIC and RTT_NOM as parameters
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2024-06-09 10:50:18 +08:00 |
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Angelo Jacobo
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df776e059a
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Merge pull request #5 from AngeloJacobo/new_feature_axi
added AXI4 interface option on top of current wishbone interface
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2024-06-03 17:41:45 +08:00 |
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AngeloJacobo
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91fc6d8ed6
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moved axi-related files to separate folders
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2024-06-03 17:36:19 +08:00 |
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AngeloJacobo
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593f56ac4a
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resolve warning in implementation: not connected to load
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2024-06-02 19:20:10 +08:00 |
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AngeloJacobo
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9c440d535f
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fix bug in write levelling with cntvalue > 15 (reaches 31), changed mark_debug for debugging
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2024-06-02 19:19:17 +08:00 |
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AngeloJacobo
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66f0daf0e9
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added AXI4 feature
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2024-06-01 15:30:15 +08:00 |
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AngeloJacobo
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a6982da97d
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match dic and rtt_nom settings
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2024-05-26 20:53:00 +08:00 |
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AngeloJacobo
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eaa45f01d5
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fix error in formal verif
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2024-05-26 20:27:53 +08:00 |
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AngeloJacobo
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57aebc6eef
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fixed error in slot calculation
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2024-05-25 13:49:48 +08:00 |
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AngeloJacobo
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18283f4436
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clean verilator lint by making parameters integer (instead of being inferred as real)
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2024-05-24 22:43:34 +08:00 |
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AngeloJacobo
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88a913f8da
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clean verilator lint
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2024-05-24 21:51:20 +08:00 |
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AngeloJacobo
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237752fa3d
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clean printed details
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2024-05-06 17:11:04 +08:00 |
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AngeloJacobo
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1d1fd96893
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fixed bug when READ_SLOT and WRITE_SLOT is the same
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2024-05-05 21:15:02 +08:00 |
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AngeloJacobo
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22f6db696c
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automatically generate CL and CWL value based on ddr3 clock period
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2024-05-05 15:21:55 +08:00 |
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AngeloJacobo
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bb26b0ef4c
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fixed BYTE_LANES
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2024-05-05 14:03:51 +08:00 |
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AngeloJacobo
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81a6ab32f9
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removed OPT parameters (no use), and add defines
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2024-05-05 13:32:37 +08:00 |
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Angelo Jacobo
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e9633ddae7
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fixed instantiation template
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2024-05-05 13:27:51 +08:00 |
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Angelo Jacobo
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da8eaa5d91
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make internal test shorter during sim
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2024-04-21 13:06:19 +08:00 |