AngeloJacobo
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df67fc038b
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add files for caas and linked uberddr3 files
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2026-01-11 12:03:03 +08:00 |
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AngeloJacobo
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31b3642fbe
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run @ 133MHz with yosys
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2025-12-31 14:40:04 +08:00 |
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AngeloJacobo
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356c6cc1a2
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run at DDR3-1000 (125MHz controller clock)
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2025-12-26 10:02:16 +08:00 |
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AngeloJacobo
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a3efc861da
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update bistream files from latest CI run
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2025-06-05 18:55:44 +08:00 |
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AngeloJacobo
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5f8f5974b4
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added vivado on makefile (make vivado)
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2025-05-12 16:02:38 +08:00 |
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AngeloJacobo
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9fd104b566
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updated example demo bitstream files
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2025-05-11 20:11:05 +08:00 |
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AngeloJacobo
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5ab1ac5d42
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add UART to ax7325b board, make openFPGAloader works on ax7325b board
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2025-03-14 15:23:34 +08:00 |
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AngeloJacobo
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4ce06f5fd8
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all example demos passing openxc7 run!
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2025-03-02 18:42:49 +08:00 |
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AngeloJacobo
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d8cb6d16d9
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update copyright date
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2025-01-02 13:18:42 +08:00 |
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AngeloJacobo
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f636dcbd2e
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bring all timing parameters to top
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2024-12-29 21:22:52 +08:00 |
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AngeloJacobo
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7acaf34b44
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added uart to display spd report
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2024-12-29 20:41:17 +08:00 |
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AngeloJacobo
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253d9495ca
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added led to xdc
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2024-12-29 14:53:19 +08:00 |
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AngeloJacobo
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75857a0af0
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read bytes 0 to 63 of spd then store (sim passing)
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2024-12-29 14:47:57 +08:00 |
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AngeloJacobo
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d3a0204ab5
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add makefile for openxc7 run (NOT YET WORKING)
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2024-10-13 16:46:51 +08:00 |