AngeloJacobo
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e22c2b1c53
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fix whitespaces
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2026-01-18 12:17:36 +08:00 |
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AngeloJacobo
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2226aa4461
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Step 7: Resize registers
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2026-01-18 12:01:58 +08:00 |
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AngeloJacobo
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859963ad20
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Step 6: Optimize wb_stall logic
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2026-01-18 11:55:31 +08:00 |
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AngeloJacobo
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5066c3d280
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Step 5: Optimize stage-1 stall and stage-2 stall logic
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2026-01-18 11:40:26 +08:00 |
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AngeloJacobo
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f724ec0d43
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Step 4: Arrange logic (stage-2 pre/act/wr-rd logic)
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2026-01-18 11:25:47 +08:00 |
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AngeloJacobo
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fad0a7b19a
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Step 3: Register conditions in advance (calibration fsm)
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2026-01-18 11:19:04 +08:00 |
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AngeloJacobo
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282d9596ca
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Step 2: Register conditions in advance (2-stage pipeline)
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2026-01-18 11:06:49 +08:00 |
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AngeloJacobo
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98fe547262
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Step 1: Separate _q (sequential) from _d (combinational) logic
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2026-01-18 10:52:57 +08:00 |
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AngeloJacobo
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a653bbeb35
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revert ddr3_controller to commit a1258e2 (before optimizing)
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2026-01-18 10:19:05 +08:00 |
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AngeloJacobo
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3c4c4b9f83
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optimize stage1/2 stall logic, optimize size of registers (delay_before_*, added_read_pipe*, delay_read_pipe), register huge conditions, explicit removal of unused states)
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2025-12-31 14:35:04 +08:00 |
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AngeloJacobo
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3d94fae1e6
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separated sequential from combinational logic for pipeline stage logic
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2025-12-29 14:36:25 +08:00 |
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AngeloJacobo
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a3ffeb670f
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register conditions for anticipate logic; change logic order for stage 2 from r/w-act-pre to pre-act-r/w
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2025-12-29 10:26:32 +08:00 |
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AngeloJacobo
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0b3bb30fae
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added define for UART-debugging of BIST exclusively
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2025-12-27 13:01:19 +08:00 |
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AngeloJacobo
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80da754a64
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achieve >40% increase in max frequency
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2025-12-26 09:50:12 +08:00 |
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AngeloJacobo
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864b8069c3
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fix read_data_store_lane logic
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2025-12-23 10:01:57 +08:00 |
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AngeloJacobo
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a3edea5e00
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add prep state for ANALYZE_DATA to cut timing path due to indexing with lane
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2025-12-22 13:11:20 +08:00 |
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AngeloJacobo
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c605135dd9
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make o_wb_stall/o_wb_stall_calib combinational logic
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2025-12-22 08:50:40 +08:00 |
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AngeloJacobo
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fdf1becc03
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register stage2 if-else conditions (2.4% increase in max freq)
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2025-12-19 17:39:03 +08:00 |
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AngeloJacobo
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ba640ca59c
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optimize wb_stall/wb_stall_calib logic (3.7% increase in max freq)
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2025-12-14 11:53:04 +08:00 |
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AngeloJacobo
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157cca28d8
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fixed late_dq logic
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2025-05-12 18:27:57 +08:00 |
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AngeloJacobo
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90647a70e0
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resolved (again) the verilator lint
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2025-05-12 16:28:07 +08:00 |
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AngeloJacobo
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50c0a6488d
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verilator now passing lint even with older verilator version
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2025-05-11 20:02:13 +08:00 |
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AngeloJacobo
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b990372663
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added support for DLL_OFF and Lattice ECP5 PHY
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2025-04-19 13:24:20 +08:00 |
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AngeloJacobo
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c0bc4ca48a
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removed extra semicolon
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2025-03-02 18:46:07 +08:00 |
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AngeloJacobo
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94b4e0866b
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added UART for debugging, DQ now support 1 cycle late
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2025-03-02 14:15:44 +08:00 |
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AngeloJacobo
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5c52351bce
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uncommented default_nettype
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2025-03-01 19:32:35 +08:00 |
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AngeloJacobo
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e19c6023c4
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remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing
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2025-03-01 15:51:48 +08:00 |
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AngeloJacobo
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74f68760a4
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removed mark_debug
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2025-03-01 14:40:21 +08:00 |
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Angelo Jacobo
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3898b1e762
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Merge branch 'main' into higher_speed_feature
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2025-02-22 11:31:54 +08:00 |
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AngeloJacobo
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d4ecfee105
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improve latency of ack after write
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2025-02-09 16:16:42 +08:00 |
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AngeloJacobo
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7ada4bcbab
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add support for BIST_MODE = 0,1,and 2 , write data is also randomized
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2025-02-09 09:48:46 +08:00 |
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AngeloJacobo
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c81f9044d8
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add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600!
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2025-01-30 19:07:09 +08:00 |
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AngeloJacobo
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760979db27
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hardware runs on ddr3-1333! Now working on ddr3-1600
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2025-01-19 17:15:40 +08:00 |
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AngeloJacobo
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d8cb6d16d9
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update copyright date
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2025-01-02 13:18:42 +08:00 |
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AngeloJacobo
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f636dcbd2e
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bring all timing parameters to top
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2024-12-29 21:22:52 +08:00 |
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AngeloJacobo
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3b2ef2afa8
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odt[1] generated by separate oserdes to make it routable
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2024-12-21 18:24:12 +08:00 |
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AngeloJacobo
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7367182640
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dual rank enabled is now passing formal and simulation!
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2024-12-20 18:56:21 +08:00 |
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AngeloJacobo
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4fdaace899
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add dual-rank feature (PHY ongoing changes)
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2024-12-02 11:28:21 +08:00 |
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AngeloJacobo
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05589c3f83
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added self-refresh to vivado IP GUI, tested self-refresh on hardware with microblaze
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2024-11-24 17:40:21 +08:00 |
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AngeloJacobo
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e08612658b
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self-refresh feature done, passing simulation and formal
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2024-11-24 14:31:20 +08:00 |
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AngeloJacobo
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1078e2ffe0
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Revert "add self-refresh option, passing Simulation, ongoing formal"
This reverts commit a5e2adf4a4.
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2024-11-23 11:43:05 +08:00 |
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AngeloJacobo
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a5e2adf4a4
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add self-refresh option, passing Simulation, ongoing formal
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2024-11-17 20:47:14 +08:00 |
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AngeloJacobo
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c58a9d70e6
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add self-refresh feature (untested)
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2024-11-03 14:52:32 +08:00 |
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AngeloJacobo
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65bcf2f621
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add option to skip internal test for Microblaze use
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2024-10-26 09:07:24 +08:00 |
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Angelo Jacobo
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aa68c22169
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turn off ECC test by default
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2024-09-01 09:04:45 +08:00 |
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AngeloJacobo
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fc963c3c23
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simulation and formal are now passing for all ECC types
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2024-07-28 17:36:37 +08:00 |
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AngeloJacobo
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f80d4ac21b
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simulation passing for ECC_ENABLE = 3
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2024-07-15 18:31:49 +08:00 |
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AngeloJacobo
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de85925681
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add support for ECC_ENABLE = 3
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2024-07-06 21:24:01 +08:00 |
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AngeloJacobo
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71b0383cda
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add support for other memory address mapping (row_bank_col = 0,1, or 2)
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2024-07-06 09:01:34 +08:00 |
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AngeloJacobo
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c81c51c9f4
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add support for ECC = 1 and 2, passing simulation and formal verification
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2024-06-29 19:36:01 +08:00 |