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v2.2.0

Mono Color

• cd753929af SwigCleanup James Cherry 2019-11-17 09:47:53 -07:00
• 63691545c9 Merge branch 'master' of https://github.com/The-OpenROAD-Project/OpenSTA James Cherry 2019-11-16 19:19:09 -07:00
• d713166a48 refactor swig init out of the library James Cherry 2019-11-16 18:11:25 -07:00
• 0f8ea9c752 format James Cherry 2019-11-14 22:14:26 -07:00
• a0107557d1 make TclInitVar.cc in /build James Cherry 2019-11-14 22:12:17 -07:00
• 0c97a10f9a network external cell/port member vars James Cherry 2019-11-13 14:58:38 -07:00
• c59b2db038 build swig outputs in /build James Cherry 2019-11-12 08:29:40 -07:00
• de50cc5d67 rm auto's for compile time James Cherry 2019-11-11 15:53:29 -07:00
• cc1bd6b5ab TransRiseFall -> RiseFall James Cherry 2019-11-11 15:30:19 -07:00
• bdab2acb09 use operator= instead of copy James Cherry 2019-11-11 13:03:38 -07:00
• c018cb212b graph no counts needed James Cherry 2019-11-11 11:16:24 -07:00
• 3076b8d2ff VertexIndex -> VertexId James Cherry 2019-11-11 09:38:25 -07:00
• e647ed391d dispatch queue for thread support James Cherry 2019-11-11 08:48:27 -07:00
• 184d044b02 replace Pool with ObjectTable James Cherry 2019-11-11 08:28:42 -07:00
• 2e6de93870 leaks James Cherry 2019-11-10 20:27:59 -07:00
• c89e9da712 set_input_delay/set_output_delay leaf pin iterators James Cherry 2019-11-10 17:10:26 -07:00
• 5a9c99228c .gitignore James Cherry 2019-11-10 15:59:19 -07:00
• b12a89de0a readme James Cherry 2019-11-08 08:45:03 -07:00
• f0e0223c7f netSlack James Cherry 2019-11-06 09:55:04 -07:00
• bbdb4ea5bc staMain init_filename arg James Cherry 2019-11-05 16:05:52 -07:00
• e7d8689f70 resizer support James Cherry 2019-11-05 10:14:35 -07:00
• 6934b4ebcd updates for resizer James Cherry 2019-11-05 07:51:54 -07:00
• 3179c5a343 public ensureLevelized James Cherry 2019-11-03 09:48:22 -08:00
• 84c13732f7 Sta::makeCmdNetwork -> Sta::makeSdcNetwork James Cherry 2019-11-02 19:32:09 -07:00
• 6ac93c8c7d vertex_pin -> leaf_pin James Cherry 2019-10-25 08:51:59 -07:00
• 13037e6093 rm BugLog James Cherry 2019-10-20 15:28:29 -07:00
• 56851ed438 ssta met/violated include sigma James Cherry 2019-10-09 18:02:54 -10:00
• 81492652ce create_clock redef preserve propagated James Cherry 2019-10-09 18:02:33 -10:00
• 0ed0d384ac SwigCleanup use pragmas to disable compile warnings James Cherry 2019-10-09 18:02:02 -10:00
• 37ee851943 sync James Cherry 2019-09-17 17:48:11 -06:00
• 2bf8b78fa5 thread speed James Cherry 2019-09-07 12:37:05 -07:00
• f9bc74e962 format_distance, area James Cherry 2019-08-16 17:34:48 -07:00
• 3ae920be7d write_verilog escaped bus name James Cherry 2019-08-13 21:34:35 -07:00
• 3c67ef972d copyright James Cherry 2019-08-13 21:34:26 -07:00
• 41ebd34031 leaks James Cherry 2019-08-12 22:56:32 -07:00
• a20fb113b7 gcc compile James Cherry 2019-08-12 21:36:32 -07:00
• 109925644f regression fast James Cherry 2019-08-09 18:44:31 -07:00
• 30a5abebc6 Hash -> size_t James Cherry 2019-08-08 14:13:02 -07:00
• e16696c347 wire_load fanout_length values in quotes ucsd20190808 James Cherry 2019-08-08 14:12:07 -07:00
• 73fef1117e copyright James Cherry 2019-07-19 07:27:59 -07:00
• ed88ddc292 rm DelayFloatClass James Cherry 2019-07-19 07:27:32 -07:00
• 90be94072b README repo url James Cherry 2019-07-19 07:17:03 -07:00
• 9d93130ff2 range iterators James Cherry 2019-07-18 06:19:00 -07:00
• 73fb94a2dd set_units James Cherry 2019-07-13 16:56:46 -07:00
• fa849908d7 set_cmd_units James Cherry 2019-07-08 11:50:41 -07:00
• db6b650a52 splash include git sha1 James Cherry 2019-07-07 09:58:47 -07:00
• d7248abcab sdc matches for verilog port nets like \foo[2] [0] James Cherry 2019-07-04 17:26:14 -07:00
• 74e287a7eb write_verilog escaped bus port name "input [7:0] \in[0] ;" James Cherry 2019-07-03 21:18:38 -07:00
• 7af69066df VerilogWriter use liberty bus port order James Cherry 2019-07-02 16:33:31 -07:00
• eb9fdd1be0 write verilog match liberty bus bit order James Cherry 2019-07-02 07:07:34 -07:00
• c759feaff6 SdcNetwork leak James Cherry 2019-07-01 10:26:59 -07:00
• 8fa2dd674c SdcNetwork memory error James Cherry 2019-07-01 07:37:52 -07:00
• ed6ed7c74b g++ compile issue James Cherry 2019-06-30 22:44:00 -07:00
• f34fc4162d base class destructors public virtual or protected non-virtual James Cherry 2019-06-30 22:30:53 -07:00
• d76ee0ca62 refactor SdcNetwork James Cherry 2019-06-30 17:17:03 -07:00
• 93f5f9d664 no need for virtuals in Concrete network objects James Cherry 2019-06-28 13:38:56 -07:00
• 88331ab9b1 Network bus brkts use library values James Cherry 2019-06-28 11:51:43 -07:00
• d108a15c56 write_verilog fails for missing pins James Cherry 2019-06-27 18:04:57 -07:00
• 5d7ad0a1ef write_verilog use concat for instance bus ports James Cherry 2019-06-27 16:06:46 -07:00
• 61333cd980 Network:bus_brkts_left/right James Cherry 2019-06-26 17:14:31 -07:00
• 344394de29 link_design use verilog library to lookup top James Cherry 2019-06-26 16:01:58 -07:00
• 389b9b8276 set_data_check no -setup|-hold James Cherry 2019-06-26 15:58:23 -07:00
• beaaafc4f2 ChangeLog.txt James Cherry 2019-06-24 17:16:29 -07:00
• e05e7185ba report_checks transition_time field -> slew James Cherry 2019-06-24 08:35:04 -07:00
• 11aa6e759a tclListSeqLibertyCell James Cherry 2019-06-23 21:59:02 -07:00
• 15e759a992 get_lib_cells allow wildcard lib name James Cherry 2019-06-23 21:38:01 -07:00
• 12494398e9 set_clock_sense -> set_sense, LibertyPort::driveResistance James Cherry 2019-06-23 19:52:29 -07:00
• b9a7b349eb template tcl typemap(in) seqs/sets James Cherry 2019-06-22 11:17:13 -07:00
• 78fa68cc7a TclListSeqLibertyLibrary James Cherry 2019-06-21 21:42:45 -07:00
• fa680f4500 stringBeginEq James Cherry 2019-06-21 13:25:21 -07:00
• 337fab4c44 equiv cells dont_use turd James Cherry 2019-06-21 13:21:37 -07:00
• fef70f0983 ConcreteNetwork::replaceCell failed if port order differed cont. James Cherry 2019-06-21 12:50:57 -07:00
• 527b74b8e4 ConcreteNetwork::replaceCell failed if port order differed James Cherry 2019-06-21 12:02:35 -07:00
• e87c2e1da3 stringBeginEq James Cherry 2019-06-21 09:06:41 -07:00
• 5f23536b17 support equiv cells across libraries James Cherry 2019-06-20 21:41:49 -07:00
• e26da7c37e stringBeginEq James Cherry 2019-06-20 21:41:19 -07:00
• e2dd765b9b report_power Nan James Cherry 2019-06-19 16:05:13 -07:00
• 1def4110c0 report_power NaN James Cherry 2019-06-19 07:55:04 -07:00
• 1a84830895 sta::worst_slack args, sta to verilog name args James Cherry 2019-06-18 15:52:12 -07:00
• db2a06c430 findCmdLineFlag/Key James Cherry 2019-06-17 16:42:26 -07:00
• eea6ab1a29 write_verilog -sorted -> -sort James Cherry 2019-06-17 12:33:37 -07:00
• 49b2c3cea7 rm redundant StaState args James Cherry 2019-06-17 08:32:28 -07:00
• 3f7e207491 write_verilog James Cherry 2019-06-16 21:08:00 -07:00
• d9237aa3e5 Liberty cell drive_resistance property James Cherry 2019-06-16 10:20:51 -07:00
• 96fcf1d8b2 ConcreteCell/Port pointers to corresponding liberty James Cherry 2019-06-15 22:20:54 -07:00
• dd8153c7f9 Network::isLeaf James Cherry 2019-06-14 21:03:11 -07:00
• c66da2935f cmd line args -exit cmd_file (flush -x, -f) James Cherry 2019-06-14 16:53:03 -07:00
• 154dcf0042 rm insert_buffer James Cherry 2019-06-14 16:52:34 -07:00
• 9659c43590 network/sta replaceCell Cell support James Cherry 2019-06-14 12:05:34 -07:00
• f6d397ce72 ConcreteParasitics::deleteReducedParasitics James Cherry 2019-06-14 08:46:41 -07:00
• fc41c240ba get_lib_cell_error James Cherry 2019-06-13 08:43:38 -07:00
• 5f3b10bdf2 mv GraphDelayCalc1::isDriver to Vertex James Cherry 2019-06-12 21:41:33 -07:00
• a04e557faa LICENSE James Cherry 2019-06-09 22:33:42 -07:00
• 1158484474 flush no cmd lib James Cherry 2019-06-05 11:29:28 -07:00
• de34f8b6b2 report_tns/wns James Cherry 2019-06-05 10:20:48 -07:00
• 94f3e7f0de export sourceTclFileEchoVerbose James Cherry 2019-06-04 10:18:14 -07:00
• 61b1ac4d12 sync James Cherry 2019-06-04 08:12:22 -07:00
• 7e0cdcc895 Parasitics const James Cherry 2019-06-02 14:58:09 -07:00
• 21658ed182 again James Cherry 2019-06-01 18:41:09 -07:00
• cbbdce9ed3 network edit functions singular args James Cherry 2019-06-01 18:32:04 -07:00