mv GraphDelayCalc1::isDriver to Vertex

dcalc/GraphDelayCalc1.cc

@@ -574,7 +574,7 @@ void
 GraphDelayCalc1::seedRootSlew(Vertex *vertex,
 			      ArcDelayCalc *arc_delay_calc)
 {
-  if (isDriver(vertex))
+  if (vertex->isDriver(network_))
     seedDrvrSlew(vertex, arc_delay_calc);
   else
     seedLoadSlew(vertex);
@@ -859,7 +859,7 @@ GraphDelayCalc1::findVertexDelay(Vertex *vertex,
 		vertex->name(sdc_network_),
 		network_->cellName(network_->instance(pin)));
     if (network_->isLeaf(pin)) {
-      if (isDriver(vertex)) {
+      if (vertex->isDriver(network_)) {
 	bool delay_changed = findDriverDelays(vertex, arc_delay_calc);
 	if (propagate) {
 	  if (network_->direction(pin)->isInternal())
@@ -896,24 +896,6 @@ GraphDelayCalc1::enqueueTimingChecksEdges(Vertex *vertex)
   }
 }
 
-bool
-GraphDelayCalc1::isDriver(Vertex *vertex)
-{
-  Pin *pin = vertex->pin();
-  PortDirection *dir = network_->direction(pin);
-  bool top_level_port = network_->isTopLevelPort(pin);
-  return ((top_level_port
-	   && (dir->isInput()
-	       || (dir->isBidirect()
-		   && vertex->isBidirectDriver())))
-	  || (!top_level_port
-	      && (dir->isOutput()
-		  || dir->isTristate()
-		  || (dir->isBidirect()
-		      && vertex->isBidirectDriver())
-		  || dir->isInternal())));
-}
-
 bool
 GraphDelayCalc1::findDriverDelays(Vertex *drvr_vertex,
 				  ArcDelayCalc *arc_delay_calc)

dcalc/GraphDelayCalc1.hh

@@ -213,7 +213,6 @@ protected:
 		Parasitic *drvr_parasitic,
 		const TransRiseFall *tr,
 		const DcalcAnalysisPt *dcalc_ap) const;
-  bool isDriver(Vertex *vertex);
 
   // Observer for edge delay changes.
   DelayCalcObserver *observer_;

graph/Graph.cc

@@ -1170,6 +1170,23 @@ Vertex::name(const Network *network) const
     return network->pathName(pin_);
 }
 
+bool
+Vertex::isDriver(const Network *network) const
+{
+  PortDirection *dir = network->direction(pin_);
+  bool top_level_port = network->isTopLevelPort(pin_);
+  return ((top_level_port
+	   && (dir->isInput()
+	       || (dir->isBidirect()
+		   && is_bidirect_drvr_)))
+	  || (!top_level_port
+	      && (dir->isOutput()
+		  || dir->isTristate()
+		  || (dir->isBidirect()
+		      && is_bidirect_drvr_)
+		  || dir->isInternal())));
+}
+
 void
 Vertex::setLevel(Level level)
 {

graph/Graph.hh

@@ -266,6 +266,7 @@ public:
   // Pin path with load/driver suffix for bidirects.
   const char *name(const Network *network) const;
   bool isBidirectDriver() const { return is_bidirect_drvr_; }
+  bool isDriver(const Network *network) const;
   Level level() const { return level_; }
   void setLevel(Level level);
   bool isRoot() const{ return level_ == 0; }

tcl/Sdc.tcl

@@ -2365,7 +2365,7 @@ define_cmd_args "set_load" \
 
 proc set_load { args } {
   parse_key_args "set_load" args keys {-corner} \
-    flags {-rise -fall -min -max -subtract_pin_load  -pin_load -wire_load}\
+    flags {-rise -fall -min -max -subtract_pin_load -pin_load -wire_load}\
 
   check_argc_eq2 "set_load" $args