Commit Graph

1746 Commits

Author SHA1 Message Date
James Cherry eb9fdd1be0 write verilog match liberty bus bit order 2019-07-02 07:07:34 -07:00
James Cherry c759feaff6 SdcNetwork leak 2019-07-01 10:26:59 -07:00
James Cherry 8fa2dd674c SdcNetwork memory error 2019-07-01 07:37:52 -07:00
James Cherry ed6ed7c74b g++ compile issue 2019-06-30 22:44:00 -07:00
James Cherry f34fc4162d base class destructors public virtual or protected non-virtual 2019-06-30 22:30:53 -07:00
James Cherry d76ee0ca62 refactor SdcNetwork 2019-06-30 17:17:03 -07:00
James Cherry 93f5f9d664 no need for virtuals in Concrete network objects 2019-06-28 13:38:56 -07:00
James Cherry 88331ab9b1 Network bus brkts use library values 2019-06-28 11:51:43 -07:00
James Cherry d108a15c56 write_verilog fails for missing pins 2019-06-27 18:04:57 -07:00
James Cherry 5d7ad0a1ef write_verilog use concat for instance bus ports 2019-06-27 16:06:46 -07:00
James Cherry 61333cd980 Network:bus_brkts_left/right 2019-06-26 17:14:31 -07:00
James Cherry 344394de29 link_design use verilog library to lookup top 2019-06-26 16:01:58 -07:00
James Cherry 389b9b8276 set_data_check no -setup|-hold 2019-06-26 15:58:23 -07:00
James Cherry beaaafc4f2 ChangeLog.txt 2019-06-24 17:16:29 -07:00
James Cherry e05e7185ba report_checks transition_time field -> slew 2019-06-24 08:35:04 -07:00
James Cherry 11aa6e759a tclListSeqLibertyCell 2019-06-23 21:59:02 -07:00
James Cherry 15e759a992 get_lib_cells allow wildcard lib name 2019-06-23 21:38:01 -07:00
James Cherry 12494398e9 set_clock_sense -> set_sense, LibertyPort::driveResistance 2019-06-23 19:52:29 -07:00
James Cherry b9a7b349eb template tcl typemap(in) seqs/sets 2019-06-22 11:17:13 -07:00
James Cherry 78fa68cc7a TclListSeqLibertyLibrary 2019-06-21 21:42:45 -07:00
James Cherry fa680f4500 stringBeginEq 2019-06-21 13:25:21 -07:00
James Cherry 337fab4c44 equiv cells dont_use turd 2019-06-21 13:21:37 -07:00
James Cherry fef70f0983 ConcreteNetwork::replaceCell failed if port order differed cont. 2019-06-21 12:50:57 -07:00
James Cherry 527b74b8e4 ConcreteNetwork::replaceCell failed if port order differed 2019-06-21 12:02:35 -07:00
James Cherry e87c2e1da3 stringBeginEq 2019-06-21 09:06:41 -07:00
James Cherry 5f23536b17 support equiv cells across libraries 2019-06-20 21:41:49 -07:00
James Cherry e26da7c37e stringBeginEq 2019-06-20 21:41:19 -07:00
James Cherry e2dd765b9b report_power Nan 2019-06-19 16:05:13 -07:00
James Cherry 1def4110c0 report_power NaN 2019-06-19 07:55:04 -07:00
James Cherry 1a84830895 sta::worst_slack args, sta to verilog name args 2019-06-18 15:52:12 -07:00
James Cherry db2a06c430 findCmdLineFlag/Key 2019-06-17 16:42:26 -07:00
James Cherry eea6ab1a29 write_verilog -sorted -> -sort 2019-06-17 12:33:37 -07:00
James Cherry 49b2c3cea7 rm redundant StaState args 2019-06-17 08:32:28 -07:00
James Cherry 3f7e207491 write_verilog 2019-06-16 21:08:00 -07:00
James Cherry d9237aa3e5 Liberty cell drive_resistance property 2019-06-16 10:20:51 -07:00
James Cherry 96fcf1d8b2 ConcreteCell/Port pointers to corresponding liberty 2019-06-15 22:20:54 -07:00
James Cherry dd8153c7f9 Network::isLeaf 2019-06-14 21:03:11 -07:00
James Cherry c66da2935f cmd line args -exit cmd_file (flush -x, -f) 2019-06-14 16:53:03 -07:00
James Cherry 154dcf0042 rm insert_buffer 2019-06-14 16:52:34 -07:00
James Cherry 9659c43590 network/sta replaceCell Cell support 2019-06-14 12:05:34 -07:00
James Cherry f6d397ce72 ConcreteParasitics::deleteReducedParasitics 2019-06-14 08:46:41 -07:00
James Cherry fc41c240ba get_lib_cell_error 2019-06-13 08:43:38 -07:00
James Cherry 5f3b10bdf2 mv GraphDelayCalc1::isDriver to Vertex 2019-06-12 21:41:33 -07:00
James Cherry a04e557faa
LICENSE 2019-06-09 22:33:42 -07:00
James Cherry 1158484474 flush no cmd lib 2019-06-05 11:29:28 -07:00
James Cherry de34f8b6b2 report_tns/wns 2019-06-05 10:20:48 -07:00
James Cherry 94f3e7f0de export sourceTclFileEchoVerbose 2019-06-04 10:18:14 -07:00
James Cherry 61b1ac4d12 sync 2019-06-04 08:12:22 -07:00
James Cherry 7e0cdcc895 Parasitics const 2019-06-02 14:58:09 -07:00
James Cherry 21658ed182 again 2019-06-01 18:41:09 -07:00