61 lines
1.9 KiB
Plaintext
61 lines
1.9 KiB
Plaintext
No paths found.
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PASS: delay calculation completed
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in1 (in)
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0.02 0.02 ^ buf1/Z (BUF_X1)
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0.01 0.02 v inv1/ZN (INV_X1)
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0.00 0.02 v reg1/D (DFF_X1)
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0.02 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.02 data arrival time
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---------------------------------------------------------
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0.02 slack (MET)
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PASS: min path delay reported
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.92 slack (MET)
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PASS: max path delay reported
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ALL PASSED
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