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OpenSTA/dcalc/test/dcalc_arnoldi_spef.ok

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Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
--- Test 1: arnoldi + SPEF ---
PASS: set arnoldi
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
PASS: report_checks
Startpoint: in1 (input port clocked by clk)
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
1.00 1.00 v input external delay
0.00 1.00 v in1 (in)
12.16 13.16 v r1/D (DFFHQx4_ASAP7_75t_R)
13.16 data arrival time
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 clock reconvergence pessimism
12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
12.51 24.61 library hold time
24.61 data required time
---------------------------------------------------------
24.61 data required time
-13.16 data arrival time
---------------------------------------------------------
-11.46 slack (VIOLATED)
PASS: min path
No paths found.
PASS: in1->out
No paths found.
PASS: in2->out
Warning: dcalc_arnoldi_spef.tcl line 1, unknown field nets.
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
48.38 0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
1 13.98 29.94 62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
54.60 15.52 90.62 ^ u1/A (BUFx2_ASAP7_75t_R)
1 13.97 54.12 33.63 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
71.52 17.95 142.20 ^ u2/B (AND2x2_ASAP7_75t_R)
1 14.02 63.30 44.25 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
78.93 18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
0.00 500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
-----------------------------------------------------------------------------
503.12 data required time
-204.96 data arrival time
-----------------------------------------------------------------------------
298.15 slack (MET)
PASS: with fields
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock source latency
0.00 0.00 ^ clk2 (in)
12.11 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock source latency
0.00 500.00 ^ clk3 (in)
11.92 511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
0.00 511.92 clock reconvergence pessimism
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
PASS: full_clock
--- Test 2: report_dcalc ---
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
Cell: BUFx2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
A ^ -> Y ^
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 54.60
| total_output_net_capacitance = 13.97
| 11.52 23.04
v --------------------
40.00 | 35.12 50.39
80.00 | 40.08 55.44
Table value = 40.18
PVT scale factor = 1.00
Delay = 40.18
------- input_net_transition = 54.60
| total_output_net_capacitance = 13.97
| 11.52 23.04
v --------------------
40.00 | 37.28 71.28
80.00 | 38.13 71.69
Table value = 44.77
PVT scale factor = 1.00
Slew = 44.77
.............................................
A v -> Y v
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 52.63
| total_output_net_capacitance = 13.97
| 11.52 23.04
v --------------------
40.00 | 36.17 49.65
80.00 | 43.28 56.72
Table value = 41.27
PVT scale factor = 1.00
Delay = 41.27
------- input_net_transition = 52.63
| total_output_net_capacitance = 13.97
| 11.52 23.04
v --------------------
40.00 | 31.72 59.66
80.00 | 32.63 60.23
Table value = 37.92
PVT scale factor = 1.00
Slew = 37.92
.............................................
dcalc u1 A->Y max: done
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
Cell: BUFx2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
A ^ -> Y ^
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 53.77
| total_output_net_capacitance = 13.72
| 11.52 23.04
v --------------------
40.00 | 35.12 50.39
80.00 | 40.08 55.44
Table value = 39.75
PVT scale factor = 1.00
Delay = 39.75
------- input_net_transition = 53.77
| total_output_net_capacitance = 13.72
| 11.52 23.04
v --------------------
40.00 | 37.28 71.28
80.00 | 38.13 71.69
Table value = 44.03
PVT scale factor = 1.00
Slew = 44.03
.............................................
A v -> Y v
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 51.77
| total_output_net_capacitance = 13.72
| 11.52 23.04
v --------------------
40.00 | 36.17 49.65
80.00 | 43.28 56.72
Table value = 40.83
PVT scale factor = 1.00
Delay = 40.83
------- input_net_transition = 51.77
| total_output_net_capacitance = 13.72
| 11.52 23.04
v --------------------
40.00 | 31.72 59.66
80.00 | 32.63 60.23
Table value = 37.30
PVT scale factor = 1.00
Slew = 37.30
.............................................
dcalc u1 A->Y min: done
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
Cell: AND2x2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
A ^ -> Y ^
P = 1.00 V = 0.70 T = 25.00
------- input_net_transition = 54.25
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 40.48 58.12
80.00 | 45.47 63.31
Table value = 46.10
PVT scale factor = 1.00
Delay = 46.10
------- input_net_transition = 54.25
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 43.68 82.62
80.00 | 44.42 82.97
Table value = 52.37
PVT scale factor = 1.00
Slew = 52.37
.............................................
A v -> Y v
P = 1.00 V = 0.70 T = 25.00
------- input_net_transition = 52.20
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 43.09 58.01
80.00 | 52.65 67.66
Table value = 49.25
PVT scale factor = 1.00
Delay = 49.25
------- input_net_transition = 52.20
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 35.08 65.82
80.00 | 36.06 66.39
Table value = 42.02
PVT scale factor = 1.00
Slew = 42.02
.............................................
dcalc u2 A->Y: done
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
Cell: AND2x2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
B ^ -> Y ^
P = 1.00 V = 0.70 T = 25.00
------- input_net_transition = 71.52
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 42.69 60.35
80.00 | 48.65 66.47
Table value = 51.25
PVT scale factor = 1.00
Delay = 51.25
------- input_net_transition = 71.52
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 43.75 82.69
80.00 | 44.49 83.12
Table value = 52.73
PVT scale factor = 1.00
Slew = 52.73
.............................................
B v -> Y v
P = 1.00 V = 0.70 T = 25.00
------- input_net_transition = 67.14
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 41.76 56.58
80.00 | 50.55 65.49
Table value = 50.96
PVT scale factor = 1.00
Delay = 50.96
------- input_net_transition = 67.14
| total_output_net_capacitance = 14.02
| 11.52 23.04
v --------------------
40.00 | 35.08 65.81
80.00 | 36.22 66.50
Table value = 42.45
PVT scale factor = 1.00
Slew = 42.45
.............................................
dcalc u2 B->Y: done
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
Cell: AND2x2_ASAP7_75t_R
Arc sense: positive_unate
Arc type: combinational
B ^ -> Y ^
P = 1.00 V = 0.70 T = 25.00
------- input_net_transition = 69.61
| total_output_net_capacitance = 13.96
| 11.52 23.04
v --------------------
40.00 | 42.69 60.35
80.00 | 48.65 66.47
Table value = 50.87
PVT scale factor = 1.00
Delay = 50.87
------- input_net_transition = 69.61
| total_output_net_capacitance = 13.96
| 11.52 23.04
v --------------------
40.00 | 43.75 82.69
80.00 | 44.49 83.12
Table value = 52.50
PVT scale factor = 1.00
Slew = 52.50
.............................................
B v -> Y v
P = 1.00 V = 0.70 T = 25.00
------- input_net_transition = 65.29
| total_output_net_capacitance = 13.95
| 11.52 23.04
v --------------------
40.00 | 41.76 56.58
80.00 | 50.55 65.49
Table value = 50.46
PVT scale factor = 1.00
Delay = 50.46
------- input_net_transition = 65.29
| total_output_net_capacitance = 13.95
| 11.52 23.04
v --------------------
40.00 | 35.08 65.81
80.00 | 36.22 66.50
Table value = 42.22
PVT scale factor = 1.00
Slew = 42.22
.............................................
dcalc u2 B->Y min: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.92
| 11.52 23.04
v --------------------
40.00 | 64.09 71.91
80.00 | 69.26 77.08
Table value = 66.81
PVT scale factor = 1.00
Delay = 66.81
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.92
| 11.52 23.04
v --------------------
40.00 | 21.04 37.91
80.00 | 21.05 37.92
Table value = 24.56
PVT scale factor = 1.00
Slew = 24.56
.............................................
CLK ^ -> Q v
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.91
| 11.52 23.04
v --------------------
40.00 | 61.63 68.60
80.00 | 66.47 73.44
Table value = 64.09
PVT scale factor = 1.00
Delay = 64.09
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.91
| 11.52 23.04
v --------------------
40.00 | 17.99 31.89
80.00 | 17.98 31.88
Table value = 20.87
PVT scale factor = 1.00
Slew = 20.87
.............................................
dcalc r1 CLK->Q max: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 47.79
| total_output_net_capacitance = 13.81
| 11.52 23.04
v --------------------
40.00 | 64.09 71.91
80.00 | 69.26 77.08
Table value = 66.65
PVT scale factor = 1.00
Delay = 66.65
------- input_net_transition = 47.79
| total_output_net_capacitance = 13.81
| 11.52 23.04
v --------------------
40.00 | 21.04 37.91
80.00 | 21.05 37.92
Table value = 24.39
PVT scale factor = 1.00
Slew = 24.39
.............................................
CLK ^ -> Q v
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 47.79
| total_output_net_capacitance = 13.80
| 11.52 23.04
v --------------------
40.00 | 61.63 68.60
80.00 | 66.47 73.44
Table value = 63.95
PVT scale factor = 1.00
Delay = 63.95
------- input_net_transition = 47.79
| total_output_net_capacitance = 13.80
| 11.52 23.04
v --------------------
40.00 | 17.99 31.89
80.00 | 17.98 31.88
Table value = 20.74
PVT scale factor = 1.00
Slew = 20.74
.............................................
dcalc r1 CLK->Q min: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.98
| 11.52 23.04
v --------------------
40.00 | 64.09 71.91
80.00 | 69.26 77.08
Table value = 66.84
PVT scale factor = 1.00
Delay = 66.84
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.98
| 11.52 23.04
v --------------------
40.00 | 21.04 37.91
80.00 | 21.05 37.92
Table value = 24.64
PVT scale factor = 1.00
Slew = 24.64
.............................................
CLK ^ -> Q v
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.98
| 11.52 23.04
v --------------------
40.00 | 61.63 68.60
80.00 | 66.47 73.44
Table value = 64.13
PVT scale factor = 1.00
Delay = 64.13
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.98
| 11.52 23.04
v --------------------
40.00 | 17.99 31.89
80.00 | 17.98 31.88
Table value = 20.95
PVT scale factor = 1.00
Slew = 20.95
.............................................
dcalc r2 CLK->Q: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc sense: non_unate
Arc type: Reg Clk to Q
CLK ^ -> Q ^
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.40
| 11.52 23.04
v --------------------
40.00 | 64.09 71.91
80.00 | 69.26 77.08
Table value = 66.45
PVT scale factor = 1.00
Delay = 66.45
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.40
| 11.52 23.04
v --------------------
40.00 | 21.04 37.91
80.00 | 21.05 37.92
Table value = 23.79
PVT scale factor = 1.00
Slew = 23.79
.............................................
CLK ^ -> Q v
P = 1.00 V = 0.77 T = 0.00
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.40
| 11.52 23.04
v --------------------
40.00 | 61.63 68.60
80.00 | 66.47 73.44
Table value = 63.78
PVT scale factor = 1.00
Delay = 63.78
------- input_net_transition = 48.38
| total_output_net_capacitance = 13.40
| 11.52 23.04
v --------------------
40.00 | 17.99 31.89
80.00 | 17.98 31.88
Table value = 20.25
PVT scale factor = 1.00
Slew = 20.25
.............................................
dcalc r3 CLK->Q: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc type: setup
CLK ^ -> D ^
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 48.93
| related_pin_transition = 47.79
| 40.00 80.00
v --------------------
40.00 | 6.68 5.15
80.00 | 8.95 8.54
Table value = 6.94
PVT scale factor = 1.00
Check = 6.94
.............................................
CLK ^ -> D v
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 48.92
| related_pin_transition = 47.79
| 40.00 80.00
v --------------------
40.00 | -2.23 -7.76
80.00 | 5.88 -2.55
Table value = -1.62
PVT scale factor = 1.00
Check = -1.62
.............................................
dcalc r1 setup: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc type: hold
CLK ^ -> D ^
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 48.61
| related_pin_transition = 48.38
| 40.00 80.00
v --------------------
40.00 | -3.44 0.59
80.00 | -1.12 0.23
Table value = -2.22
PVT scale factor = 1.00
Check = -2.22
.............................................
CLK ^ -> D v
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 48.54
| related_pin_transition = 48.38
| 40.00 80.00
v --------------------
40.00 | 11.76 17.37
80.00 | 9.46 16.46
Table value = 12.51
PVT scale factor = 1.00
Check = 12.51
.............................................
dcalc r1 hold: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc type: setup
CLK ^ -> D ^
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 78.93
| related_pin_transition = 47.79
| 40.00 80.00
v --------------------
40.00 | 6.68 5.15
80.00 | 8.95 8.54
Table value = 8.80
PVT scale factor = 1.00
Check = 8.80
.............................................
CLK ^ -> D v
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 71.42
| related_pin_transition = 47.79
| 40.00 80.00
v --------------------
40.00 | -2.23 -7.76
80.00 | 5.88 -2.55
Table value = 2.62
PVT scale factor = 1.00
Check = 2.62
.............................................
dcalc r3 setup: done
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
Cell: DFFHQx4_ASAP7_75t_R
Arc type: hold
CLK ^ -> D ^
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 78.23
| related_pin_transition = 48.38
| 40.00 80.00
v --------------------
40.00 | -3.44 0.59
80.00 | -1.12 0.23
Table value = -0.92
PVT scale factor = 1.00
Check = -0.92
.............................................
CLK ^ -> D v
P = 1.00 V = 0.77 T = 0.00
------- constrained_pin_transition = 70.58
| related_pin_transition = 48.38
| 40.00 80.00
v --------------------
40.00 | 11.76 17.37
80.00 | 9.46 16.46
Table value = 11.40
PVT scale factor = 1.00
Check = 11.40
.............................................
dcalc r3 hold: done
PASS: dcalc reports
--- Test 3: varying slew ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
61.61 73.71 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 122.87 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 185.07 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 203.58 ^ r3/D (DFFHQx4_ASAP7_75t_R)
203.58 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-9.13 502.79 library setup time
502.79 data required time
---------------------------------------------------------
502.79 data required time
-203.58 data arrival time
---------------------------------------------------------
299.21 slack (MET)
arnoldi slew=0.1: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
61.78 73.89 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 123.04 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 185.25 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 203.76 ^ r3/D (DFFHQx4_ASAP7_75t_R)
203.76 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-9.03 502.89 library setup time
502.89 data required time
---------------------------------------------------------
502.89 data required time
-203.76 data arrival time
---------------------------------------------------------
299.13 slack (MET)
arnoldi slew=1: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.34 74.45 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 123.60 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 185.81 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.32 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.32 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.86 503.06 library setup time
503.06 data required time
---------------------------------------------------------
503.06 data required time
-204.32 data arrival time
---------------------------------------------------------
298.75 slack (MET)
arnoldi slew=5: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi slew=10: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
64.93 77.04 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 126.19 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 188.39 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 206.90 ^ r3/D (DFFHQx4_ASAP7_75t_R)
206.90 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.64 503.28 library setup time
503.28 data required time
---------------------------------------------------------
503.28 data required time
-206.90 data arrival time
---------------------------------------------------------
296.38 slack (MET)
arnoldi slew=25: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
67.78 79.89 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.14 129.04 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 191.24 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 209.75 ^ r3/D (DFFHQx4_ASAP7_75t_R)
209.75 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.37 503.55 library setup time
503.55 data required time
---------------------------------------------------------
503.55 data required time
-209.75 data arrival time
---------------------------------------------------------
293.80 slack (MET)
arnoldi slew=50: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
71.96 84.07 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.14 133.21 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 195.42 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 213.92 ^ r3/D (DFFHQx4_ASAP7_75t_R)
213.92 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-7.85 504.07 library setup time
504.07 data required time
---------------------------------------------------------
504.07 data required time
-213.92 data arrival time
---------------------------------------------------------
290.15 slack (MET)
arnoldi slew=100: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
77.80 89.91 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 139.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 201.26 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 219.77 ^ r3/D (DFFHQx4_ASAP7_75t_R)
219.77 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-6.83 505.09 library setup time
505.09 data required time
---------------------------------------------------------
505.09 data required time
-219.77 data arrival time
---------------------------------------------------------
285.32 slack (MET)
arnoldi slew=200: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
93.24 105.35 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.16 154.51 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 216.72 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 235.23 ^ r3/D (DFFHQx4_ASAP7_75t_R)
235.23 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-3.78 508.14 library setup time
508.14 data required time
---------------------------------------------------------
508.14 data required time
-235.23 data arrival time
---------------------------------------------------------
272.91 slack (MET)
arnoldi slew=500: done
PASS: varying slew
--- Test 4: varying load ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.00001: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.0001: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.001: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.005: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.01: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.05: done
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
arnoldi load=0.1: done
PASS: varying load
--- Test 5: re-read SPEF ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
PASS: arnoldi after re-read
--- Test 6: engine switch from arnoldi ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
201.72 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.46 503.46 library setup time
503.46 data required time
---------------------------------------------------------
503.46 data required time
-201.72 data arrival time
---------------------------------------------------------
301.74 slack (MET)
PASS: switch to dmp_ceff_elmore
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
PASS: back to arnoldi
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (propagated)
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
59.07 59.07 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
35.39 94.45 ^ u1/Y (BUFx2_ASAP7_75t_R)
47.16 141.62 ^ u2/Y (AND2x2_ASAP7_75t_R)
0.00 141.62 ^ r3/D (DFFHQx4_ASAP7_75t_R)
141.62 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (propagated)
0.00 500.00 clock reconvergence pessimism
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-10.20 489.80 library setup time
489.80 data required time
---------------------------------------------------------
489.80 data required time
-141.62 data arrival time
---------------------------------------------------------
348.18 slack (MET)
PASS: switch to lumped_cap
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
PASS: back to arnoldi again
--- Test 7: format options ---
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
-----------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
12.108056 12.108056 clock network delay (propagated)
0.000000 12.108056 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.991230 75.099289 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.150017 124.249306 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.204601 186.453903 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.507528 204.961441 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.961441 data arrival time
500.000000 500.000000 clock clk (rise edge)
11.920251 511.920227 clock network delay (propagated)
0.000000 511.920227 clock reconvergence pessimism
511.920227 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.804284 503.115936 library setup time
503.115936 data required time
-----------------------------------------------------------------
503.115936 data required time
-204.961441 data arrival time
-----------------------------------------------------------------
298.154510 slack (MET)
PASS: 6 digits
Warning: dcalc_arnoldi_spef.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
60.40 72.51 v r2/Q (DFFHQx4_ASAP7_75t_R)
50.40 122.91 v u1/Y (BUFx2_ASAP7_75t_R)
62.12 185.03 v u2/Y (AND2x2_ASAP7_75t_R)
18.40 203.42 v r3/D (DFFHQx4_ASAP7_75t_R)
203.42 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-2.62 509.30 library setup time
509.30 data required time
---------------------------------------------------------
509.30 data required time
-203.42 data arrival time
---------------------------------------------------------
305.88 slack (MET)
Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r1/Q (DFFHQx4_ASAP7_75t_R)
54.36 129.46 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 147.97 ^ r3/D (DFFHQx4_ASAP7_75t_R)
147.97 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-147.97 data arrival time
---------------------------------------------------------
355.15 slack (MET)
PASS: endpoint_count 3
Warning: dcalc_arnoldi_spef.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
204.96 data arrival time
500.00 500.00 clock clk (rise edge)
11.92 511.92 clock network delay (propagated)
0.00 511.92 clock reconvergence pessimism
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
-8.80 503.12 library setup time
503.12 data required time
---------------------------------------------------------
503.12 data required time
-204.96 data arrival time
---------------------------------------------------------
298.15 slack (MET)
Startpoint: r3 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
12.11 12.11 clock network delay (propagated)
0.00 12.11 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
62.96 75.07 ^ r3/Q (DFFHQx4_ASAP7_75t_R)
14.33 89.40 ^ out (out)
89.40 data arrival time
500.00 500.00 clock clk (rise edge)
0.00 500.00 clock network delay (ideal)
0.00 500.00 clock reconvergence pessimism
-1.00 499.00 output external delay
499.00 data required time
---------------------------------------------------------
499.00 data required time
-89.40 data arrival time
---------------------------------------------------------
409.60 slack (MET)
PASS: group_count 2
ALL PASSED
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