647 lines
21 KiB
Plaintext
647 lines
21 KiB
Plaintext
--- Test 1: baseline timing ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: baseline
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Startpoint: in4 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in4 (in)
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0.01 0.01 v nor1/ZN (NOR2_X1)
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0.00 0.01 v reg2/D (DFF_X1)
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0.01 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.01 data arrival time
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---------------------------------------------------------
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0.01 slack (MET)
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PASS: baseline min
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--- Test 2: incremental delay tolerance ---
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PASS: set tolerance 0.5
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No paths found.
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PASS: after slew change with large tolerance
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No paths found.
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PASS: after slew revert with large tolerance
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PASS: set tolerance 0.001
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No paths found.
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PASS: after slew change with small tolerance
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No paths found.
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PASS: after slew revert with small tolerance
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PASS: set tolerance 0.0
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--- Test 3: incremental load changes ---
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No paths found.
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load=0.0001: done
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No paths found.
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load=0.001: done
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No paths found.
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load=0.005: done
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No paths found.
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load=0.01: done
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No paths found.
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load=0.05: done
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No paths found.
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load=0.1: done
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No paths found.
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load=0.5: done
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: load on all outputs
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--- Test 4: incremental slew changes ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.02 0.02 v buf3/Z (BUF_X4)
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0.02 0.04 v and1/ZN (AND2_X1)
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0.05 0.10 v or1/ZN (OR2_X1)
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0.02 0.12 ^ nor1/ZN (NOR2_X1)
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0.00 0.12 ^ reg2/D (DFF_X1)
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0.12 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.12 data arrival time
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---------------------------------------------------------
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9.85 slack (MET)
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PASS: very fast slew
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: medium slew
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.44 0.44 v buf1/Z (BUF_X1)
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0.03 0.47 ^ inv1/ZN (INV_X1)
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0.02 0.49 ^ buf2/Z (BUF_X2)
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0.03 0.52 ^ or1/ZN (OR2_X1)
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0.01 0.53 v nor1/ZN (NOR2_X1)
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0.00 0.53 v reg2/D (DFF_X1)
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0.53 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.12 9.88 library setup time
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9.88 data required time
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---------------------------------------------------------
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9.88 data required time
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-0.53 data arrival time
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---------------------------------------------------------
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9.35 slack (MET)
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PASS: very slow slew
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Startpoint: in4 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in4 (in)
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0.24 0.24 ^ nor1/ZN (NOR2_X1)
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0.00 0.24 ^ reg2/D (DFF_X1)
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0.24 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.05 9.95 library setup time
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9.95 data required time
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---------------------------------------------------------
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9.95 data required time
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-0.24 data arrival time
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---------------------------------------------------------
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9.71 slack (MET)
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PASS: mixed slews
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--- Test 5: constraint changes ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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5.00 5.00 clock clk (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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5.00 ^ reg2/CK (DFF_X1)
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-0.04 4.96 library setup time
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4.96 data required time
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---------------------------------------------------------
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4.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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4.81 slack (MET)
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PASS: clock period 5
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg2/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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19.81 slack (MET)
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PASS: clock period 20
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No paths found.
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PASS: input_delay 2.0
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.00 0.08 ^ out1 (out)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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6.92 slack (MET)
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PASS: output_delay 3.0
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--- Test 6: network modification invalidation ---
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PASS: make_instance
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PASS: make_net
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PASS: connect_pin
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: report after add
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PASS: disconnect_pin
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PASS: cleanup
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: report after cleanup
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--- Test 7: replace cell ---
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No paths found.
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PASS: replace buf1 -> BUF_X4
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No paths found.
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PASS: replace buf1 -> BUF_X2
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No paths found.
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PASS: replace buf1 -> BUF_X1 (restore)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.02 0.08 v and1/ZN (AND2_X2)
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0.05 0.12 v or1/ZN (OR2_X2)
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0.02 0.14 ^ nor1/ZN (NOR2_X1)
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0.00 0.14 ^ reg2/D (DFF_X1)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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9.82 slack (MET)
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PASS: replace multiple cells
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: restore cells
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--- Test 8: tolerance with calculator switching ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: lumped_cap with tolerance
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: dmp_ceff_elmore with tolerance
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: dmp_ceff_two_pole with tolerance
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ in1 (in)
|
|
1.00 1.00 ^ buf1/Z (BUF_X1)
|
|
1.00 2.00 v inv1/ZN (INV_X1)
|
|
1.00 3.00 v buf2/Z (BUF_X2)
|
|
1.00 4.00 v or1/ZN (OR2_X1)
|
|
1.00 5.00 ^ nand1/ZN (NAND2_X1)
|
|
0.00 5.00 ^ reg1/D (DFF_X1)
|
|
5.00 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-1.00 9.00 library setup time
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-5.00 data arrival time
|
|
---------------------------------------------------------
|
|
4.00 slack (MET)
|
|
|
|
|
|
PASS: unit with tolerance
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: final report
|
|
ALL PASSED
|