277 lines
9.2 KiB
Tcl
277 lines
9.2 KiB
Tcl
# Test GraphDelayCalc with a larger design for coverage improvement.
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# Targets: GraphDelayCalc.cc (findDelays, seedRootSlews, seedInvalidDelays,
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# findVertexDelay, findCheckEdgeDelays, findLatchEdgeDelays,
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# findMultiDrvrNet, mergeMultiDrvrNets, loadDelay, netCaps,
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# hasMultiDrvrNet, reportCheckMultiDrvrNet, deleteVertexBefore,
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# levelChangedBefore, levelsChangedBefore, delayInvalid(pin/vertex),
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# setIncrementalDelayTolerance, incrementalDelayTolerance)
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# DmpCeff.cc (dmpCeffElmore, dmpCeffTwoPole paths with various loads)
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# NetCaps.cc (net capacitance queries, pinCapacitance, wireCap)
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# ArcDelayCalc.cc (arc delay for various gate types)
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# DelayCalcBase.cc (base class paths)
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog dcalc_multidriver_test.v
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link_design dcalc_multidriver_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3 in4 sel}]
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set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
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set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
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#---------------------------------------------------------------
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# Baseline timing (exercises findDelays, seedRootSlews)
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#---------------------------------------------------------------
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puts "--- baseline timing ---"
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report_checks
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puts "PASS: baseline report_checks"
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report_checks -path_delay min
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puts "PASS: baseline min path"
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report_checks -path_delay max
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puts "PASS: baseline max path"
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#---------------------------------------------------------------
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# Multiple from/to path queries (exercises findVertexDelay for many paths)
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#---------------------------------------------------------------
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puts "--- multiple path queries ---"
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: in1->out1"
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report_checks -from [get_ports in1] -to [get_ports out2]
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puts "PASS: in1->out2"
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report_checks -from [get_ports in1] -to [get_ports out3]
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puts "PASS: in1->out3"
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report_checks -from [get_ports in2] -to [get_ports out1]
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puts "PASS: in2->out1"
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report_checks -from [get_ports in2] -to [get_ports out2]
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puts "PASS: in2->out2"
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report_checks -from [get_ports in3] -to [get_ports out1]
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puts "PASS: in3->out1"
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report_checks -from [get_ports in4] -to [get_ports out2]
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puts "PASS: in4->out2"
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report_checks -from [get_ports sel] -to [get_ports out1]
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puts "PASS: sel->out1"
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#---------------------------------------------------------------
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# Through pin queries (exercises more graph traversal)
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#---------------------------------------------------------------
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puts "--- through pin queries ---"
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catch {report_checks -through [get_pins or1/ZN]} msg
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puts "PASS: through or1/ZN"
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catch {report_checks -through [get_pins nand1/ZN]} msg
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puts "PASS: through nand1/ZN"
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catch {report_checks -through [get_pins nor1/ZN]} msg
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puts "PASS: through nor1/ZN"
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catch {report_checks -through [get_pins and1/ZN]} msg
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puts "PASS: through and1/ZN"
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catch {report_checks -through [get_pins inv1/ZN]} msg
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puts "PASS: through inv1/ZN"
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#---------------------------------------------------------------
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# report_dcalc for all arc types in design
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# Exercises: arc delay computation for BUF, INV, AND, OR, NAND, NOR
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#---------------------------------------------------------------
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puts "--- report_dcalc various gate types ---"
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# BUF arcs
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
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puts "dcalc buf1 max: $msg"
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
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puts "dcalc buf1 min: $msg"
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# INV arcs
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catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
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puts "dcalc inv1 max: $msg"
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# AND arcs (both inputs)
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catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
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puts "dcalc and1 A1->ZN max: $msg"
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catch {report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max} msg
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puts "dcalc and1 A2->ZN max: $msg"
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# OR arcs
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catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
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puts "dcalc or1 A1->ZN max: $msg"
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catch {report_dcalc -from [get_pins or1/A2] -to [get_pins or1/ZN] -max} msg
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puts "dcalc or1 A2->ZN max: $msg"
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# NAND arcs
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catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
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puts "dcalc nand1 A1->ZN max: $msg"
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catch {report_dcalc -from [get_pins nand1/A2] -to [get_pins nand1/ZN] -max} msg
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puts "dcalc nand1 A2->ZN max: $msg"
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# NOR arcs
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catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
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puts "dcalc nor1 A1->ZN max: $msg"
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catch {report_dcalc -from [get_pins nor1/A2] -to [get_pins nor1/ZN] -max} msg
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puts "dcalc nor1 A2->ZN max: $msg"
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# DFF arcs
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
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puts "dcalc reg1 CK->Q max: $msg"
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
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puts "dcalc reg1 CK->Q min: $msg"
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# DFF check arcs
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
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puts "dcalc reg1 setup max: $msg"
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catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
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puts "dcalc reg1 hold min: $msg"
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catch {report_dcalc -from [get_pins reg2/CK] -to [get_pins reg2/Q] -max} msg
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puts "dcalc reg2 CK->Q max: $msg"
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catch {report_dcalc -from [get_pins reg2/CK] -to [get_pins reg2/D] -max} msg
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puts "dcalc reg2 setup max: $msg"
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# report_dcalc with -digits
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 2} msg
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puts "dcalc buf1 2 digits: $msg"
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 6} msg
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puts "dcalc buf1 6 digits: $msg"
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catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 10} msg
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puts "dcalc buf1 10 digits: $msg"
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#---------------------------------------------------------------
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# Incremental delay calculation: change constraints, recompute
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# Exercises: seedInvalidDelays, delayInvalid, incremental paths
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#---------------------------------------------------------------
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puts "--- incremental delay calculation ---"
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# Change loads
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set_load 0.001 [get_ports out1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after set_load 0.001 on out1"
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set_load 0.01 [get_ports out1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after set_load 0.01 on out1"
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set_load 0.1 [get_ports out1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after set_load 0.1 on out1"
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set_load 0.05 [get_ports out2]
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report_checks -from [get_ports in4] -to [get_ports out2]
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puts "PASS: incremental after set_load 0.05 on out2"
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# Reset loads
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set_load 0 [get_ports out1]
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set_load 0 [get_ports out2]
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# Change input transitions
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set_input_transition 0.01 [get_ports in1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after slew 0.01 on in1"
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set_input_transition 1.0 [get_ports in1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after slew 1.0 on in1"
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set_input_transition 0.1 [get_ports in1]
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# Change clock period
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create_clock -name clk -period 5 [get_ports clk]
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report_checks
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puts "PASS: incremental after clock period change to 5"
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# Change input/output delays
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set_input_delay -clock clk 1.0 [get_ports in1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after input_delay 1.0"
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set_output_delay -clock clk 2.0 [get_ports out1]
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report_checks -from [get_ports in1] -to [get_ports out1]
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puts "PASS: incremental after output_delay 2.0"
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#---------------------------------------------------------------
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# Test various delay calculators on larger design
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# Exercises: calculator switching, copy/init paths
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#---------------------------------------------------------------
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puts "--- calculator switching ---"
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set_delay_calculator unit
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report_checks
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puts "PASS: unit on large design"
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set_delay_calculator lumped_cap
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report_checks
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puts "PASS: lumped_cap on large design"
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set_delay_calculator dmp_ceff_elmore
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report_checks
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puts "PASS: dmp_ceff_elmore on large design"
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set_delay_calculator dmp_ceff_two_pole
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report_checks
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puts "PASS: dmp_ceff_two_pole on large design"
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catch {set_delay_calculator ccs_ceff} msg
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report_checks
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puts "PASS: ccs_ceff on large design"
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# Switch back to default
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set_delay_calculator dmp_ceff_elmore
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#---------------------------------------------------------------
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# report_checks with various formatting options
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#---------------------------------------------------------------
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puts "--- report_checks formatting ---"
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report_checks -fields {slew cap input_pins nets fanout}
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puts "PASS: report_checks with all fields"
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report_checks -format full_clock
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puts "PASS: report_checks full_clock"
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report_checks -format full_clock_expanded
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puts "PASS: report_checks full_clock_expanded"
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report_checks -endpoint_count 3
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puts "PASS: report_checks endpoint_count 3"
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report_checks -group_count 5
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puts "PASS: report_checks group_count 5"
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report_checks -unconstrained
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puts "PASS: report_checks unconstrained"
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report_checks -sort_by_slack
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puts "PASS: report_checks sort_by_slack"
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#---------------------------------------------------------------
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# report_check_types
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#---------------------------------------------------------------
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puts "--- report_check_types ---"
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report_check_types -max_delay -verbose
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puts "PASS: report_check_types max"
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report_check_types -min_delay -verbose
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puts "PASS: report_check_types min"
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report_check_types -max_delay -min_delay -verbose
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puts "PASS: report_check_types max+min"
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puts "ALL PASSED"
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