309 lines
6.7 KiB
Plaintext
309 lines
6.7 KiB
Plaintext
PASS: read sky130hd
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PASS: read Nangate45
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PASS: read ASAP7 SEQ
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PASS: read IHP
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--- Nangate45 cell classification ---
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BUF_X1 is_buffer = 1
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BUF_X1 is_inverter = 0
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BUF_X1 is_leaf = 1
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INV_X1 is_buffer = 0
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INV_X1 is_inverter = 1
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CLKGATETST_X1 is_buffer = 0
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CLKGATETST_X1 is_inverter = 0
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DFF_X1 is_buffer = 0
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DFF_X1 is_inverter = 0
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DFF_X1 is_leaf = 1
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SDFF_X1 test_cell = NULL
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PASS: Nangate45 classification
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--- port function queries ---
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INV_X1/ZN func=!A dir=output
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BUF_X1/Z func=A dir=output
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NAND2_X1/ZN func=!(A1*A2) dir=output
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NOR2_X1/ZN func=!(A1+A2) dir=output
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AND2_X1/ZN func=A1*A2 dir=output
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OR2_X1/ZN func=A1+A2 dir=output
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XOR2_X1/Z func=A^B dir=output
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XNOR2_X1/ZN func=!(A^B) dir=output
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AOI21_X1/ZN func=!(A+(B1*B2)) dir=output
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OAI21_X1/ZN func=!(A*(B1+B2)) dir=output
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MUX2_X1/Z func=(S*B)+(A*!S) dir=output
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HA_X1/CO func=A*B dir=output
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HA_X1/S func=A^B dir=output
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FA_X1/CO func=(A*B)+(CI*(A+B)) dir=output
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FA_X1/S func=CI^(A^B) dir=output
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PASS: port function queries
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--- bus port member iteration ---
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PASS: bus port member iteration
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--- port capacitance corner ---
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PASS: port capacitance corner
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--- timing arc sets ---
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INV_X1 arc_sets=1
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A -> ZN is_check=0
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rise -> fall
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fall -> rise
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BUF_X1 arc_sets=1
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A -> Z is_check=0
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rise -> rise
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fall -> fall
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DFF_X1 arc_sets=5
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CK -> D is_check=1
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rise -> rise
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rise -> fall
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CK -> D is_check=1
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rise -> rise
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rise -> fall
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CK -> CK is_check=1
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rise -> fall
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fall -> rise
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CK -> Q is_check=0
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rise -> rise
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rise -> fall
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CK -> QN is_check=0
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rise -> rise
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rise -> fall
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DFFR_X1 arc_sets=16
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CK -> D is_check=1
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rise -> rise
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rise -> fall
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CK -> D is_check=1
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rise -> rise
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rise -> fall
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CK -> RN is_check=1
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rise -> rise
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CK -> RN is_check=1
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rise -> rise
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RN -> RN is_check=1
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fall -> rise
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CK -> CK is_check=1
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rise -> fall
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fall -> rise
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CK -> Q is_check=0
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rise -> rise
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rise -> fall
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RN -> Q is_check=0
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fall -> fall
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RN -> Q is_check=0
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fall -> fall
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RN -> Q is_check=0
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fall -> fall
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RN -> Q is_check=0
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fall -> fall
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CK -> QN is_check=0
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rise -> rise
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rise -> fall
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RN -> QN is_check=0
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fall -> rise
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RN -> QN is_check=0
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fall -> rise
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RN -> QN is_check=0
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fall -> rise
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RN -> QN is_check=0
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fall -> rise
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NAND2_X1 arc_sets=2
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A1 -> ZN is_check=0
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rise -> fall
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fall -> rise
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A2 -> ZN is_check=0
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rise -> fall
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fall -> rise
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AOI21_X1 arc_sets=5
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A -> ZN is_check=0
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rise -> fall
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fall -> rise
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A -> ZN is_check=0
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rise -> fall
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fall -> rise
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A -> ZN is_check=0
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rise -> fall
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fall -> rise
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B1 -> ZN is_check=0
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rise -> fall
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fall -> rise
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B2 -> ZN is_check=0
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rise -> fall
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fall -> rise
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MUX2_X1 arc_sets=6
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A -> Z is_check=0
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rise -> rise
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fall -> fall
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A -> Z is_check=0
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rise -> rise
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fall -> fall
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B -> Z is_check=0
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rise -> rise
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fall -> fall
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B -> Z is_check=0
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rise -> rise
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fall -> fall
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S -> Z is_check=0
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rise -> rise
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fall -> fall
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S -> Z is_check=0
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rise -> fall
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fall -> rise
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SDFF_X1 arc_sets=9
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CK -> D is_check=1
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rise -> rise
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rise -> fall
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CK -> D is_check=1
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rise -> rise
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rise -> fall
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CK -> SE is_check=1
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rise -> rise
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rise -> fall
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CK -> SE is_check=1
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rise -> rise
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rise -> fall
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CK -> SI is_check=1
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rise -> rise
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rise -> fall
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CK -> SI is_check=1
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rise -> rise
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rise -> fall
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CK -> CK is_check=1
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rise -> fall
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fall -> rise
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CK -> Q is_check=0
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rise -> rise
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rise -> fall
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CK -> QN is_check=0
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rise -> rise
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rise -> fall
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CLKGATETST_X1 arc_sets=9
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CK -> CK is_check=1
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fall -> rise
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CK -> E is_check=1
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rise -> rise
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rise -> fall
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CK -> E is_check=1
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rise -> rise
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rise -> fall
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CK -> SE is_check=1
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rise -> rise
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rise -> fall
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CK -> SE is_check=1
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rise -> rise
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rise -> fall
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CK -> GCK is_check=0
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rise -> rise
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fall -> fall
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CK -> GCK is_check=0
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rise -> rise
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fall -> fall
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CK -> GCK is_check=0
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rise -> rise
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fall -> fall
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CK -> GCK is_check=0
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fall -> fall
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PASS: timing arc sets
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--- Sky130 cell queries ---
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sky130_fd_sc_hd__inv_1 is_buffer=0 is_inverter=1
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__inv_2 is_buffer=0 is_inverter=1
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__inv_4 is_buffer=0 is_inverter=1
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__buf_1 is_buffer=1 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__buf_2 is_buffer=1 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__nand2_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__nor2_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__and2_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__or2_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__dfxtp_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__dfrtp_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__mux2_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__dlxtp_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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sky130_fd_sc_hd__ebufn_1 is_buffer=0 is_inverter=0
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VGND pwr_gnd=1
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VNB pwr_gnd=1
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VPB pwr_gnd=1
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VPWR pwr_gnd=1
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PASS: Sky130 cell queries
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--- operating conditions ---
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Sky130 default OC process=1.0 voltage=1.7999999523162842 temp=25.0
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PASS: operating conditions
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--- IHP cell queries ---
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sg13g2_inv_1 is_buffer=0 is_inverter=1
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arc_sets=1
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sg13g2_inv_2 is_buffer=0 is_inverter=1
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arc_sets=1
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sg13g2_buf_1 is_buffer=1 is_inverter=0
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arc_sets=1
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sg13g2_buf_2 is_buffer=1 is_inverter=0
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arc_sets=1
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sg13g2_nand2_1 is_buffer=0 is_inverter=0
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arc_sets=2
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sg13g2_nor2_1 is_buffer=0 is_inverter=0
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arc_sets=2
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sg13g2_and2_1 is_buffer=0 is_inverter=0
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arc_sets=2
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sg13g2_dfrbp_1 is_buffer=0 is_inverter=0
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arc_sets=10
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sg13g2_dfrbp_2 is_buffer=0 is_inverter=0
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arc_sets=10
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sg13g2_ebufn_2 is_buffer=0 is_inverter=0
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arc_sets=3
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PASS: IHP cell queries
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--- ensure voltage waveforms ---
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PASS: INV_X1 ensure_voltage_waveforms
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PASS: DFF_X1 ensure_voltage_waveforms
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PASS: ensure voltage waveforms
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--- liberty cell matching ---
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INV_* matches = 6
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DFF* matches = 8
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* matches = 134
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regex INV_X matches = 6
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INV_X1 port * matches = 4
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INV_X1 port A matches = 1
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PASS: liberty cell matching
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ALL PASSED
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