test: Apply review feedback - part1
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
This commit is contained in:
Jaehyun Kim
parent
fdb24d8132
commit
6799b1909a
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@ -4138,4 +4138,750 @@ TEST_F(DesignDcalcTest, LevelChangedBefore) {
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}
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}
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////////////////////////////////////////////////////////////////
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// NangateDcalcTest - Loads Nangate45 + dcalc_test1.v (BUF->INV->DFF chain)
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class NangateDcalcTest : public ::testing::Test {
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protected:
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void SetUp() override {
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interp_ = Tcl_CreateInterp();
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initSta();
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sta_ = new Sta;
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Sta::setSta(sta_);
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sta_->makeComponents();
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ReportTcl *report = dynamic_cast<ReportTcl*>(sta_->report());
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if (report)
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report->setTclInterp(interp_);
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registerDelayCalcs();
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Corner *corner = sta_->cmdCorner();
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const MinMaxAll *min_max = MinMaxAll::all();
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LibertyLibrary *lib = sta_->readLiberty(
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"test/nangate45/Nangate45_typ.lib", corner, min_max, false);
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ASSERT_NE(lib, nullptr);
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bool ok = sta_->readVerilog("dcalc/test/dcalc_test1.v");
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ASSERT_TRUE(ok);
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ok = sta_->linkDesign("dcalc_test1", true);
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ASSERT_TRUE(ok);
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// Create clock and set constraints
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Pin *clk_pin = network->findPin(top, "clk");
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ASSERT_NE(clk_pin, nullptr);
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PinSet *clk_pins = new PinSet(network);
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clk_pins->insert(clk_pin);
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FloatSeq *waveform = new FloatSeq;
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waveform->push_back(0.0f);
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waveform->push_back(5.0f);
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sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
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// Set input/output delay constraints to create constrained timing paths
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Clock *clk = sta_->sdc()->findClock("clk");
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ASSERT_NE(clk, nullptr);
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Pin *in1_pin = network->findPin(top, "in1");
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ASSERT_NE(in1_pin, nullptr);
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sta_->setInputDelay(in1_pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 0.0f);
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Pin *out1_pin = network->findPin(top, "out1");
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ASSERT_NE(out1_pin, nullptr);
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sta_->setOutputDelay(out1_pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 0.0f);
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design_loaded_ = true;
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}
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void TearDown() override {
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deleteDelayCalcs();
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deleteAllMemory();
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sta_ = nullptr;
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if (interp_) Tcl_DeleteInterp(interp_);
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interp_ = nullptr;
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}
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Sta *sta_;
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Tcl_Interp *interp_;
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bool design_loaded_ = false;
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};
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// Run updateTiming with each calculator, verify all complete without crash
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// and graph has delays.
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TEST_F(NangateDcalcTest, TimingAllCalcsNangate) {
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EXPECT_TRUE(design_loaded_);
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const char *calcs[] = {"unit", "lumped_cap", "dmp_ceff_elmore",
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"dmp_ceff_two_pole", "ccs_ceff"};
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for (const char *name : calcs) {
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sta_->setArcDelayCalc(name);
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sta_->updateTiming(true);
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Graph *graph = sta_->graph();
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ASSERT_NE(graph, nullptr);
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EXPECT_GT(graph->vertexCount(), 0);
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}
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}
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// Set various loads on output, run dmp_ceff_elmore for each, verify slack changes.
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TEST_F(NangateDcalcTest, DmpExtremeLoads) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *out_port = network->findPort(top_cell, "out1");
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ASSERT_NE(out_port, nullptr);
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Corner *corner = sta_->cmdCorner();
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float loads[] = {0.00001f, 0.1f, 1.0f, 5.0f, 10.0f};
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Slack prev_slack = 0.0f;
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bool first = true;
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for (float load : loads) {
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sta_->setPortExtPinCap(out_port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), load);
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sta_->updateTiming(true);
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Slack slack = sta_->worstSlack(MinMax::max());
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if (!first) {
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// With increasing load, slack should generally decrease (become worse)
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// but we just verify it's a valid number and changes
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EXPECT_TRUE(slack != prev_slack || load == loads[0]);
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}
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prev_slack = slack;
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first = false;
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}
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}
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// Set various input transitions via setInputSlew, verify timing completes.
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TEST_F(NangateDcalcTest, DmpExtremeSlews) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *in_port = network->findPort(top_cell, "in1");
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ASSERT_NE(in_port, nullptr);
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float slews[] = {0.0001f, 0.1f, 5.0f, 10.0f};
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for (float slew : slews) {
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sta_->setInputSlew(in_port, RiseFallBoth::riseFall(),
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MinMaxAll::all(), slew);
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sta_->updateTiming(true);
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SUCCEED();
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}
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}
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// Large load + fast slew, tiny load + slow slew combinations.
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TEST_F(NangateDcalcTest, DmpCombinedExtremes) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *out_port = network->findPort(top_cell, "out1");
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const Port *in_port = network->findPort(top_cell, "in1");
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ASSERT_NE(out_port, nullptr);
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ASSERT_NE(in_port, nullptr);
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Corner *corner = sta_->cmdCorner();
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// Large load + fast slew
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sta_->setPortExtPinCap(out_port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), 10.0f);
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sta_->setInputSlew(in_port, RiseFallBoth::riseFall(),
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MinMaxAll::all(), 0.0001f);
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sta_->updateTiming(true);
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Slack slack1 = sta_->worstSlack(MinMax::max());
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// Tiny load + slow slew
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sta_->setPortExtPinCap(out_port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), 0.00001f);
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sta_->setInputSlew(in_port, RiseFallBoth::riseFall(),
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MinMaxAll::all(), 10.0f);
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sta_->updateTiming(true);
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Slack slack2 = sta_->worstSlack(MinMax::max());
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// Just verify both complete and produce different slacks
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EXPECT_NE(slack1, slack2);
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}
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// Same as DmpExtremeLoads but with dmp_ceff_two_pole.
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TEST_F(NangateDcalcTest, TwoPoleExtremeLoads) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_two_pole");
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *out_port = network->findPort(top_cell, "out1");
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ASSERT_NE(out_port, nullptr);
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Corner *corner = sta_->cmdCorner();
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float loads[] = {0.00001f, 0.1f, 1.0f, 5.0f, 10.0f};
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for (float load : loads) {
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sta_->setPortExtPinCap(out_port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), load);
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sta_->updateTiming(true);
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SUCCEED();
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}
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}
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// Switch calculator from dmp_ceff_elmore->lumped_cap->unit->dmp_ceff_two_pole,
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// verify timing works at each switch.
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TEST_F(NangateDcalcTest, CalcSwitchingIncremental) {
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EXPECT_TRUE(design_loaded_);
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const char *calcs[] = {"dmp_ceff_elmore", "lumped_cap", "unit",
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"dmp_ceff_two_pole"};
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for (const char *name : calcs) {
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sta_->setArcDelayCalc(name);
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sta_->updateTiming(true);
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Graph *graph = sta_->graph();
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ASSERT_NE(graph, nullptr);
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EXPECT_GT(graph->vertexCount(), 0);
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}
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}
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// Set ccs_ceff (falls back to table-based for NLDM), verify timing works.
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TEST_F(NangateDcalcTest, CcsWithNldmFallback) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("ccs_ceff");
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sta_->updateTiming(true);
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Graph *graph = sta_->graph();
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ASSERT_NE(graph, nullptr);
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EXPECT_GT(graph->vertexCount(), 0);
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Slack slack = sta_->worstSlack(MinMax::max());
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// CCS with NLDM fallback should still produce valid timing
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(void)slack;
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SUCCEED();
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}
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// Set ccs_ceff, change load, verify incremental timing.
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TEST_F(NangateDcalcTest, CcsIncrementalLoadChange) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("ccs_ceff");
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sta_->updateTiming(true);
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Slack slack1 = sta_->worstSlack(MinMax::max());
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *out_port = network->findPort(top_cell, "out1");
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ASSERT_NE(out_port, nullptr);
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Corner *corner = sta_->cmdCorner();
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sta_->setPortExtPinCap(out_port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), 5.0f);
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sta_->updateTiming(false);
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Slack slack2 = sta_->worstSlack(MinMax::max());
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// With large load, slack should change
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EXPECT_NE(slack1, slack2);
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}
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////////////////////////////////////////////////////////////////
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// MultiDriverDcalcTest - Loads Nangate45 + dcalc_multidriver_test.v
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class MultiDriverDcalcTest : public ::testing::Test {
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protected:
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void SetUp() override {
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interp_ = Tcl_CreateInterp();
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initSta();
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sta_ = new Sta;
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Sta::setSta(sta_);
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sta_->makeComponents();
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ReportTcl *report = dynamic_cast<ReportTcl*>(sta_->report());
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if (report)
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report->setTclInterp(interp_);
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registerDelayCalcs();
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Corner *corner = sta_->cmdCorner();
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const MinMaxAll *min_max = MinMaxAll::all();
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LibertyLibrary *lib = sta_->readLiberty(
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"test/nangate45/Nangate45_typ.lib", corner, min_max, false);
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ASSERT_NE(lib, nullptr);
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bool ok = sta_->readVerilog("dcalc/test/dcalc_multidriver_test.v");
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ASSERT_TRUE(ok);
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ok = sta_->linkDesign("dcalc_multidriver_test", true);
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ASSERT_TRUE(ok);
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// Create clock
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Pin *clk_pin = network->findPin(top, "clk");
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ASSERT_NE(clk_pin, nullptr);
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PinSet *clk_pins = new PinSet(network);
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clk_pins->insert(clk_pin);
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FloatSeq *waveform = new FloatSeq;
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waveform->push_back(0.0f);
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waveform->push_back(5.0f);
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sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
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Clock *clk = sta_->sdc()->findClock("clk");
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ASSERT_NE(clk, nullptr);
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// Set input delays on in1-in4, sel
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Cell *top_cell = network->cell(top);
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const char *input_ports[] = {"in1", "in2", "in3", "in4", "sel"};
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for (const char *pname : input_ports) {
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const Port *port = network->findPort(top_cell, pname);
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if (port) {
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sta_->setInputSlew(port, RiseFallBoth::riseFall(),
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MinMaxAll::all(), 0.1f);
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// Also set SDC input delay to constrain the path
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Pin *pin = network->findPin(top, pname);
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if (pin) {
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sta_->setInputDelay(pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 0.0f);
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}
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}
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}
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// Set output loads and output delays on out1-out3
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const char *output_ports[] = {"out1", "out2", "out3"};
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for (const char *pname : output_ports) {
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const Port *port = network->findPort(top_cell, pname);
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if (port) {
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sta_->setPortExtPinCap(port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), 0.01f);
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Pin *pin = network->findPin(top, pname);
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if (pin) {
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sta_->setOutputDelay(pin, RiseFallBoth::riseFall(), clk,
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RiseFall::rise(), nullptr, false, false,
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MinMaxAll::all(), false, 0.0f);
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}
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}
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}
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design_loaded_ = true;
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}
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void TearDown() override {
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deleteDelayCalcs();
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deleteAllMemory();
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sta_ = nullptr;
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if (interp_) Tcl_DeleteInterp(interp_);
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interp_ = nullptr;
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}
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Sta *sta_;
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Tcl_Interp *interp_;
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bool design_loaded_ = false;
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};
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// updateTiming, query paths from each input to each output, verify graph has paths.
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TEST_F(MultiDriverDcalcTest, AllPathQueries) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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sta_->updateTiming(true);
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Graph *graph = sta_->graph();
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ASSERT_NE(graph, nullptr);
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EXPECT_GT(graph->vertexCount(), 10);
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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// Verify output pins have vertices
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const char *out_names[] = {"out1", "out2", "out3"};
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for (const char *name : out_names) {
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Pin *pin = network->findPin(top, name);
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ASSERT_NE(pin, nullptr);
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Vertex *v = graph->pinDrvrVertex(pin);
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EXPECT_NE(v, nullptr);
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}
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}
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// Sweep loads 0.001->0.1 on out1, verify delays change monotonically.
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TEST_F(MultiDriverDcalcTest, DmpCeffLoadSweep) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *out_port = network->findPort(top_cell, "out1");
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ASSERT_NE(out_port, nullptr);
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Corner *corner = sta_->cmdCorner();
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float loads[] = {0.001f, 0.005f, 0.01f, 0.05f, 0.1f};
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Slack prev_slack = 1e30f; // Start with large positive value
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for (float load : loads) {
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sta_->setPortExtPinCap(out_port, RiseFallBoth::riseFall(),
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corner, MinMaxAll::all(), load);
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sta_->updateTiming(true);
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Slack slack = sta_->worstSlack(MinMax::max());
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// With increasing load, slack should decrease (more negative = worse)
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EXPECT_LE(slack, prev_slack + 1e-6f);
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prev_slack = slack;
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}
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}
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// Set large tolerance (0.5), change slew, verify timing completes.
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TEST_F(MultiDriverDcalcTest, IncrementalToleranceLarge) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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sta_->setIncrementalDelayTolerance(0.5f);
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sta_->updateTiming(true);
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *in_port = network->findPort(top_cell, "in1");
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ASSERT_NE(in_port, nullptr);
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sta_->setInputSlew(in_port, RiseFallBoth::riseFall(),
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MinMaxAll::all(), 0.5f);
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sta_->updateTiming(false);
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SUCCEED();
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}
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// Set small tolerance (0.001), change slew, verify timing recomputes.
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TEST_F(MultiDriverDcalcTest, IncrementalToleranceSmall) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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sta_->setIncrementalDelayTolerance(0.001f);
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sta_->updateTiming(true);
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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const Port *in_port = network->findPort(top_cell, "in1");
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ASSERT_NE(in_port, nullptr);
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sta_->setInputSlew(in_port, RiseFallBoth::riseFall(),
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MinMaxAll::all(), 0.5f);
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sta_->updateTiming(false);
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SUCCEED();
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}
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// Set loads on multiple outputs, verify incremental update works.
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TEST_F(MultiDriverDcalcTest, IncrementalLoadChanges) {
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EXPECT_TRUE(design_loaded_);
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sta_->setArcDelayCalc("dmp_ceff_elmore");
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sta_->updateTiming(true);
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Network *network = sta_->network();
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Instance *top = network->topInstance();
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Cell *top_cell = network->cell(top);
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Corner *corner = sta_->cmdCorner();
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const char *output_ports[] = {"out1", "out2", "out3"};
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for (const char *pname : output_ports) {
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const Port *port = network->findPort(top_cell, pname);
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ASSERT_NE(port, nullptr);
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sta_->setPortExtPinCap(port, RiseFallBoth::riseFall(),
|
||||
corner, MinMaxAll::all(), 1.0f);
|
||||
}
|
||||
sta_->updateTiming(false);
|
||||
|
||||
Slack slack = sta_->worstSlack(MinMax::max());
|
||||
(void)slack;
|
||||
SUCCEED();
|
||||
}
|
||||
|
||||
// Change clock period, verify timing updates.
|
||||
TEST_F(MultiDriverDcalcTest, IncrementalClockPeriodChange) {
|
||||
EXPECT_TRUE(design_loaded_);
|
||||
sta_->setArcDelayCalc("dmp_ceff_elmore");
|
||||
sta_->updateTiming(true);
|
||||
Slack slack1 = sta_->worstSlack(MinMax::max());
|
||||
|
||||
// Create new clock with different period
|
||||
Network *network = sta_->network();
|
||||
Instance *top = network->topInstance();
|
||||
Pin *clk_pin = network->findPin(top, "clk");
|
||||
ASSERT_NE(clk_pin, nullptr);
|
||||
PinSet *clk_pins = new PinSet(network);
|
||||
clk_pins->insert(clk_pin);
|
||||
FloatSeq *waveform = new FloatSeq;
|
||||
waveform->push_back(0.0f);
|
||||
waveform->push_back(1.0f);
|
||||
sta_->makeClock("clk", clk_pins, false, 2.0f, waveform, nullptr);
|
||||
sta_->updateTiming(true);
|
||||
Slack slack2 = sta_->worstSlack(MinMax::max());
|
||||
|
||||
// Tighter clock => smaller (worse) slack
|
||||
EXPECT_NE(slack1, slack2);
|
||||
}
|
||||
|
||||
// Replace buf1 with BUF_X4, verify timing completes, replace back.
|
||||
TEST_F(MultiDriverDcalcTest, ReplaceCellIncremental) {
|
||||
EXPECT_TRUE(design_loaded_);
|
||||
sta_->setArcDelayCalc("dmp_ceff_elmore");
|
||||
sta_->updateTiming(true);
|
||||
|
||||
Network *network = sta_->network();
|
||||
Instance *top = network->topInstance();
|
||||
Instance *buf1 = network->findChild(top, "buf1");
|
||||
ASSERT_NE(buf1, nullptr);
|
||||
|
||||
LibertyCell *buf_x4 = network->findLibertyCell("BUF_X4");
|
||||
ASSERT_NE(buf_x4, nullptr);
|
||||
|
||||
LibertyCell *buf_x1 = network->findLibertyCell("BUF_X1");
|
||||
ASSERT_NE(buf_x1, nullptr);
|
||||
|
||||
// Check vertex delay on buf1 output before replacement
|
||||
Graph *graph = sta_->graph();
|
||||
Pin *buf1_z = network->findPin(buf1, "Z");
|
||||
ASSERT_NE(buf1_z, nullptr);
|
||||
Vertex *v1 = graph->pinDrvrVertex(buf1_z);
|
||||
ASSERT_NE(v1, nullptr);
|
||||
|
||||
sta_->replaceCell(buf1, buf_x4);
|
||||
sta_->updateTiming(true);
|
||||
|
||||
// Verify timing completes after replacement
|
||||
graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
|
||||
// Replace back to original
|
||||
sta_->replaceCell(buf1, buf_x1);
|
||||
sta_->updateTiming(true);
|
||||
|
||||
graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
SUCCEED();
|
||||
}
|
||||
|
||||
// Switch through all 5 calculators, verify timing at each.
|
||||
TEST_F(MultiDriverDcalcTest, CalcSwitchAllEngines) {
|
||||
EXPECT_TRUE(design_loaded_);
|
||||
const char *calcs[] = {"unit", "lumped_cap", "dmp_ceff_elmore",
|
||||
"dmp_ceff_two_pole", "ccs_ceff"};
|
||||
for (const char *name : calcs) {
|
||||
sta_->setArcDelayCalc(name);
|
||||
sta_->updateTiming(true);
|
||||
Graph *graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
}
|
||||
}
|
||||
|
||||
// Call findDelays() directly, invalidate, call again.
|
||||
TEST_F(MultiDriverDcalcTest, FindDelaysExplicit) {
|
||||
EXPECT_TRUE(design_loaded_);
|
||||
sta_->setArcDelayCalc("dmp_ceff_elmore");
|
||||
sta_->findDelays();
|
||||
Graph *graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
|
||||
// Change something and call findDelays again
|
||||
Network *network = sta_->network();
|
||||
Instance *top = network->topInstance();
|
||||
Cell *top_cell = network->cell(top);
|
||||
const Port *in_port = network->findPort(top_cell, "in1");
|
||||
ASSERT_NE(in_port, nullptr);
|
||||
sta_->setInputSlew(in_port, RiseFallBoth::riseFall(),
|
||||
MinMaxAll::all(), 1.0f);
|
||||
sta_->findDelays();
|
||||
SUCCEED();
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// MultiCornerDcalcTest - Loads Nangate45 fast/slow + dcalc_test1.v
|
||||
|
||||
class MultiCornerDcalcTest : public ::testing::Test {
|
||||
protected:
|
||||
void SetUp() override {
|
||||
interp_ = Tcl_CreateInterp();
|
||||
initSta();
|
||||
sta_ = new Sta;
|
||||
Sta::setSta(sta_);
|
||||
sta_->makeComponents();
|
||||
ReportTcl *report = dynamic_cast<ReportTcl*>(sta_->report());
|
||||
if (report)
|
||||
report->setTclInterp(interp_);
|
||||
registerDelayCalcs();
|
||||
|
||||
// Define corners
|
||||
StringSet corner_names;
|
||||
corner_names.insert("fast");
|
||||
corner_names.insert("slow");
|
||||
sta_->makeCorners(&corner_names);
|
||||
|
||||
Corner *fast_corner = sta_->findCorner("fast");
|
||||
Corner *slow_corner = sta_->findCorner("slow");
|
||||
ASSERT_NE(fast_corner, nullptr);
|
||||
ASSERT_NE(slow_corner, nullptr);
|
||||
|
||||
const MinMaxAll *min_max = MinMaxAll::all();
|
||||
|
||||
LibertyLibrary *fast_lib = sta_->readLiberty(
|
||||
"test/nangate45/Nangate45_fast.lib", fast_corner, min_max, false);
|
||||
ASSERT_NE(fast_lib, nullptr);
|
||||
|
||||
LibertyLibrary *slow_lib = sta_->readLiberty(
|
||||
"test/nangate45/Nangate45_slow.lib", slow_corner, min_max, false);
|
||||
ASSERT_NE(slow_lib, nullptr);
|
||||
|
||||
bool ok = sta_->readVerilog("dcalc/test/dcalc_test1.v");
|
||||
ASSERT_TRUE(ok);
|
||||
ok = sta_->linkDesign("dcalc_test1", true);
|
||||
ASSERT_TRUE(ok);
|
||||
|
||||
// Create clock
|
||||
Network *network = sta_->network();
|
||||
Instance *top = network->topInstance();
|
||||
Pin *clk_pin = network->findPin(top, "clk");
|
||||
ASSERT_NE(clk_pin, nullptr);
|
||||
PinSet *clk_pins = new PinSet(network);
|
||||
clk_pins->insert(clk_pin);
|
||||
FloatSeq *waveform = new FloatSeq;
|
||||
waveform->push_back(0.0f);
|
||||
waveform->push_back(5.0f);
|
||||
sta_->makeClock("clk", clk_pins, false, 10.0f, waveform, nullptr);
|
||||
|
||||
// Set input/output delay constraints to create constrained timing paths
|
||||
Clock *clk = sta_->sdc()->findClock("clk");
|
||||
ASSERT_NE(clk, nullptr);
|
||||
|
||||
Pin *in1_pin = network->findPin(top, "in1");
|
||||
ASSERT_NE(in1_pin, nullptr);
|
||||
sta_->setInputDelay(in1_pin, RiseFallBoth::riseFall(), clk,
|
||||
RiseFall::rise(), nullptr, false, false,
|
||||
MinMaxAll::all(), false, 0.0f);
|
||||
|
||||
Pin *out1_pin = network->findPin(top, "out1");
|
||||
ASSERT_NE(out1_pin, nullptr);
|
||||
sta_->setOutputDelay(out1_pin, RiseFallBoth::riseFall(), clk,
|
||||
RiseFall::rise(), nullptr, false, false,
|
||||
MinMaxAll::all(), false, 0.0f);
|
||||
|
||||
design_loaded_ = true;
|
||||
}
|
||||
void TearDown() override {
|
||||
deleteDelayCalcs();
|
||||
deleteAllMemory();
|
||||
sta_ = nullptr;
|
||||
if (interp_) Tcl_DeleteInterp(interp_);
|
||||
interp_ = nullptr;
|
||||
}
|
||||
Sta *sta_;
|
||||
Tcl_Interp *interp_;
|
||||
bool design_loaded_ = false;
|
||||
};
|
||||
|
||||
// Verify timing with both corners produces valid results and
|
||||
// that the slow corner does not have better slack than the fast corner.
|
||||
TEST_F(MultiCornerDcalcTest, TimingDiffersPerCorner) {
|
||||
EXPECT_TRUE(design_loaded_);
|
||||
sta_->setArcDelayCalc("dmp_ceff_elmore");
|
||||
sta_->updateTiming(true);
|
||||
|
||||
Corner *fast_corner = sta_->findCorner("fast");
|
||||
Corner *slow_corner = sta_->findCorner("slow");
|
||||
ASSERT_NE(fast_corner, nullptr);
|
||||
ASSERT_NE(slow_corner, nullptr);
|
||||
|
||||
Slack fast_slack, slow_slack;
|
||||
Vertex *fast_vertex, *slow_vertex;
|
||||
sta_->worstSlack(fast_corner, MinMax::max(), fast_slack, fast_vertex);
|
||||
sta_->worstSlack(slow_corner, MinMax::max(), slow_slack, slow_vertex);
|
||||
|
||||
// Both corners should produce valid slack (not infinity)
|
||||
EXPECT_LT(fast_slack, 1e29f);
|
||||
EXPECT_LT(slow_slack, 1e29f);
|
||||
|
||||
// Fast corner should have slack >= slow corner (better or equal)
|
||||
EXPECT_GE(fast_slack, slow_slack);
|
||||
}
|
||||
|
||||
// Run each calculator with multi-corner, verify completes.
|
||||
TEST_F(MultiCornerDcalcTest, AllCalcsMultiCorner) {
|
||||
EXPECT_TRUE(design_loaded_);
|
||||
const char *calcs[] = {"unit", "lumped_cap", "dmp_ceff_elmore",
|
||||
"dmp_ceff_two_pole", "ccs_ceff"};
|
||||
for (const char *name : calcs) {
|
||||
sta_->setArcDelayCalc(name);
|
||||
sta_->updateTiming(true);
|
||||
Graph *graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Additional DesignDcalcTest tests for SPEF-based scenarios
|
||||
|
||||
// Run all delay calculators with SPEF loaded.
|
||||
TEST_F(DesignDcalcTest, TimingAllCalcsWithSpef) {
|
||||
ASSERT_TRUE(design_loaded_);
|
||||
const char *calcs[] = {"unit", "lumped_cap", "dmp_ceff_elmore",
|
||||
"dmp_ceff_two_pole", "arnoldi", "ccs_ceff", "prima"};
|
||||
for (const char *name : calcs) {
|
||||
sta_->setArcDelayCalc(name);
|
||||
sta_->updateTiming(true);
|
||||
Graph *graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
}
|
||||
}
|
||||
|
||||
// Set prima reduce order 1,2,3,4,5, verify each completes.
|
||||
TEST_F(DesignDcalcTest, PrimaReduceOrderVariation) {
|
||||
ASSERT_TRUE(design_loaded_);
|
||||
sta_->setArcDelayCalc("prima");
|
||||
|
||||
ArcDelayCalc *calc = sta_->arcDelayCalc();
|
||||
ASSERT_NE(calc, nullptr);
|
||||
PrimaDelayCalc *prima = dynamic_cast<PrimaDelayCalc*>(calc);
|
||||
ASSERT_NE(prima, nullptr);
|
||||
|
||||
size_t orders[] = {1, 2, 3, 4, 5};
|
||||
for (size_t order : orders) {
|
||||
prima->setPrimaReduceOrder(order);
|
||||
sta_->updateTiming(true);
|
||||
SUCCEED();
|
||||
}
|
||||
}
|
||||
|
||||
// Change load, slew, clock period with SPEF, verify updates.
|
||||
TEST_F(DesignDcalcTest, IncrementalWithSpef) {
|
||||
ASSERT_TRUE(design_loaded_);
|
||||
sta_->setArcDelayCalc("dmp_ceff_elmore");
|
||||
sta_->updateTiming(true);
|
||||
Slack slack1 = sta_->worstSlack(MinMax::max());
|
||||
|
||||
// Change clock period
|
||||
Network *network = sta_->network();
|
||||
Instance *top = network->topInstance();
|
||||
Pin *clk1 = network->findPin(top, "clk1");
|
||||
Pin *clk2 = network->findPin(top, "clk2");
|
||||
Pin *clk3 = network->findPin(top, "clk3");
|
||||
PinSet *clk_pins = new PinSet(network);
|
||||
clk_pins->insert(clk1);
|
||||
clk_pins->insert(clk2);
|
||||
clk_pins->insert(clk3);
|
||||
FloatSeq *waveform = new FloatSeq;
|
||||
waveform->push_back(0.0f);
|
||||
waveform->push_back(50.0f);
|
||||
sta_->makeClock("clk", clk_pins, false, 100.0f, waveform, nullptr);
|
||||
sta_->updateTiming(true);
|
||||
Slack slack2 = sta_->worstSlack(MinMax::max());
|
||||
|
||||
// Tighter clock => different slack
|
||||
EXPECT_NE(slack1, slack2);
|
||||
}
|
||||
|
||||
// Rapidly switch between all calcs with SPEF loaded.
|
||||
TEST_F(DesignDcalcTest, RapidCalcSwitchingSpef) {
|
||||
ASSERT_TRUE(design_loaded_);
|
||||
const char *calcs[] = {"dmp_ceff_elmore", "lumped_cap", "unit",
|
||||
"dmp_ceff_two_pole", "arnoldi", "ccs_ceff",
|
||||
"prima", "dmp_ceff_elmore", "ccs_ceff"};
|
||||
for (const char *name : calcs) {
|
||||
sta_->setArcDelayCalc(name);
|
||||
sta_->updateTiming(true);
|
||||
Graph *graph = sta_->graph();
|
||||
ASSERT_NE(graph, nullptr);
|
||||
EXPECT_GT(graph->vertexCount(), 0);
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace sta
|
||||
|
|
|
|||
|
|
@ -7,6 +7,10 @@ namespace sta {
|
|||
|
||||
class FindRootTest : public ::testing::Test {};
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Original 7 tests
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Test finding root of f(x) = x^2 - 4 (root at x=2)
|
||||
TEST_F(FindRootTest, QuadraticPositiveRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
|
|
@ -92,4 +96,572 @@ TEST_F(FindRootTest, WithPrecomputedY) {
|
|||
EXPECT_NEAR(root, 3.0, 1e-8);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Tolerance edge cases
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Very tight tolerance: 1e-15 (near machine epsilon)
|
||||
TEST_F(FindRootTest, VeryTightTolerance) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 5.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 3.0, 7.0, 1e-15, 500, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 5.0, 1e-13);
|
||||
}
|
||||
|
||||
// Very loose tolerance: 1e-1
|
||||
TEST_F(FindRootTest, LooseTolerance) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 25.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 3.0, 7.0, 1e-1, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
// With 10% relative tolerance, result should still be in the right ballpark
|
||||
EXPECT_NEAR(root, 5.0, 0.6);
|
||||
}
|
||||
|
||||
// Zero tolerance: convergence check becomes abs(dx) <= 0, which is only
|
||||
// satisfied when dx is exactly 0. Likely hits max_iter and fails.
|
||||
TEST_F(FindRootTest, ZeroTolerance) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 3.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 5.0, 0.0, 100, fail);
|
||||
// May or may not converge -- for a linear function Newton converges in 1 step
|
||||
// so dx can be exactly 0. Accept either outcome.
|
||||
if (!fail) {
|
||||
EXPECT_NEAR(root, 3.0, 1e-10);
|
||||
}
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Iteration limit edge cases
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Only 1 iteration allowed
|
||||
TEST_F(FindRootTest, OneIteration) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 4.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 3.0, 1e-10, 1, fail);
|
||||
// With only 1 iteration, a quadratic likely won't converge to tight tol
|
||||
// The algorithm may or may not fail depending on initial bisection step
|
||||
(void)root; // just ensure no crash
|
||||
}
|
||||
|
||||
// Two iterations
|
||||
TEST_F(FindRootTest, TwoIterations) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 7.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 5.0, 9.0, 1e-10, 2, fail);
|
||||
// Linear function: Newton should converge very fast
|
||||
// After the initial midpoint (7.0), Newton step should nail it
|
||||
if (!fail) {
|
||||
EXPECT_NEAR(root, 7.0, 1e-6);
|
||||
}
|
||||
}
|
||||
|
||||
// Zero max iterations: the for-loop body never executes, so fail is set to true
|
||||
TEST_F(FindRootTest, ZeroMaxIterations) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 1.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
findRoot(func, 0.0, 2.0, 1e-10, 0, fail);
|
||||
EXPECT_TRUE(fail);
|
||||
}
|
||||
|
||||
// Large max_iter (should still converge quickly and not hang)
|
||||
TEST_F(FindRootTest, LargeMaxIter) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 16.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 10.0, 1e-12, 10000, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 4.0, 1e-10);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Special function types
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Cubic: f(x) = x^3 - 8 (root at x=2)
|
||||
TEST_F(FindRootTest, CubicRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x * x - 8.0;
|
||||
dy = 3.0 * x * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 3.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0, 1e-8);
|
||||
}
|
||||
|
||||
// Quartic: f(x) = x^4 - 16 (root at x=2)
|
||||
TEST_F(FindRootTest, QuarticRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x * x * x - 16.0;
|
||||
dy = 4.0 * x * x * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 3.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0, 1e-8);
|
||||
}
|
||||
|
||||
// Exponential: f(x) = e^x - 10 (root at x=ln(10))
|
||||
TEST_F(FindRootTest, ExponentialRoot2) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = exp(x) - 10.0;
|
||||
dy = exp(x);
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 4.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, log(10.0), 1e-8);
|
||||
}
|
||||
|
||||
// Square root function: f(x) = sqrt(x) - 3, root at x=9
|
||||
// Derivative: 1/(2*sqrt(x))
|
||||
TEST_F(FindRootTest, SqrtFunctionRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = sqrt(x) - 3.0;
|
||||
dy = 0.5 / sqrt(x);
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 20.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 9.0, 1e-6);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Near-zero roots
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = x - 1e-10 (root very close to zero)
|
||||
// Note: convergence check is abs(dx) <= x_tol * abs(root).
|
||||
// When root is near zero, the relative tolerance is very tight.
|
||||
// This may require many iterations or not converge.
|
||||
TEST_F(FindRootTest, NearZeroRootLinear) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 1e-10;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -1.0, 1.0, 1e-6, 200, fail);
|
||||
// Newton on a linear function converges in 1-2 steps regardless of root location
|
||||
if (!fail) {
|
||||
EXPECT_NEAR(root, 1e-10, 1e-6);
|
||||
}
|
||||
}
|
||||
|
||||
// f(x) = x (root exactly at zero)
|
||||
// Convergence test: abs(dx) <= x_tol * abs(root) = x_tol * 0 = 0
|
||||
// Will likely hit max_iter because relative tolerance at root=0 requires dx=0 exactly
|
||||
TEST_F(FindRootTest, RootExactlyAtZero) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -1.0, 1.0, 1e-10, 200, fail);
|
||||
// Even if fail is true, root should be very close to 0
|
||||
EXPECT_NEAR(root, 0.0, 1e-6);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Negative domain
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Root in deeply negative domain: f(x) = x + 100, root at x=-100
|
||||
TEST_F(FindRootTest, NegativeDomainRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x + 100.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -200.0, 0.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, -100.0, 1e-6);
|
||||
}
|
||||
|
||||
// Both bracket endpoints negative: f(x) = x^2 - 1, root at x=-1
|
||||
TEST_F(FindRootTest, NegativeBracketRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 1.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -2.0, -0.5, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, -1.0, 1e-8);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Trigonometric functions
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// sin(x) root at x=0 (bracket [-1, 1])
|
||||
TEST_F(FindRootTest, SinRootAtZero) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = sin(x);
|
||||
dy = cos(x);
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -1.0, 1.0, 1e-10, 100, fail);
|
||||
// Root at 0 has the relative-tolerance issue, but Newton converges fast for sin
|
||||
EXPECT_NEAR(root, 0.0, 1e-4);
|
||||
}
|
||||
|
||||
// sin(x) root at x=2*pi (bracket [5.5, 7.0])
|
||||
TEST_F(FindRootTest, SinRootAt2Pi) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = sin(x);
|
||||
dy = cos(x);
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 5.5, 7.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0 * M_PI, 1e-6);
|
||||
}
|
||||
|
||||
// cos(x) root at x=pi/2
|
||||
TEST_F(FindRootTest, CosRootAtPiOver2) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = cos(x);
|
||||
dy = -sin(x);
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 2.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, M_PI / 2.0, 1e-6);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Multiple roots nearby
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = (x-1)(x-2) = x^2 - 3x + 2, roots at x=1 and x=2
|
||||
// Bracket [0.5, 1.5] should find x=1
|
||||
TEST_F(FindRootTest, MultipleRootsFindFirst) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = (x - 1.0) * (x - 2.0);
|
||||
dy = 2.0 * x - 3.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 0.5, 1.5, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 1.0, 1e-8);
|
||||
}
|
||||
|
||||
// Same function, bracket [1.5, 2.5] should find x=2
|
||||
TEST_F(FindRootTest, MultipleRootsFindSecond) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = (x - 1.0) * (x - 2.0);
|
||||
dy = 2.0 * x - 3.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.5, 2.5, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0, 1e-8);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Discontinuous derivative (sharp corner)
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = |x| - 1 with piecewise derivative.
|
||||
// Root at x=1 (bracket [0.5, 2.0] avoids the corner at 0)
|
||||
TEST_F(FindRootTest, AbsValueRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = fabs(x) - 1.0;
|
||||
dy = (x >= 0.0) ? 1.0 : -1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 0.5, 2.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 1.0, 1e-8);
|
||||
}
|
||||
|
||||
// f(x) = |x| - 1, root at x=-1
|
||||
TEST_F(FindRootTest, AbsValueNegativeRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = fabs(x) - 1.0;
|
||||
dy = (x >= 0.0) ? 1.0 : -1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -2.0, -0.5, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, -1.0, 1e-8);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Very flat function (slow convergence)
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = (x - 3)^5 has a repeated root at x=3 where the derivative is also
|
||||
// zero. Newton-Raphson divides by dy which becomes 0, producing NaN.
|
||||
// The algorithm is expected to fail on this degenerate case.
|
||||
TEST_F(FindRootTest, FlatFifthOrderRootFails) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
double d = x - 3.0;
|
||||
double d2 = d * d;
|
||||
double d4 = d2 * d2;
|
||||
y = d4 * d; // (x-3)^5
|
||||
dy = 5.0 * d4; // 5*(x-3)^4
|
||||
};
|
||||
bool fail = false;
|
||||
findRoot(func, 2.0, 4.0, 1e-6, 500, fail);
|
||||
// The algorithm is expected to fail because dy -> 0 at the root
|
||||
EXPECT_TRUE(fail);
|
||||
}
|
||||
|
||||
// A function that is very flat near the root but still has nonzero derivative
|
||||
// at the root: f(x) = sinh(x - 3) which is ~0 near x=3 but never has dy=0.
|
||||
// sinh is flat near 0 (sinh(e) ~ e for small e) but derivative cosh(e) >= 1.
|
||||
TEST_F(FindRootTest, FlatSinhRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = sinh(x - 3.0);
|
||||
dy = cosh(x - 3.0);
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 2.0, 4.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 3.0, 1e-6);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Very steep function (fast convergence)
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = 1000*(x - 5), root at x=5. Very steep gradient.
|
||||
TEST_F(FindRootTest, SteepLinearRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = 1000.0 * (x - 5.0);
|
||||
dy = 1000.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 3.0, 7.0, 1e-12, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 5.0, 1e-10);
|
||||
}
|
||||
|
||||
// f(x) = 1e6 * (x - 2), very steep
|
||||
TEST_F(FindRootTest, VerySteepLinearRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = 1e6 * (x - 2.0);
|
||||
dy = 1e6;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 3.0, 1e-14, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0, 1e-12);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Large bracket
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = x - 42, bracket [-1000, 1000]
|
||||
TEST_F(FindRootTest, LargeBracket) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 42.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -1000.0, 1000.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 42.0, 1e-6);
|
||||
}
|
||||
|
||||
// Quadratic with large bracket: f(x) = x^2 - 100, root at 10
|
||||
TEST_F(FindRootTest, LargeBracketQuadratic) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 100.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.0, 1000.0, 1e-10, 200, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 10.0, 1e-6);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Small bracket
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = x - 1.0, bracket [0.999999, 1.000001] (very tight bracket around root)
|
||||
TEST_F(FindRootTest, SmallBracket) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 1.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 0.999999, 1.000001, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 1.0, 1e-6);
|
||||
}
|
||||
|
||||
// Quadratic with very small bracket around root=2
|
||||
TEST_F(FindRootTest, SmallBracketQuadratic) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 4.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 1.9999, 2.0001, 1e-12, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0, 1e-8);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Both overloads tested together
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Compare 2-arg and 4-arg overloads produce same result
|
||||
TEST_F(FindRootTest, OverloadsProduceSameResult) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x * x - 27.0;
|
||||
dy = 3.0 * x * x;
|
||||
};
|
||||
|
||||
bool fail_2arg = false;
|
||||
double root_2arg = findRoot(func, 2.0, 4.0, 1e-12, 100, fail_2arg);
|
||||
|
||||
// Pre-compute y values for 4-arg version
|
||||
double y1 = 2.0 * 2.0 * 2.0 - 27.0; // 8 - 27 = -19
|
||||
double y2 = 4.0 * 4.0 * 4.0 - 27.0; // 64 - 27 = 37
|
||||
bool fail_4arg = false;
|
||||
double root_4arg = findRoot(func, 2.0, y1, 4.0, y2, 1e-12, 100, fail_4arg);
|
||||
|
||||
EXPECT_FALSE(fail_2arg);
|
||||
EXPECT_FALSE(fail_4arg);
|
||||
EXPECT_NEAR(root_2arg, 3.0, 1e-10);
|
||||
EXPECT_NEAR(root_4arg, 3.0, 1e-10);
|
||||
EXPECT_NEAR(root_2arg, root_4arg, 1e-14);
|
||||
}
|
||||
|
||||
// 4-arg overload: x1 endpoint is exact root (y1 == 0)
|
||||
TEST_F(FindRootTest, FourArgX1IsRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 5.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
// y1 = 5 - 5 = 0
|
||||
double root = findRoot(func, 5.0, 0.0, 8.0, 3.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_DOUBLE_EQ(root, 5.0);
|
||||
}
|
||||
|
||||
// 4-arg overload: x2 endpoint is exact root (y2 == 0)
|
||||
TEST_F(FindRootTest, FourArgX2IsRoot) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 5.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
// y2 = 5 - 5 = 0
|
||||
double root = findRoot(func, 2.0, -3.0, 5.0, 0.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_DOUBLE_EQ(root, 5.0);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Same-sign y values (should fail)
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// Both endpoints positive: should fail
|
||||
TEST_F(FindRootTest, BothEndpointsPositiveFails) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x + 1.0; // Always positive, no real root
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
findRoot(func, 1.0, 3.0, 1e-10, 100, fail);
|
||||
EXPECT_TRUE(fail);
|
||||
}
|
||||
|
||||
// Both endpoints negative: should fail
|
||||
TEST_F(FindRootTest, BothEndpointsNegativeFails) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = -x * x - 1.0; // Always negative
|
||||
dy = -2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
findRoot(func, -3.0, 3.0, 1e-10, 100, fail);
|
||||
EXPECT_TRUE(fail);
|
||||
}
|
||||
|
||||
// 4-arg version: same-sign y values
|
||||
TEST_F(FindRootTest, FourArgSameSignFails) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
// Both y values positive
|
||||
findRoot(func, 1.0, 1.0, 2.0, 4.0, 1e-10, 100, fail);
|
||||
EXPECT_TRUE(fail);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Symmetry test
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// f(x) = x^2 - 4: bracket [0, 3] finds +2, bracket [-3, 0] finds -2
|
||||
TEST_F(FindRootTest, SymmetryPositiveBracket) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 4.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, 0.5, 3.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 2.0, 1e-8);
|
||||
}
|
||||
|
||||
TEST_F(FindRootTest, SymmetryNegativeBracket) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x * x - 4.0;
|
||||
dy = 2.0 * x;
|
||||
};
|
||||
bool fail = false;
|
||||
double root = findRoot(func, -3.0, -0.5, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, -2.0, 1e-8);
|
||||
}
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Swapped bracket order (x1 > x2)
|
||||
////////////////////////////////////////////////////////////////
|
||||
|
||||
// The algorithm should work regardless of bracket order
|
||||
TEST_F(FindRootTest, SwappedBracketOrder) {
|
||||
FindRootFunc func = [](double x, double &y, double &dy) {
|
||||
y = x - 3.0;
|
||||
dy = 1.0;
|
||||
};
|
||||
bool fail = false;
|
||||
// x1=5 > x2=1 (reversed order)
|
||||
double root = findRoot(func, 5.0, 1.0, 1e-10, 100, fail);
|
||||
EXPECT_FALSE(fail);
|
||||
EXPECT_NEAR(root, 3.0, 1e-8);
|
||||
}
|
||||
|
||||
} // namespace sta
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,15 +21,12 @@ set_output_delay -clock clk 0 [get_ports out1]
|
|||
puts "--- set_load variations ---"
|
||||
set_load 0.001 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with 1fF load"
|
||||
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with 100fF load"
|
||||
|
||||
set_load 1.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with 1pF load"
|
||||
|
||||
# Reset load
|
||||
set_load 0 [get_ports out1]
|
||||
|
|
@ -40,11 +37,9 @@ set_load 0 [get_ports out1]
|
|||
puts "--- set_input_transition ---"
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with 10ps input transition"
|
||||
|
||||
set_input_transition 0.5 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: report_checks with 500ps input transition"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
|
|
@ -92,13 +87,10 @@ puts "--- unit delay calculator ---"
|
|||
set_delay_calculator unit
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unit report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: unit min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unit max path"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "unit dcalc buf1: $msg"
|
||||
|
|
@ -113,7 +105,6 @@ catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D]} msg
|
|||
puts "unit dcalc reg1 setup: $msg"
|
||||
|
||||
report_checks -fields {slew cap}
|
||||
puts "PASS: unit with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# lumped_cap delay calculator
|
||||
|
|
@ -122,7 +113,6 @@ puts "--- lumped_cap delay calculator ---"
|
|||
set_delay_calculator lumped_cap
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: lumped_cap report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "lumped_cap dcalc buf1: $msg"
|
||||
|
|
@ -134,7 +124,6 @@ catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
|||
puts "lumped_cap dcalc reg1: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: lumped_cap with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# dmp_ceff_elmore (default) delay calculator
|
||||
|
|
@ -143,7 +132,6 @@ puts "--- dmp_ceff_elmore delay calculator ---"
|
|||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts "dmp_ceff_elmore dcalc buf1: $msg"
|
||||
|
|
@ -155,13 +143,10 @@ puts "--- dmp_ceff_two_pole delay calculator ---"
|
|||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_two_pole report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: dmp_ceff_two_pole min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: dmp_ceff_two_pole max path"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc buf1 max: $msg"
|
||||
|
|
@ -179,6 +164,3 @@ catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
|||
puts "dmp_ceff_two_pole dcalc reg1 setup: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: dmp_ceff_two_pole with fields"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -28,13 +28,10 @@ set_input_transition 0.1 [get_ports {in1 clk}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc for all arcs: exercises gateDelay, loadDelay paths
|
||||
|
|
@ -42,35 +39,33 @@ puts "PASS: baseline max"
|
|||
puts "--- report_dcalc all arcs ---"
|
||||
|
||||
# BUF arc: rise and fall
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
|
||||
puts "buf1 A->Z max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min
|
||||
puts "buf1 A->Z min: done"
|
||||
|
||||
# INV arc: rise and fall
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max} msg
|
||||
report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -max
|
||||
puts "inv1 A->ZN max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min} msg
|
||||
report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -min
|
||||
puts "inv1 A->ZN min: done"
|
||||
|
||||
# DFF CK->Q arc
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "reg1 CK->Q max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min} msg
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -min
|
||||
puts "reg1 CK->Q min: done"
|
||||
|
||||
# DFF setup and hold check arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -max
|
||||
puts "reg1 setup max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min
|
||||
puts "reg1 hold min: done"
|
||||
|
||||
puts "PASS: report_dcalc all arcs"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Exercise different delay calculators and check delay values
|
||||
# Targets: all delay calculator engines, copy/reinit paths
|
||||
|
|
@ -80,39 +75,34 @@ puts "--- delay calculator engines ---"
|
|||
# Unit delay calculator
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "unit buf1: done"
|
||||
|
||||
# Lumped capacitance calculator
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "lumped_cap buf1: done"
|
||||
|
||||
# DMP Ceff Elmore
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "dmp_elmore buf1: done"
|
||||
|
||||
# DMP Ceff Two Pole
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole calculator"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "dmp_two_pole buf1: done"
|
||||
|
||||
# CCS Ceff
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff calculator"
|
||||
|
||||
# Switch back to default
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
|
@ -129,7 +119,6 @@ foreach load_val {0.00001 0.0001 0.001 0.005 0.01 0.05 0.1 0.5 1.0 5.0} {
|
|||
puts "load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: load variation"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Vary input transition to exercise table lookup paths
|
||||
|
|
@ -143,7 +132,6 @@ foreach slew_val {0.001 0.005 0.01 0.05 0.1 0.2 0.5 1.0 2.0} {
|
|||
puts "slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
puts "PASS: slew variation"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental delay recalculation
|
||||
|
|
@ -154,24 +142,20 @@ puts "--- incremental delay calc ---"
|
|||
# Change clock period
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental after clock change"
|
||||
|
||||
# Change input delay
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input delay change"
|
||||
|
||||
# Change output delay
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after output delay change"
|
||||
|
||||
# Reset and recheck
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after reset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report checks with various formatting to exercise reporting paths
|
||||
|
|
@ -179,22 +163,16 @@ puts "PASS: incremental after reset"
|
|||
puts "--- report formatting ---"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: full_clock_expanded"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: unconstrained"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: sort_by_slack"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types exercises check edge delay queries
|
||||
|
|
@ -202,10 +180,8 @@ puts "PASS: sort_by_slack"
|
|||
puts "--- report_check_types ---"
|
||||
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_slews for all pins: exercises slew getters
|
||||
|
|
@ -221,6 +197,3 @@ report_slews [get_pins inv1/ZN]
|
|||
report_slews [get_pins reg1/D]
|
||||
report_slews [get_pins reg1/CK]
|
||||
report_slews [get_pins reg1/Q]
|
||||
puts "PASS: report_slews"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,553 +0,0 @@
|
|||
--- setIncrementalDelayTolerance ---
|
||||
PASS: incremental delay tolerance 0.01
|
||||
PASS: incremental delay tolerance 0.0
|
||||
PASS: incremental delay tolerance 0.1
|
||||
--- report_net for various nets ---
|
||||
Net n1
|
||||
Pin capacitance: 1.55-1.70
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.55-1.70
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
inv1/A input (INV_X1) 1.55-1.70
|
||||
|
||||
Net n2
|
||||
Pin capacitance: 1.59-1.78
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.59-1.78
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
inv1/ZN output (INV_X1)
|
||||
|
||||
Load pins
|
||||
buf2/A input (BUF_X2) 1.59-1.78
|
||||
|
||||
Net n3
|
||||
Pin capacitance: 0.79-0.95
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.79-0.95
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf2/Z output (BUF_X2)
|
||||
|
||||
Load pins
|
||||
or1/A1 input (OR2_X1) 0.79-0.95
|
||||
|
||||
Net n4
|
||||
Pin capacitance: 0.87-0.92
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.87-0.92
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf3/Z output (BUF_X4)
|
||||
|
||||
Load pins
|
||||
and1/A1 input (AND2_X1) 0.87-0.92
|
||||
|
||||
Net n5
|
||||
Pin capacitance: 0.90-0.94
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 0.90-0.94
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
and1/ZN output (AND2_X1)
|
||||
|
||||
Load pins
|
||||
or1/A2 input (OR2_X1) 0.90-0.94
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 3.82-4.29
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.82-4.29
|
||||
Number of drivers: 1
|
||||
Number of loads: 3
|
||||
Number of pins: 4
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
buf_out/A input (BUF_X1) 0.88-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net all nets
|
||||
--- report_net with loads ---
|
||||
Net n6
|
||||
Pin capacitance: 3.82-4.29
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.82-4.29
|
||||
Number of drivers: 1
|
||||
Number of loads: 3
|
||||
Number of pins: 4
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
buf_out/A input (BUF_X1) 0.88-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
Net n7
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nand1/ZN output (NAND2_X1)
|
||||
|
||||
Load pins
|
||||
reg1/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
Net n8
|
||||
Pin capacitance: 1.06-1.14
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 1.06-1.14
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
nor1/ZN output (NOR2_X1)
|
||||
|
||||
Load pins
|
||||
reg2/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net with loads
|
||||
--- report_net with digits ---
|
||||
Net n1
|
||||
Pin capacitance: 1.549360-1.700230
|
||||
Wire capacitance: 0.000000
|
||||
Total capacitance: 1.549360-1.700230
|
||||
Number of drivers: 1
|
||||
Number of loads: 1
|
||||
Number of pins: 2
|
||||
|
||||
Driver pins
|
||||
buf1/Z output (BUF_X1)
|
||||
|
||||
Load pins
|
||||
inv1/A input (INV_X1) 1.549360-1.700230
|
||||
|
||||
Net n6
|
||||
Pin capacitance: 3.82-4.29
|
||||
Wire capacitance: 0.00
|
||||
Total capacitance: 3.82-4.29
|
||||
Number of drivers: 1
|
||||
Number of loads: 3
|
||||
Number of pins: 4
|
||||
|
||||
Driver pins
|
||||
or1/ZN output (OR2_X1)
|
||||
|
||||
Load pins
|
||||
buf_out/A input (BUF_X1) 0.88-0.97
|
||||
nand1/A1 input (NAND2_X1) 1.53-1.60
|
||||
nor1/A1 input (NOR2_X1) 1.41-1.71
|
||||
|
||||
PASS: report_net digits
|
||||
--- incremental with wire caps ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: wire cap n1
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: wire cap n6
|
||||
--- rapid constraint changes ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: rapid constraint changes
|
||||
--- input transition incremental ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: input transition incremental
|
||||
--- clock period incremental ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
5.00 5.00 clock clk (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 4.96 library setup time
|
||||
4.96 data required time
|
||||
---------------------------------------------------------
|
||||
4.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
20.00 20.00 clock clk (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
19.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
2.00 2.00 clock clk (rise edge)
|
||||
0.00 2.00 clock network delay (ideal)
|
||||
0.00 2.00 clock reconvergence pessimism
|
||||
2.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 1.96 library setup time
|
||||
1.96 data required time
|
||||
---------------------------------------------------------
|
||||
1.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.81 slack (MET)
|
||||
|
||||
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: clock period incremental
|
||||
--- delay calc after constraint changes ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: constraint change incremental
|
||||
--- driving cell changes ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: driving cell changes
|
||||
--- write and read SDF ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
|
||||
Not
|
||||
Delay type Total Annotated Annotated
|
||||
----------------------------------------------------------------
|
||||
cell arcs 17 17 0
|
||||
internal net arcs 10 10 0
|
||||
net arcs from primary inputs 7 7 0
|
||||
net arcs to primary outputs 3 3 0
|
||||
----------------------------------------------------------------
|
||||
37 37 0
|
||||
|
||||
Annotated Arcs
|
||||
primary input net clk -> reg1/CK
|
||||
primary input net clk -> reg2/CK
|
||||
primary input net in1 -> buf1/A
|
||||
primary input net in2 -> buf3/A
|
||||
primary input net in3 -> and1/A2
|
||||
primary input net in4 -> nor1/A2
|
||||
primary input net sel -> nand1/A2
|
||||
delay and1/A1 -> and1/ZN
|
||||
delay and1/A2 -> and1/ZN
|
||||
internal net and1/ZN -> or1/A2
|
||||
delay buf1/A -> buf1/Z
|
||||
internal net buf1/Z -> inv1/A
|
||||
delay buf2/A -> buf2/Z
|
||||
internal net buf2/Z -> or1/A1
|
||||
delay buf3/A -> buf3/Z
|
||||
internal net buf3/Z -> and1/A1
|
||||
delay buf_out/A -> buf_out/Z
|
||||
primary output net buf_out/Z -> out3
|
||||
delay inv1/A -> inv1/ZN
|
||||
internal net inv1/ZN -> buf2/A
|
||||
delay nand1/A1 -> nand1/ZN
|
||||
delay nand1/A2 -> nand1/ZN
|
||||
internal net nand1/ZN -> reg1/D
|
||||
delay nor1/A1 -> nor1/ZN
|
||||
delay nor1/A2 -> nor1/ZN
|
||||
internal net nor1/ZN -> reg2/D
|
||||
delay or1/A1 -> or1/ZN
|
||||
delay or1/A2 -> or1/ZN
|
||||
internal net or1/ZN -> nand1/A1
|
||||
internal net or1/ZN -> nor1/A1
|
||||
internal net or1/ZN -> buf_out/A
|
||||
delay reg1/CK -> reg1/QN
|
||||
delay reg1/CK -> reg1/Q
|
||||
primary output net reg1/Q -> out1
|
||||
delay reg2/CK -> reg2/QN
|
||||
delay reg2/CK -> reg2/Q
|
||||
primary output net reg2/Q -> out2
|
||||
Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
|
||||
Not
|
||||
Check type Total Annotated Annotated
|
||||
----------------------------------------------------------------
|
||||
cell setup arcs 2 2 0
|
||||
cell hold arcs 2 2 0
|
||||
----------------------------------------------------------------
|
||||
4 4 0
|
||||
|
||||
Annotated Arcs
|
||||
setup reg1/CK -> reg1/D
|
||||
hold reg1/CK -> reg1/D
|
||||
setup reg2/CK -> reg2/D
|
||||
hold reg2/CK -> reg2/D
|
||||
PASS: write/read SDF
|
||||
--- remove annotations ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: remove annotations
|
||||
--- calculator switch incremental ---
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
No paths found.
|
||||
PASS: calculator switch incremental
|
||||
ALL PASSED
|
||||
|
|
@ -26,26 +26,17 @@ report_checks -path_delay max > /dev/null
|
|||
# Incremental delay tolerance
|
||||
############################################################
|
||||
puts "--- setIncrementalDelayTolerance ---"
|
||||
catch {
|
||||
sta::set_incremental_delay_tolerance 0.01
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: incremental delay tolerance 0.01"
|
||||
sta::set_incremental_delay_tolerance 0.01
|
||||
report_checks -path_delay max
|
||||
|
||||
catch {
|
||||
sta::set_incremental_delay_tolerance 0.0
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: incremental delay tolerance 0.0"
|
||||
sta::set_incremental_delay_tolerance 0.0
|
||||
report_checks -path_delay max
|
||||
|
||||
catch {
|
||||
sta::set_incremental_delay_tolerance 0.1
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: incremental delay tolerance 0.1"
|
||||
sta::set_incremental_delay_tolerance 0.1
|
||||
report_checks -path_delay max
|
||||
|
||||
# Reset
|
||||
catch { sta::set_incremental_delay_tolerance 0.0 }
|
||||
sta::set_incremental_delay_tolerance 0.0
|
||||
|
||||
############################################################
|
||||
# report_net for capacitance queries
|
||||
|
|
@ -59,7 +50,6 @@ report_net n5
|
|||
report_net n6
|
||||
report_net n7
|
||||
report_net n8
|
||||
puts "PASS: report_net all nets"
|
||||
|
||||
############################################################
|
||||
# report_net with loads
|
||||
|
|
@ -71,7 +61,6 @@ set_load 0.02 [get_ports out3]
|
|||
report_net n6
|
||||
report_net n7
|
||||
report_net n8
|
||||
puts "PASS: report_net with loads"
|
||||
|
||||
############################################################
|
||||
# report_net with digits
|
||||
|
|
@ -79,23 +68,16 @@ puts "PASS: report_net with loads"
|
|||
puts "--- report_net with digits ---"
|
||||
report_net -digits 6 n1
|
||||
report_net -digits 2 n6
|
||||
puts "PASS: report_net digits"
|
||||
|
||||
############################################################
|
||||
# Incremental: add wire caps and recompute
|
||||
############################################################
|
||||
puts "--- incremental with wire caps ---"
|
||||
catch {
|
||||
set_load 0.005 [get_nets n1]
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: wire cap n1"
|
||||
set_load 0.005 [get_nets n1]
|
||||
report_checks -path_delay max
|
||||
|
||||
catch {
|
||||
set_load 0.01 [get_nets n6]
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: wire cap n6"
|
||||
set_load 0.01 [get_nets n6]
|
||||
report_checks -path_delay max
|
||||
|
||||
############################################################
|
||||
# Rapid constraint changes for incremental recalculation
|
||||
|
|
@ -120,7 +102,6 @@ set_load 1.0 [get_ports out1]
|
|||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: rapid constraint changes"
|
||||
|
||||
############################################################
|
||||
# Input transition changes driving incremental
|
||||
|
|
@ -128,10 +109,9 @@ puts "PASS: rapid constraint changes"
|
|||
puts "--- input transition incremental ---"
|
||||
foreach slew {0.001 0.005 0.01 0.05 0.1 0.5 1.0 2.0} {
|
||||
set_input_transition $slew [get_ports in1]
|
||||
catch { report_checks -from [get_ports in1] -to [get_ports out1] }
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
}
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
puts "PASS: input transition incremental"
|
||||
|
||||
############################################################
|
||||
# Clock period changes
|
||||
|
|
@ -145,7 +125,6 @@ create_clock -name clk -period 2 [get_ports clk]
|
|||
report_checks -path_delay max
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
report_checks -path_delay max
|
||||
puts "PASS: clock period incremental"
|
||||
|
||||
############################################################
|
||||
# Delay calc after adding/removing constraints
|
||||
|
|
@ -158,7 +137,6 @@ report_checks -from [get_ports in1] -to [get_ports out1]
|
|||
set_input_delay -clock clk 0 [get_ports in1]
|
||||
set_output_delay -clock clk 0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: constraint change incremental"
|
||||
|
||||
############################################################
|
||||
# Driving cell changes
|
||||
|
|
@ -170,32 +148,25 @@ set_driving_cell -lib_cell BUF_X4 [get_ports in1]
|
|||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: driving cell changes"
|
||||
|
||||
############################################################
|
||||
# read_sdf and annotated delay
|
||||
############################################################
|
||||
puts "--- write and read SDF ---"
|
||||
set sdf_file [file join [pwd] results dcalc_annotated.sdf]
|
||||
catch {
|
||||
file mkdir results
|
||||
write_sdf -no_timestamp -no_version $sdf_file
|
||||
read_sdf $sdf_file
|
||||
report_checks -path_delay max
|
||||
report_annotated_delay -list_annotated
|
||||
report_annotated_check -list_annotated -setup -hold
|
||||
}
|
||||
puts "PASS: write/read SDF"
|
||||
file mkdir results
|
||||
write_sdf -no_timestamp -no_version $sdf_file
|
||||
read_sdf $sdf_file
|
||||
report_checks -path_delay max
|
||||
report_annotated_delay -list_annotated
|
||||
report_annotated_check -list_annotated -setup -hold
|
||||
|
||||
############################################################
|
||||
# Remove annotations and recalculate
|
||||
############################################################
|
||||
puts "--- remove annotations ---"
|
||||
catch {
|
||||
sta::remove_delay_slew_annotations
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: remove annotations"
|
||||
sta::remove_delay_slew_annotations
|
||||
report_checks -path_delay max
|
||||
|
||||
############################################################
|
||||
# Multiple calculator with incremental
|
||||
|
|
@ -216,6 +187,3 @@ report_checks -from [get_ports in1] -to [get_ports out1]
|
|||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: calculator switch incremental"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -27,7 +27,6 @@ set_propagated_clock {clk1 clk2 clk3}
|
|||
# Read SPEF parasitics
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Prima delay calculator with various input transition values
|
||||
|
|
@ -111,23 +110,17 @@ puts "prima u1 8 digits: $msg"
|
|||
|
||||
# Prima with fields
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: prima with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: prima full_clock"
|
||||
|
||||
# Prima specific paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: prima in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: prima in2->out"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: prima min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: prima max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Arnoldi delay calculator with same variations
|
||||
|
|
@ -193,10 +186,8 @@ puts "arnoldi r3 hold: $msg"
|
|||
|
||||
# Arnoldi with fields
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: arnoldi full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switching between parasitic calculators to exercise reinit paths
|
||||
|
|
@ -204,27 +195,21 @@ puts "PASS: arnoldi full_clock"
|
|||
puts "--- switching parasitic calculators ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with parasitics"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics"
|
||||
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff with parasitics"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with parasitics"
|
||||
|
||||
catch {set_delay_calculator prima} msg
|
||||
set_delay_calculator prima
|
||||
report_checks
|
||||
puts "PASS: prima after switching"
|
||||
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: arnoldi after switching"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental updates with parasitics
|
||||
|
|
@ -235,19 +220,14 @@ set_delay_calculator dmp_ceff_elmore
|
|||
|
||||
set_load 0.001 [get_ports out]
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_load"
|
||||
|
||||
set_input_transition 50 {in1 in2}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_input_transition"
|
||||
|
||||
create_clock -name clk -period 200 {clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after clock change"
|
||||
|
||||
# Restore
|
||||
set_load 0 [get_ports out]
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
create_clock -name clk -period 500 {clk1 clk2 clk3}
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -31,25 +31,18 @@ set_propagated_clock {clk1 clk2 clk3}
|
|||
puts "--- Test 1: arnoldi + SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
set_delay_calculator arnoldi
|
||||
puts "PASS: set arnoldi"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min path"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: in2->out"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: report_dcalc for all cell arcs
|
||||
|
|
@ -57,48 +50,46 @@ puts "PASS: full_clock"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: report_dcalc ---"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
|
||||
puts "dcalc u1 A->Y max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -min
|
||||
puts "dcalc u1 A->Y min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
|
||||
puts "dcalc u2 A->Y: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max
|
||||
puts "dcalc u2 B->Y: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -min} msg
|
||||
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -min
|
||||
puts "dcalc u2 B->Y min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
|
||||
puts "dcalc r1 CLK->Q max: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min
|
||||
puts "dcalc r1 CLK->Q min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
|
||||
report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max
|
||||
puts "dcalc r2 CLK->Q: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max
|
||||
puts "dcalc r3 CLK->Q: done"
|
||||
|
||||
# Setup/hold check arcs
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max
|
||||
puts "dcalc r1 setup: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min
|
||||
puts "dcalc r1 hold: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max
|
||||
puts "dcalc r3 setup: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min
|
||||
puts "dcalc r3 hold: done"
|
||||
|
||||
puts "PASS: dcalc reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Vary input slew with arnoldi
|
||||
# Exercises: arnoldi gate delay computation at different slew points
|
||||
|
|
@ -111,7 +102,6 @@ foreach slew_val {0.1 1 5 10 25 50 100 200 500} {
|
|||
puts "arnoldi slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
puts "PASS: varying slew"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Vary output load with arnoldi
|
||||
|
|
@ -125,7 +115,6 @@ foreach load_val {0.00001 0.0001 0.001 0.005 0.01 0.05 0.1} {
|
|||
puts "arnoldi load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
puts "PASS: varying load"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Arnoldi after re-read SPEF
|
||||
|
|
@ -134,7 +123,6 @@ puts "PASS: varying load"
|
|||
puts "--- Test 5: re-read SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
report_checks
|
||||
puts "PASS: arnoldi after re-read"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Switch engines while arnoldi active
|
||||
|
|
@ -144,31 +132,22 @@ puts "--- Test 6: engine switch from arnoldi ---"
|
|||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: switch to dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: back to arnoldi"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: switch to lumped_cap"
|
||||
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: back to arnoldi again"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Arnoldi with digits and endpoint count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: format options ---"
|
||||
report_checks -digits 6
|
||||
puts "PASS: 6 digits"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count 3"
|
||||
|
||||
report_checks -group_count 2
|
||||
puts "PASS: group_count 2"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -25,13 +25,10 @@ catch {set_delay_calculator ccs_ceff} msg
|
|||
puts "set_delay_calculator ccs_ceff: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: ccs_ceff min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: ccs_ceff max path"
|
||||
|
||||
# report_dcalc with ccs_ceff
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
|
|
@ -61,10 +58,8 @@ puts "ccs_ceff dcalc reg1 hold: $msg"
|
|||
|
||||
# With fields
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: ccs_ceff with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: ccs_ceff full_clock format"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental delay update: change constraints and recompute
|
||||
|
|
@ -74,38 +69,30 @@ puts "--- incremental delay update ---"
|
|||
# Change load and recompute (exercises GraphDelayCalc incremental update)
|
||||
set_load 0.01 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after set_load 0.01"
|
||||
|
||||
set_load 0.05 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after set_load 0.05"
|
||||
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after set_load 0.1"
|
||||
|
||||
# Change input transition and recompute
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input_transition 0.01"
|
||||
|
||||
set_input_transition 0.5 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input_transition 0.5"
|
||||
|
||||
# Change clock period (triggers incremental update)
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental after clock period change"
|
||||
|
||||
# Change delays
|
||||
set_input_delay -clock clk 1.0 [get_ports in1]
|
||||
report_checks
|
||||
puts "PASS: incremental after input_delay change"
|
||||
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental after output_delay change"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch between calculators to exercise copy/init paths
|
||||
|
|
@ -114,27 +101,21 @@ puts "--- calculator switching ---"
|
|||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: switch to dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: switch back to ccs_ceff"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: switch to dmp_ceff_two_pole"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: switch to lumped_cap"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: switch to unit"
|
||||
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: switch back to ccs_ceff final"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc with -digits (exercises formatting paths)
|
||||
|
|
@ -151,5 +132,3 @@ puts "dcalc 8 digits: $msg"
|
|||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 12} msg
|
||||
puts "dcalc 12 digits: $msg"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -27,7 +27,6 @@ set_propagated_clock {clk1 clk2 clk3}
|
|||
# Read SPEF parasitics
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# CCS delay calculator with parasitics
|
||||
|
|
@ -37,16 +36,12 @@ catch {set_delay_calculator ccs_ceff} msg
|
|||
puts "set_delay_calculator ccs_ceff: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff with parasitics report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: ccs_ceff with parasitics min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: ccs_ceff with parasitics max"
|
||||
|
||||
report_checks -fields {slew cap input_pins} -format full_clock
|
||||
puts "PASS: ccs_ceff with parasitics fields"
|
||||
|
||||
# report_dcalc exercises arc delay computation through parasitics
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
|
|
@ -73,10 +68,8 @@ puts "ccs_ceff dcalc r3 hold: $msg"
|
|||
|
||||
# Additional paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: ccs_ceff in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: ccs_ceff in2->out"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# DMP ceff two-pole with parasitics (incremental from ccs_ceff)
|
||||
|
|
@ -85,13 +78,10 @@ puts "--- dmp_ceff_two_pole with parasitics ---"
|
|||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: dmp_ceff_two_pole min with parasitics"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: dmp_ceff_two_pole max with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "dmp_two_pole dcalc u1: $msg"
|
||||
|
|
@ -103,7 +93,6 @@ catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
|||
puts "dmp_two_pole dcalc r1 CLK->Q: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets}
|
||||
puts "PASS: dmp_two_pole with full fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Incremental changes with parasitics
|
||||
|
|
@ -113,17 +102,14 @@ puts "--- incremental with parasitics ---"
|
|||
# Change load
|
||||
set_load 0.001 [get_ports out]
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_load"
|
||||
|
||||
# Change input transition
|
||||
set_input_transition 50 {in1 in2}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after set_input_transition"
|
||||
|
||||
# Change clock period
|
||||
create_clock -name clk -period 200 {clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: incremental parasitics after clock change"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch to ccs_ceff after constraint changes (exercises reinit)
|
||||
|
|
@ -131,7 +117,6 @@ puts "PASS: incremental parasitics after clock change"
|
|||
puts "--- ccs_ceff after constraint changes ---"
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff after constraint changes"
|
||||
|
||||
# Switch rapidly between calculators
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
|
@ -139,19 +124,13 @@ set_delay_calculator ccs_ceff
|
|||
set_delay_calculator arnoldi
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: rapid calculator switching"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report checks with different endpoint counts
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with endpoint_count ---"
|
||||
report_checks -endpoint_count 2
|
||||
puts "PASS: endpoint_count 2"
|
||||
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: min endpoint_count 3"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,694 +0,0 @@
|
|||
--- Fast corner timing ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast corner
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.01 0.01 ^ buf1/Z (BUF_X1)
|
||||
0.00 0.02 v inv1/ZN (INV_X1)
|
||||
0.00 0.02 v reg1/D (DFF_X1)
|
||||
0.02 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.02 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.01 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast corner min path
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast corner max path
|
||||
--- Slow corner timing ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow corner
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.05 0.05 ^ buf1/Z (BUF_X1)
|
||||
0.02 0.07 v inv1/ZN (INV_X1)
|
||||
0.00 0.07 v reg1/D (DFF_X1)
|
||||
0.07 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.07 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.07 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow corner min path
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow corner max path
|
||||
--- report_dcalc per corner ---
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.72
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.72
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.00 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.60
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.60
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.00 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner buf1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.64
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.04 0.05
|
||||
0.01 | 0.04 0.06
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.64
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.03
|
||||
0.01 | 0.01 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.48
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.07 0.08
|
||||
0.01 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.48
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.02
|
||||
0.01 | 0.01 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner buf1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.10
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.01 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.00
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.10
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.01 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.16
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.01 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.16
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.01 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner inv1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.03
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.01 0.02
|
||||
0.04 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.03
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.00 0.01
|
||||
0.04 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.11
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.02 0.04
|
||||
0.04 | 0.04 0.06
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.02
|
||||
| total_output_net_capacitance = 1.11
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.01 | 0.01 0.02
|
||||
0.04 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner inv1
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.05 0.05
|
||||
0.00 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.05 0.05
|
||||
0.00 | 0.05 0.05
|
||||
Table value = 0.05
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.05
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.00 | 0.00 0.00
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner DFF CK->Q
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.29 0.30
|
||||
0.01 | 0.30 0.31
|
||||
Table value = 0.29
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.29
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.03
|
||||
0.01 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.02
|
||||
Driver waveform slew = 0.02
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.23 0.24
|
||||
0.01 | 0.24 0.25
|
||||
Table value = 0.23
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.23
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.01 | 0.02 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner DFF CK->Q
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc type: hold
|
||||
CK ^ -> D ^
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- constrained_pin_transition = 0.00 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.03
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.03 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> D v
|
||||
P = 1.00 V = 1.25 T = 0.00
|
||||
------- constrained_pin_transition = 0.00 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.03
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.03 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc fast corner DFF hold check
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: DFF_X1
|
||||
Arc type: setup
|
||||
CK ^ -> D ^
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- constrained_pin_transition = 0.02 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.11
|
||||
v --------------------
|
||||
0.00 | 0.06 0.04
|
||||
0.11 | 0.11 0.08
|
||||
Table value = 0.07
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.07
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> D v
|
||||
P = 1.00 V = 0.95 T = 125.00
|
||||
------- constrained_pin_transition = 0.01 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.11
|
||||
v --------------------
|
||||
0.00 | 0.15 0.09
|
||||
0.11 | 0.21 0.15
|
||||
Table value = 0.15
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.15
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc slow corner DFF setup check
|
||||
--- report_checks with fields ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast with fields
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.02 0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.02 0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
0.00 10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
-----------------------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow with fields
|
||||
--- set_load and recheck corners ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: fast
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.05 0.05 v reg1/Q (DFF_X1)
|
||||
0.00 0.05 v out1 (out)
|
||||
0.05 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.05 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks fast after set_load
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
Corner: slow
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.29 0.29 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.29 ^ out1 (out)
|
||||
0.29 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.29 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks slow after set_load
|
||||
ALL PASSED
|
||||
|
|
@ -18,23 +18,17 @@ set_output_delay -clock clk 0 [get_ports out1]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Fast corner timing ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: report_checks fast corner"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: report_checks fast corner min path"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: report_checks fast corner max path"
|
||||
|
||||
puts "--- Slow corner timing ---"
|
||||
report_checks -corner slow
|
||||
puts "PASS: report_checks slow corner"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: report_checks slow corner min path"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: report_checks slow corner max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc per corner
|
||||
|
|
@ -43,47 +37,37 @@ puts "--- report_dcalc per corner ---"
|
|||
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner buf1"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner buf1"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner inv1"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner inv1"
|
||||
|
||||
# DFF arcs per corner
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner DFF CK->Q"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner DFF CK->Q"
|
||||
|
||||
# Setup/hold check arcs per corner
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc fast corner DFF hold check"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc slow corner DFF setup check"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with -fields for more coverage
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with fields ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins}
|
||||
puts "PASS: report_checks fast with fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins}
|
||||
puts "PASS: report_checks slow with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_load on output and recheck corners
|
||||
|
|
@ -91,9 +75,5 @@ puts "PASS: report_checks slow with fields"
|
|||
puts "--- set_load and recheck corners ---"
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks -corner fast
|
||||
puts "PASS: report_checks fast after set_load"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: report_checks slow after set_load"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -31,7 +31,6 @@ set_delay_calculator dmp_ceff_elmore
|
|||
set_load 0.0001 [get_ports out1]
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore tiny load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "tiny load dcalc: $msg"
|
||||
|
|
@ -40,7 +39,6 @@ puts "tiny load dcalc: $msg"
|
|||
set_load 0.001 [get_ports out1]
|
||||
set_input_transition 0.05 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore small load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "small load dcalc: $msg"
|
||||
|
|
@ -49,7 +47,6 @@ puts "small load dcalc: $msg"
|
|||
set_load 0.01 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore medium load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "medium load dcalc: $msg"
|
||||
|
|
@ -58,7 +55,6 @@ puts "medium load dcalc: $msg"
|
|||
set_load 0.1 [get_ports out1]
|
||||
set_input_transition 0.5 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore large load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "large load dcalc: $msg"
|
||||
|
|
@ -67,7 +63,6 @@ puts "large load dcalc: $msg"
|
|||
set_load 1.0 [get_ports out1]
|
||||
set_input_transition 1.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_elmore very large load"
|
||||
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "very large load dcalc: $msg"
|
||||
|
|
@ -87,7 +82,7 @@ set_delay_calculator dmp_ceff_two_pole
|
|||
foreach out_port {out1 out2 out3} {
|
||||
foreach load_val {0.001 0.01 0.05 0.1} {
|
||||
set_load $load_val [get_ports $out_port]
|
||||
catch {report_checks -to [get_ports $out_port]} msg
|
||||
report_checks -to [get_ports $out_port]
|
||||
puts "dmp_two_pole $out_port load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports $out_port]
|
||||
|
|
@ -130,9 +125,7 @@ set_delay_calculator dmp_ceff_elmore
|
|||
|
||||
foreach slew_val {0.001 0.01 0.05 0.1 0.2 0.5 1.0} {
|
||||
set_input_transition $slew_val [get_ports {in1 in2 in3 in4 sel}]
|
||||
catch {
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
} msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel}]
|
||||
|
|
@ -146,7 +139,6 @@ catch {set_delay_calculator ccs_ceff} msg
|
|||
puts "set_delay_calculator ccs_ceff: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff on larger design"
|
||||
|
||||
# Various loads with ccs_ceff
|
||||
foreach load_val {0.001 0.01 0.1} {
|
||||
|
|
@ -181,23 +173,17 @@ set_delay_calculator dmp_ceff_elmore
|
|||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
puts "PASS: rapid switching"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various reporting formats
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks formatting ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: full_clock_expanded"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,980 +0,0 @@
|
|||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
--- Test 1: manual pi + dmp_ceff_elmore ---
|
||||
PASS: pi/elmore set
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_elmore with pi
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
0.00 1.00 v r1/D (DFFHQx4_ASAP7_75t_R)
|
||||
1.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
8.56 8.56 library hold time
|
||||
8.56 data required time
|
||||
---------------------------------------------------------
|
||||
8.56 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
-7.56 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: min with pi
|
||||
--- Test 2: dmp_ceff_two_pole ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with pi
|
||||
No paths found.
|
||||
PASS: in1->out two_pole
|
||||
No paths found.
|
||||
PASS: in2->out two_pole
|
||||
--- Test 3: extreme slew ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
45.32 45.32 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.76 57.08 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 71.96 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 71.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
71.96 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-7.11 492.89 library setup time
|
||||
492.89 data required time
|
||||
---------------------------------------------------------
|
||||
492.89 data required time
|
||||
-71.96 data arrival time
|
||||
---------------------------------------------------------
|
||||
420.94 slack (MET)
|
||||
|
||||
|
||||
PASS: very small slew 0.01
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
45.34 45.34 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.76 57.11 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 71.98 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 71.98 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
71.98 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-7.09 492.91 library setup time
|
||||
492.91 data required time
|
||||
---------------------------------------------------------
|
||||
492.91 data required time
|
||||
-71.98 data arrival time
|
||||
---------------------------------------------------------
|
||||
420.92 slack (MET)
|
||||
|
||||
|
||||
PASS: small slew 0.1
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.39 56.39 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 68.16 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 83.03 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 83.03 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
83.03 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.73 496.27 library setup time
|
||||
496.27 data required time
|
||||
---------------------------------------------------------
|
||||
496.27 data required time
|
||||
-83.03 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.24 slack (MET)
|
||||
|
||||
|
||||
PASS: medium slew 50
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
84.45 84.45 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 96.22 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 111.09 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 111.09 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
111.09 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
2.57 502.57 library setup time
|
||||
502.57 data required time
|
||||
---------------------------------------------------------
|
||||
502.57 data required time
|
||||
-111.09 data arrival time
|
||||
---------------------------------------------------------
|
||||
391.48 slack (MET)
|
||||
|
||||
|
||||
PASS: large slew 500
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
161.62 161.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.78 173.40 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 188.28 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 188.28 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
188.28 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
18.08 518.08 library setup time
|
||||
518.08 data required time
|
||||
---------------------------------------------------------
|
||||
518.08 data required time
|
||||
-188.28 data arrival time
|
||||
---------------------------------------------------------
|
||||
329.80 slack (MET)
|
||||
|
||||
|
||||
PASS: very large slew 2000
|
||||
--- Test 4: tiny pi model ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: tiny pi model
|
||||
--- Test 5: large pi model ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: large pi model
|
||||
--- Test 6: report_dcalc ---
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 12.833000 15.145800
|
||||
10.000000 | 14.375000 16.681900
|
||||
Table value = 11.767857
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 11.767857
|
||||
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 7.612690 11.681800
|
||||
10.000000 | 7.631100 11.699600
|
||||
Table value = 5.145066
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 5.145066
|
||||
Driver waveform slew = 5.145066
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 13.395100 15.605499
|
||||
10.000000 | 15.032999 17.245100
|
||||
Table value = 12.146009
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 12.146009
|
||||
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 6.998250 10.429300
|
||||
10.000000 | 7.020140 10.451000
|
||||
Table value = 4.916347
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 4.916347
|
||||
Driver waveform slew = 4.916347
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore u1: done
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.0000 V = 0.7000 T = 25.0000
|
||||
------- input_net_transition = 6.0255
|
||||
| total_output_net_capacitance = 0.6212
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 16.6604 19.5485
|
||||
10.0000 | 17.8038 20.6883
|
||||
Table value = 15.2532
|
||||
PVT scale factor = 1.0000
|
||||
Delay = 15.2532
|
||||
|
||||
------- input_net_transition = 6.0255
|
||||
| total_output_net_capacitance = 0.6212
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 9.6841 14.4815
|
||||
10.0000 | 9.6803 14.4760
|
||||
Table value = 6.9558
|
||||
PVT scale factor = 1.0000
|
||||
Slew = 6.9558
|
||||
Driver waveform slew = 6.9558
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.0000 V = 0.7000 T = 25.0000
|
||||
------- input_net_transition = 5.2046
|
||||
| total_output_net_capacitance = 0.6192
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 16.7215 19.2327
|
||||
10.0000 | 18.4070 20.9322
|
||||
Table value = 15.3587
|
||||
PVT scale factor = 1.0000
|
||||
Delay = 15.3587
|
||||
|
||||
------- input_net_transition = 5.2046
|
||||
| total_output_net_capacitance = 0.6192
|
||||
| 1.4400 2.8800
|
||||
v --------------------
|
||||
5.0000 | 8.1900 11.9873
|
||||
10.0000 | 8.1957 11.9745
|
||||
Table value = 6.0261
|
||||
PVT scale factor = 1.0000
|
||||
Slew = 6.0261
|
||||
Driver waveform slew = 6.0261
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore u2 A: done
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
B ^ -> Y ^
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 5.15
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 16.47 19.36
|
||||
10.00 | 18.11 20.96
|
||||
Table value = 14.88
|
||||
PVT scale factor = 1.00
|
||||
Delay = 14.88
|
||||
|
||||
------- input_net_transition = 5.15
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 9.69 14.48
|
||||
10.00 | 9.69 14.49
|
||||
Table value = 6.96
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.96
|
||||
Driver waveform slew = 6.96
|
||||
|
||||
.............................................
|
||||
|
||||
B v -> Y v
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 4.92
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 15.82 18.32
|
||||
10.00 | 17.62 20.13
|
||||
Table value = 14.36
|
||||
PVT scale factor = 1.00
|
||||
Delay = 14.36
|
||||
|
||||
------- input_net_transition = 4.92
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 8.02 11.83
|
||||
10.00 | 8.02 11.83
|
||||
Table value = 5.84
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.84
|
||||
Driver waveform slew = 5.84
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore u2 B: done
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.52
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 49.30 50.80
|
||||
20.00 | 52.04 53.53
|
||||
Table value = 48.34
|
||||
PVT scale factor = 1.00
|
||||
Delay = 48.34
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.52
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 7.26 9.21
|
||||
20.00 | 7.26 9.21
|
||||
Table value = 6.03
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.03
|
||||
Driver waveform slew = 6.03
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.51
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 47.74 49.14
|
||||
20.00 | 50.34 51.75
|
||||
Table value = 46.84
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.84
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.51
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 6.31 8.01
|
||||
20.00 | 6.30 8.01
|
||||
Table value = 5.20
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.20
|
||||
Driver waveform slew = 5.20
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore r1: done
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
Pi model C2=0.00 Rpi=2.00 C1=0.00, Ceff=0.00
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 49.30 50.80
|
||||
20.00 | 52.04 53.53
|
||||
Table value = 47.80
|
||||
PVT scale factor = 1.00
|
||||
Delay = 47.80
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 7.26 9.21
|
||||
20.00 | 7.26 9.21
|
||||
Table value = 5.32
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.32
|
||||
Driver waveform slew = 5.32
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
Pi model C2=0.00 Rpi=2.00 C1=0.00, Ceff=0.00
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 47.74 49.14
|
||||
20.00 | 50.34 51.75
|
||||
Table value = 46.35
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.35
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 6.31 8.01
|
||||
20.00 | 6.30 8.01
|
||||
Table value = 4.60
|
||||
PVT scale factor = 1.00
|
||||
Slew = 4.60
|
||||
Driver waveform slew = 4.60
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_elmore r3 min: done
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 12.833000 15.145800
|
||||
10.000000 | 14.375000 16.681900
|
||||
Table value = 11.767857
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 11.767857
|
||||
|
||||
------- input_net_transition = 6.099100
|
||||
| total_output_net_capacitance = 0.565282
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 7.612690 11.681800
|
||||
10.000000 | 7.631100 11.699600
|
||||
Table value = 5.145066
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 5.145066
|
||||
Driver waveform slew = 5.145066
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.000000 V = 0.770000 T = 0.000000
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 13.395100 15.605499
|
||||
10.000000 | 15.032999 17.245100
|
||||
Table value = 12.146009
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 12.146009
|
||||
|
||||
------- input_net_transition = 5.283920
|
||||
| total_output_net_capacitance = 0.565708
|
||||
| 1.440000 2.880000
|
||||
v --------------------
|
||||
5.000000 | 6.998250 10.429300
|
||||
10.000000 | 7.020140 10.451000
|
||||
Table value = 4.916347
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 4.916347
|
||||
Driver waveform slew = 4.916347
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_two_pole u1: done
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 6.03
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 16.66 19.55
|
||||
10.00 | 17.80 20.69
|
||||
Table value = 15.25
|
||||
PVT scale factor = 1.00
|
||||
Delay = 15.25
|
||||
|
||||
------- input_net_transition = 6.03
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 9.68 14.48
|
||||
10.00 | 9.68 14.48
|
||||
Table value = 6.96
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.96
|
||||
Driver waveform slew = 6.96
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 5.20
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 16.72 19.23
|
||||
10.00 | 18.41 20.93
|
||||
Table value = 15.36
|
||||
PVT scale factor = 1.00
|
||||
Delay = 15.36
|
||||
|
||||
------- input_net_transition = 5.20
|
||||
| total_output_net_capacitance = 0.62
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
5.00 | 8.19 11.99
|
||||
10.00 | 8.20 11.97
|
||||
Table value = 6.03
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.03
|
||||
Driver waveform slew = 6.03
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_two_pole u2: done
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 49.30 50.80
|
||||
20.00 | 52.04 53.53
|
||||
Table value = 48.40
|
||||
PVT scale factor = 1.00
|
||||
Delay = 48.40
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 7.26 9.21
|
||||
20.00 | 7.26 9.21
|
||||
Table value = 6.10
|
||||
PVT scale factor = 1.00
|
||||
Slew = 6.10
|
||||
Driver waveform slew = 6.10
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 47.74 49.14
|
||||
20.00 | 50.34 51.75
|
||||
Table value = 46.90
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.90
|
||||
|
||||
------- input_net_transition = 10.00
|
||||
| total_output_net_capacitance = 0.58
|
||||
| 1.44 2.88
|
||||
v --------------------
|
||||
10.00 | 6.31 8.01
|
||||
20.00 | 6.30 8.01
|
||||
Table value = 5.28
|
||||
PVT scale factor = 1.00
|
||||
Slew = 5.28
|
||||
Driver waveform slew = 5.28
|
||||
|
||||
.............................................
|
||||
|
||||
dmp_two_pole r2: done
|
||||
PASS: dcalc reports
|
||||
--- Test 7: SPEF override manual ---
|
||||
PASS: SPEF override
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_elmore with SPEF
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
48.40 48.40 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 60.17 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 75.04 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 75.04 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
75.04 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-5.78 494.22 library setup time
|
||||
494.22 data required time
|
||||
---------------------------------------------------------
|
||||
494.22 data required time
|
||||
-75.04 data arrival time
|
||||
---------------------------------------------------------
|
||||
419.17 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with SPEF
|
||||
--- Test 8: load variation ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.0001: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.001: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.01: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.05: done
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
56.18 68.29 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
11.77 80.05 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
14.88 94.93 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 94.93 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
94.93 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-3.87 508.05 library setup time
|
||||
508.05 data required time
|
||||
---------------------------------------------------------
|
||||
508.05 data required time
|
||||
-94.93 data arrival time
|
||||
---------------------------------------------------------
|
||||
413.12 slack (MET)
|
||||
|
||||
|
||||
dmp load=0.1: done
|
||||
PASS: load variation
|
||||
--- Test 9: find_delays ---
|
||||
PASS: find_delays
|
||||
PASS: invalidate + find_delays
|
||||
ALL PASSED
|
||||
|
|
@ -34,23 +34,20 @@ puts "--- Test 1: manual pi + dmp_ceff_elmore ---"
|
|||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
# Set pi models on all driver pins
|
||||
catch {sta::set_pi_model u1/Y 0.005 10.0 0.003} msg
|
||||
catch {sta::set_elmore u1/Y u2/B 0.005} msg
|
||||
catch {sta::set_pi_model u2/Y 0.008 15.0 0.005} msg
|
||||
catch {sta::set_elmore u2/Y r3/D 0.008} msg
|
||||
catch {sta::set_pi_model r1/Q 0.002 5.0 0.001} msg
|
||||
catch {sta::set_elmore r1/Q u2/A 0.003} msg
|
||||
catch {sta::set_pi_model r2/Q 0.003 6.0 0.002} msg
|
||||
catch {sta::set_elmore r2/Q u1/A 0.004} msg
|
||||
catch {sta::set_pi_model r3/Q 0.001 2.0 0.001} msg
|
||||
catch {sta::set_elmore r3/Q out 0.002} msg
|
||||
puts "PASS: pi/elmore set"
|
||||
sta::set_pi_model u1/Y 0.005 10.0 0.003
|
||||
sta::set_elmore u1/Y u2/B 0.005
|
||||
sta::set_pi_model u2/Y 0.008 15.0 0.005
|
||||
sta::set_elmore u2/Y r3/D 0.008
|
||||
sta::set_pi_model r1/Q 0.002 5.0 0.001
|
||||
sta::set_elmore r1/Q u2/A 0.003
|
||||
sta::set_pi_model r2/Q 0.003 6.0 0.002
|
||||
sta::set_elmore r2/Q u1/A 0.004
|
||||
sta::set_pi_model r3/Q 0.001 2.0 0.001
|
||||
sta::set_elmore r3/Q out 0.002
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with pi"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min with pi"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: dmp_ceff_two_pole with manual pi
|
||||
|
|
@ -59,13 +56,10 @@ puts "PASS: min with pi"
|
|||
puts "--- Test 2: dmp_ceff_two_pole ---"
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with pi"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: in1->out two_pole"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: in2->out two_pole"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Extreme slew values with DMP
|
||||
|
|
@ -78,27 +72,22 @@ set_delay_calculator dmp_ceff_elmore
|
|||
# Very small slew
|
||||
set_input_transition 0.01 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: very small slew 0.01"
|
||||
|
||||
# Small slew
|
||||
set_input_transition 0.1 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: small slew 0.1"
|
||||
|
||||
# Medium slew
|
||||
set_input_transition 50 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: medium slew 50"
|
||||
|
||||
# Large slew
|
||||
set_input_transition 500 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: large slew 500"
|
||||
|
||||
# Very large slew
|
||||
set_input_transition 2000 {in1 in2 clk1 clk2 clk3}
|
||||
report_checks
|
||||
puts "PASS: very large slew 2000"
|
||||
|
||||
set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
||||
|
||||
|
|
@ -108,10 +97,9 @@ set_input_transition 10 {in1 in2 clk1 clk2 clk3}
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: tiny pi model ---"
|
||||
|
||||
catch {sta::set_pi_model u1/Y 0.00001 0.1 0.00001} msg
|
||||
catch {sta::set_elmore u1/Y u2/B 0.00001} msg
|
||||
sta::set_pi_model u1/Y 0.00001 0.1 0.00001
|
||||
sta::set_elmore u1/Y u2/B 0.00001
|
||||
report_checks
|
||||
puts "PASS: tiny pi model"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Large pi model values
|
||||
|
|
@ -119,12 +107,11 @@ puts "PASS: tiny pi model"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: large pi model ---"
|
||||
|
||||
catch {sta::set_pi_model u1/Y 0.1 100.0 0.05} msg
|
||||
catch {sta::set_elmore u1/Y u2/B 0.5} msg
|
||||
catch {sta::set_pi_model u2/Y 0.15 150.0 0.08} msg
|
||||
catch {sta::set_elmore u2/Y r3/D 0.8} msg
|
||||
sta::set_pi_model u1/Y 0.1 100.0 0.05
|
||||
sta::set_elmore u1/Y u2/B 0.5
|
||||
sta::set_pi_model u2/Y 0.15 150.0 0.08
|
||||
sta::set_elmore u2/Y r3/D 0.8
|
||||
report_checks
|
||||
puts "PASS: large pi model"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: report_dcalc with dmp calculators
|
||||
|
|
@ -133,33 +120,31 @@ puts "PASS: large pi model"
|
|||
puts "--- Test 6: report_dcalc ---"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6
|
||||
puts "dmp_elmore u1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max -digits 4} msg
|
||||
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max -digits 4
|
||||
puts "dmp_elmore u2 A: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max
|
||||
puts "dmp_elmore u2 B: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
|
||||
puts "dmp_elmore r1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -min} msg
|
||||
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -min
|
||||
puts "dmp_elmore r3 min: done"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max -digits 6
|
||||
puts "dmp_two_pole u1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
|
||||
puts "dmp_two_pole u2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max} msg
|
||||
report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -max
|
||||
puts "dmp_two_pole r2: done"
|
||||
|
||||
puts "PASS: dcalc reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: SPEF overriding manual, then DMP
|
||||
# Exercises: deleteReducedParasitics from manual->SPEF transition
|
||||
|
|
@ -167,14 +152,11 @@ puts "PASS: dcalc reports"
|
|||
puts "--- Test 7: SPEF override manual ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: SPEF override"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with SPEF"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with SPEF"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 8: Load variation with DMP
|
||||
|
|
@ -189,17 +171,12 @@ foreach load_val {0.0001 0.001 0.01 0.05 0.1} {
|
|||
puts "dmp load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out]
|
||||
puts "PASS: load variation"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 9: find_delays and invalidation
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 9: find_delays ---"
|
||||
sta::find_delays
|
||||
puts "PASS: find_delays"
|
||||
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
puts "PASS: invalidate + find_delays"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -30,14 +30,12 @@ set_input_transition 0.1 [get_ports in1]
|
|||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore zero load: $msg"
|
||||
puts "PASS: elmore zero load"
|
||||
|
||||
# Tiny load
|
||||
set_load 0.00001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore tiny load: $msg"
|
||||
puts "PASS: elmore tiny load"
|
||||
|
||||
# Very large load (potential overflow path)
|
||||
set_load 5.0 [get_ports out1]
|
||||
|
|
@ -45,14 +43,12 @@ set_input_transition 0.1 [get_ports in1]
|
|||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore large load: $msg"
|
||||
puts "PASS: elmore large load"
|
||||
|
||||
# Huge load
|
||||
set_load 10.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore huge load: $msg"
|
||||
puts "PASS: elmore huge load"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
|
|
@ -66,21 +62,18 @@ set_input_transition 0.0001 [get_ports in1]
|
|||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore fast transition: $msg"
|
||||
puts "PASS: elmore fast transition"
|
||||
|
||||
# Very slow transition
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore slow transition: $msg"
|
||||
puts "PASS: elmore slow transition"
|
||||
|
||||
# Extreme slow
|
||||
set_input_transition 10.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "elmore extreme slow: $msg"
|
||||
puts "PASS: elmore extreme slow"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
|
|
@ -92,17 +85,14 @@ puts "--- dmp_ceff_elmore combined extremes ---"
|
|||
set_load 5.0 [get_ports out1]
|
||||
set_input_transition 0.001 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: elmore extreme: large load + fast slew"
|
||||
|
||||
set_load 0.0001 [get_ports out1]
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: elmore extreme: small load + slow slew"
|
||||
|
||||
set_load 5.0 [get_ports out1]
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: elmore extreme: large load + slow slew"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
|
@ -115,19 +105,15 @@ set_delay_calculator dmp_ceff_two_pole
|
|||
|
||||
set_load 0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole zero load"
|
||||
|
||||
set_load 0.00001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole tiny load"
|
||||
|
||||
set_load 5.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole large load"
|
||||
|
||||
set_load 10.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole huge load"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
|
||||
|
|
@ -135,11 +121,9 @@ puts "--- dmp_ceff_two_pole extreme transitions ---"
|
|||
|
||||
set_input_transition 0.0001 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole fast transition"
|
||||
|
||||
set_input_transition 5.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: two_pole slow transition"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
|
|
@ -174,8 +158,6 @@ puts "dcalc reg1 setup: $msg"
|
|||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
puts "dcalc reg1 hold: $msg"
|
||||
|
||||
puts "PASS: report_dcalc all arcs"
|
||||
|
||||
############################################################
|
||||
# report_dcalc with various digit counts
|
||||
############################################################
|
||||
|
|
@ -188,7 +170,6 @@ catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 6} msg
|
|||
puts "6 digits: $msg"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -digits 10} msg
|
||||
puts "10 digits: $msg"
|
||||
puts "PASS: dcalc digits"
|
||||
|
||||
############################################################
|
||||
# Sweep load/slew matrix for convergence coverage
|
||||
|
|
@ -200,13 +181,12 @@ foreach calc {dmp_ceff_elmore dmp_ceff_two_pole} {
|
|||
foreach slew {0.01 0.05 0.1 0.5 1.0} {
|
||||
set_load $load [get_ports out1]
|
||||
set_input_transition $slew [get_ports in1]
|
||||
catch { report_checks -from [get_ports in1] -to [get_ports out1] > /dev/null }
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] > /dev/null
|
||||
}
|
||||
}
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
puts "PASS: load/slew sweep"
|
||||
|
||||
############################################################
|
||||
# Unit delay calculator
|
||||
|
|
@ -216,7 +196,6 @@ set_delay_calculator unit
|
|||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "unit dcalc buf1: $msg"
|
||||
puts "PASS: unit calculator"
|
||||
|
||||
############################################################
|
||||
# Lumped cap calculator
|
||||
|
|
@ -228,9 +207,6 @@ report_checks -from [get_ports in1] -to [get_ports out1]
|
|||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts "lumped_cap dcalc buf1: $msg"
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: lumped_cap calculator"
|
||||
|
||||
# Restore default
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,7 +21,6 @@ create_clock -name clk -period 10 [get_ports clk]
|
|||
set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: design setup"
|
||||
|
||||
############################################################
|
||||
# Test 1: Manual pi model with dmp_ceff_elmore on all outputs
|
||||
|
|
@ -33,30 +32,24 @@ set_delay_calculator dmp_ceff_elmore
|
|||
set all_cells [get_cells *]
|
||||
foreach cell_obj $all_cells {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set ref [get_property $cell_obj ref_name]
|
||||
# Try to set pi model on output pins
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.003 8.0 0.002}
|
||||
}
|
||||
set ref [get_property $cell_obj ref_name]
|
||||
# Try to set pi model on output pins
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.003 8.0 0.002}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: set pi models"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with pi"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min with pi"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max with pi"
|
||||
|
||||
############################################################
|
||||
# Test 2: Extreme pi model values (very small)
|
||||
|
|
@ -65,20 +58,17 @@ puts "--- Test 2: tiny pi model ---"
|
|||
|
||||
foreach cell_obj [lrange $all_cells 0 4] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.00001 0.01 0.000005}
|
||||
}
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.00001 0.01 0.000005}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: tiny pi model"
|
||||
|
||||
############################################################
|
||||
# Test 3: Large pi model values
|
||||
|
|
@ -87,20 +77,17 @@ puts "--- Test 3: large pi model ---"
|
|||
|
||||
foreach cell_obj [lrange $all_cells 0 4] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.1 200.0 0.05}
|
||||
}
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.1 200.0 0.05}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: large pi model"
|
||||
|
||||
############################################################
|
||||
# Test 4: dmp_ceff_two_pole with manual pi models
|
||||
|
|
@ -109,10 +96,8 @@ puts "--- Test 4: dmp_ceff_two_pole ---"
|
|||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks
|
||||
puts "PASS: two_pole with pi"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: two_pole min"
|
||||
|
||||
# Vary slew
|
||||
foreach slew_val {0.01 0.1 0.5 1.0 5.0} {
|
||||
|
|
@ -121,7 +106,6 @@ foreach slew_val {0.01 0.1 0.5 1.0 5.0} {
|
|||
puts "two_pole slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: two_pole varying slew"
|
||||
|
||||
############################################################
|
||||
# Test 5: SPEF then manual pi model override
|
||||
|
|
@ -130,28 +114,23 @@ puts "--- Test 5: SPEF then pi override ---"
|
|||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
read_spef ../../search/test/search_test1.spef
|
||||
puts "PASS: read SPEF"
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp with SPEF"
|
||||
|
||||
# Override with manual pi models
|
||||
foreach cell_obj [lrange $all_cells 0 2] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.005 10.0 0.003}
|
||||
}
|
||||
set pins [get_pins $cname/*]
|
||||
foreach pin $pins {
|
||||
catch {
|
||||
set dir [get_property $pin direction]
|
||||
if {$dir == "output"} {
|
||||
catch {sta::set_pi_model [get_name $pin] 0.005 10.0 0.003}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
report_checks
|
||||
puts "PASS: pi override after SPEF"
|
||||
|
||||
############################################################
|
||||
# Test 6: report_dcalc with dmp calculators and pi models
|
||||
|
|
@ -161,31 +140,25 @@ puts "--- Test 6: report_dcalc ---"
|
|||
set_delay_calculator dmp_ceff_elmore
|
||||
foreach cell_obj [lrange $all_cells 0 5] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -max}
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -min}
|
||||
}
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -max}
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -min}
|
||||
}
|
||||
}
|
||||
puts "PASS: dmp_ceff_elmore dcalc"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
foreach cell_obj [lrange $all_cells 0 5] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -max -digits 6}
|
||||
}
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {report_dcalc -from $in_pin -to $out_pin -max -digits 6}
|
||||
}
|
||||
}
|
||||
puts "PASS: dmp_ceff_two_pole dcalc"
|
||||
|
||||
############################################################
|
||||
# Test 7: Incremental updates with pi models
|
||||
|
|
@ -197,46 +170,35 @@ set_delay_calculator dmp_ceff_elmore
|
|||
# Load change triggers incremental
|
||||
set_load 0.001 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental load out1"
|
||||
|
||||
set_load 0.005 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: incremental load out1 (2)"
|
||||
|
||||
# Slew change triggers incremental
|
||||
set_input_transition 0.5 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: incremental slew 0.5"
|
||||
|
||||
set_input_transition 2.0 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: incremental slew 2.0"
|
||||
|
||||
# Clock change triggers incremental
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental clock 5"
|
||||
|
||||
create_clock -name clk -period 2 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental clock 2"
|
||||
|
||||
############################################################
|
||||
# Test 8: find_delays and invalidation
|
||||
############################################################
|
||||
puts "--- Test 8: find_delays ---"
|
||||
sta::find_delays
|
||||
puts "PASS: find_delays"
|
||||
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
puts "PASS: invalidate + find_delays"
|
||||
|
||||
# Multiple invalidation cycles
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
}
|
||||
puts "PASS: multiple invalidation cycles"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,656 +0,0 @@
|
|||
--- Testing unit delay calculator ---
|
||||
|
||||
No paths found.
|
||||
PASS: unit delay calculator report_checks
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
1.00 1.00 ^ reg1/Q (DFF_X1)
|
||||
0.00 1.00 ^ out1 (out)
|
||||
1.00 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 0.00 output external delay
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-1.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
1.00 slack (MET)
|
||||
|
||||
|
||||
PASS: unit min path
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
1.00 1.00 v buf1/Z (BUF_X1)
|
||||
1.00 2.00 ^ inv1/ZN (INV_X1)
|
||||
0.00 2.00 ^ reg1/D (DFF_X1)
|
||||
2.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-1.00 9.00 library setup time
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-2.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
7.00 slack (MET)
|
||||
|
||||
|
||||
PASS: unit max path
|
||||
--- Testing lumped_cap delay calculator ---
|
||||
|
||||
No paths found.
|
||||
PASS: lumped_cap delay calculator report_checks
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.02 0.02 ^ buf1/Z (BUF_X1)
|
||||
0.01 0.02 v inv1/ZN (INV_X1)
|
||||
0.00 0.02 v reg1/D (DFF_X1)
|
||||
0.02 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.02 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.02 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap min path
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap max path
|
||||
--- Testing report_dcalc ---
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc from/to
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -min
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -max
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.000000 V = 1.100000 T = 25.000000
|
||||
------- input_net_transition = 0.007053
|
||||
| total_output_net_capacitance = 1.062342
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.004611 0.006782
|
||||
0.017186 | 0.005658 0.009630
|
||||
Table value = 0.005947
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 0.005947
|
||||
|
||||
------- input_net_transition = 0.007053
|
||||
| total_output_net_capacitance = 1.062342
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.002081 0.003192
|
||||
0.017186 | 0.004539 0.006195
|
||||
Table value = 0.003092
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 0.003092
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.000000 V = 1.100000 T = 25.000000
|
||||
------- input_net_transition = 0.005514
|
||||
| total_output_net_capacitance = 1.140290
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.007266 0.011031
|
||||
0.017186 | 0.011759 0.017202
|
||||
Table value = 0.009509
|
||||
PVT scale factor = 1.000000
|
||||
Delay = 0.009509
|
||||
|
||||
------- input_net_transition = 0.005514
|
||||
| total_output_net_capacitance = 1.140290
|
||||
| 0.365616 1.897810
|
||||
v --------------------
|
||||
0.004724 | 0.003321 0.006755
|
||||
0.017186 | 0.006463 0.009176
|
||||
Table value = 0.005233
|
||||
PVT scale factor = 1.000000
|
||||
Slew = 0.005233
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -digits
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.02
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.02 0.02
|
||||
0.00 | 0.02 0.03
|
||||
Table value = 0.02
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.02
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.00 | 0.00 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -from only
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: INV_X1
|
||||
Arc sense: negative_unate
|
||||
Arc type: combinational
|
||||
A ^ -> ZN v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.06
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.06
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.00
|
||||
0.02 | 0.00 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> ZN ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.14
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.02 | 0.01 0.02
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.01
|
||||
|
||||
------- input_net_transition = 0.01
|
||||
| total_output_net_capacitance = 1.14
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.00 0.01
|
||||
0.02 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc -to only
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc type: setup
|
||||
CK ^ -> D ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- constrained_pin_transition = 0.01 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.04
|
||||
v --------------------
|
||||
0.00 | 0.03 0.02
|
||||
0.04 | 0.04 0.03
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.03
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> D v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- constrained_pin_transition = 0.00 (ideal clock)
|
||||
| related_pin_transition = 0.00
|
||||
| 0.00 0.04
|
||||
v --------------------
|
||||
0.00 | 0.04 0.02
|
||||
0.04 | 0.05 0.04
|
||||
Table value = 0.04
|
||||
PVT scale factor = 1.00
|
||||
Check = 0.04
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF check arcs
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.00
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF CK->Q arc
|
||||
--- Testing set_load ---
|
||||
|
||||
No paths found.
|
||||
PASS: report_checks after set_load
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: DFF_X1
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CK ^ -> Q ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.09
|
||||
0.00 | 0.08 0.09
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
CK ^ -> Q v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.08 0.08
|
||||
0.00 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.00
|
||||
| total_output_net_capacitance = 0.05
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.00 | 0.01 0.01
|
||||
0.00 | 0.01 0.01
|
||||
Table value = 0.00
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.00
|
||||
Driver waveform slew = 0.00
|
||||
|
||||
.............................................
|
||||
|
||||
PASS: report_dcalc after set_load
|
||||
--- Testing set_input_transition ---
|
||||
No paths found.
|
||||
PASS: report_checks after set_input_transition
|
||||
Library: NangateOpenCellLibrary
|
||||
Cell: BUF_X1
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Z ^
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.03 0.04
|
||||
0.20 | 0.03 0.03
|
||||
Table value = 0.03
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.03
|
||||
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.70
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.01 0.01
|
||||
0.20 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Z v
|
||||
P = 1.00 V = 1.10 T = 25.00
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.06 0.07
|
||||
0.20 | 0.08 0.08
|
||||
Table value = 0.08
|
||||
PVT scale factor = 1.00
|
||||
Delay = 0.08
|
||||
|
||||
------- input_net_transition = 0.20
|
||||
| total_output_net_capacitance = 1.55
|
||||
| 0.37 1.90
|
||||
v --------------------
|
||||
0.13 | 0.01 0.01
|
||||
0.20 | 0.01 0.01
|
||||
Table value = 0.01
|
||||
PVT scale factor = 1.00
|
||||
Slew = 0.01
|
||||
Driver waveform slew = 0.01
|
||||
|
||||
.............................................
|
||||
|
||||
PASS: report_dcalc after set_input_transition
|
||||
--- Testing dmp_ceff_two_pole delay calculator ---
|
||||
|
||||
No paths found.
|
||||
PASS: dmp_ceff_two_pole report_checks
|
||||
ALL PASSED
|
||||
|
|
@ -16,13 +16,10 @@ puts "--- Testing unit delay calculator ---"
|
|||
catch {set_delay_calculator unit} msg
|
||||
puts $msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: unit delay calculator report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: unit min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: unit max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Lumped cap delay calculator
|
||||
|
|
@ -31,13 +28,10 @@ puts "--- Testing lumped_cap delay calculator ---"
|
|||
catch {set_delay_calculator lumped_cap} msg
|
||||
puts $msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: lumped_cap delay calculator report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: lumped_cap min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: lumped_cap max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc with various options
|
||||
|
|
@ -47,42 +41,34 @@ puts "--- Testing report_dcalc ---"
|
|||
# report_dcalc from/to
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc from/to"
|
||||
|
||||
# report_dcalc -min
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -min} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -min"
|
||||
|
||||
# report_dcalc -max
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -max"
|
||||
|
||||
# report_dcalc with -digits
|
||||
catch {report_dcalc -from [get_pins inv1/A] -to [get_pins inv1/ZN] -digits 6} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -digits"
|
||||
|
||||
# report_dcalc from only
|
||||
catch {report_dcalc -from [get_pins buf1/A]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -from only"
|
||||
|
||||
# report_dcalc to only
|
||||
catch {report_dcalc -to [get_pins inv1/ZN]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc -to only"
|
||||
|
||||
# report_dcalc for DFF setup/hold arcs
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/D]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF check arcs"
|
||||
|
||||
# report_dcalc for DFF clock->Q arc
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF CK->Q arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_load on output ports and recompute
|
||||
|
|
@ -95,10 +81,8 @@ catch {set_delay_calculator dmp_ceff_elmore} msg
|
|||
puts $msg
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_load"
|
||||
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "PASS: report_dcalc after set_load"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_input_transition on inputs and recompute
|
||||
|
|
@ -107,10 +91,8 @@ puts "--- Testing set_input_transition ---"
|
|||
set_input_transition 0.2 [get_ports in1]
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks after set_input_transition"
|
||||
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
|
||||
puts "PASS: report_dcalc after set_input_transition"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test dmp_ceff_two_pole calculator
|
||||
|
|
@ -119,6 +101,3 @@ puts "--- Testing dmp_ceff_two_pole delay calculator ---"
|
|||
catch {set_delay_calculator dmp_ceff_two_pole} msg
|
||||
puts $msg
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: dmp_ceff_two_pole report_checks"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -19,28 +19,22 @@ source ../../test/helpers.tcl
|
|||
# Read Sky130 library and GCD design
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read sky130hd"
|
||||
|
||||
read_verilog ../../examples/gcd_sky130hd.v
|
||||
link_design gcd
|
||||
puts "PASS: link gcd"
|
||||
|
||||
source ../../examples/gcd_sky130hd.sdc
|
||||
puts "PASS: SDC"
|
||||
|
||||
# Read SPEF parasitics (large: ~19k lines, many parasitic nodes)
|
||||
read_spef ../../examples/gcd_sky130hd.spef
|
||||
puts "PASS: read gcd SPEF"
|
||||
|
||||
############################################################
|
||||
# Baseline with default delay calculator (dmp_ceff_elmore)
|
||||
############################################################
|
||||
puts "--- baseline dmp_ceff_elmore ---"
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: dmp baseline"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: dmp min"
|
||||
|
||||
############################################################
|
||||
# Arnoldi with large GCD design
|
||||
|
|
@ -49,44 +43,37 @@ puts "PASS: dmp min"
|
|||
puts "--- arnoldi with gcd ---"
|
||||
set_delay_calculator arnoldi
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: arnoldi max"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: arnoldi min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: arnoldi full_clock"
|
||||
|
||||
# Arnoldi report_dcalc on various cells in the design
|
||||
puts "--- arnoldi report_dcalc ---"
|
||||
set cell_count 0
|
||||
foreach cell_obj [get_cells *] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
set in_pins {}
|
||||
set out_pins {}
|
||||
foreach p $pins {
|
||||
set dir [get_property $p direction]
|
||||
if {$dir == "input"} {
|
||||
lappend in_pins $p
|
||||
} elseif {$dir == "output"} {
|
||||
lappend out_pins $p
|
||||
}
|
||||
}
|
||||
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
|
||||
catch {
|
||||
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
|
||||
}
|
||||
incr cell_count
|
||||
if {$cell_count >= 30} break
|
||||
set pins [get_pins $cname/*]
|
||||
set in_pins {}
|
||||
set out_pins {}
|
||||
foreach p $pins {
|
||||
set dir [get_property $p direction]
|
||||
if {$dir == "input"} {
|
||||
lappend in_pins $p
|
||||
} elseif {$dir == "output"} {
|
||||
lappend out_pins $p
|
||||
}
|
||||
}
|
||||
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
|
||||
catch {
|
||||
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
|
||||
}
|
||||
incr cell_count
|
||||
if {$cell_count >= 30} break
|
||||
}
|
||||
}
|
||||
puts "PASS: arnoldi report_dcalc on $cell_count cells"
|
||||
|
||||
# Arnoldi with varying input slews
|
||||
puts "--- arnoldi varying slew ---"
|
||||
|
|
@ -96,7 +83,6 @@ foreach slew_val {0.01 0.05 0.1 0.5 1.0} {
|
|||
puts "arnoldi slew=$slew_val done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: arnoldi varying slew"
|
||||
|
||||
# Arnoldi with varying output loads
|
||||
puts "--- arnoldi varying loads ---"
|
||||
|
|
@ -106,7 +92,6 @@ foreach load_val {0.0001 0.001 0.01 0.05} {
|
|||
puts "arnoldi load=$load_val done"
|
||||
}
|
||||
set_load 0 [get_ports resp_msg*]
|
||||
puts "PASS: arnoldi varying loads"
|
||||
|
||||
############################################################
|
||||
# Prima with GCD design and varying reduce orders
|
||||
|
|
@ -116,52 +101,45 @@ catch {set_delay_calculator prima} msg
|
|||
puts "set prima: $msg"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: prima max"
|
||||
|
||||
report_checks -path_delay min -endpoint_count 3
|
||||
puts "PASS: prima min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: prima fields"
|
||||
|
||||
# Prima with varying reduce orders
|
||||
puts "--- prima reduce orders ---"
|
||||
foreach order {1 2 3 4 5} {
|
||||
catch {sta::set_prima_reduce_order $order} msg
|
||||
sta::set_prima_reduce_order $order
|
||||
report_checks -endpoint_count 1
|
||||
puts "prima order=$order done"
|
||||
}
|
||||
# Reset to default
|
||||
catch {sta::set_prima_reduce_order 3}
|
||||
puts "PASS: prima reduce orders"
|
||||
sta::set_prima_reduce_order 3
|
||||
|
||||
# Prima report_dcalc
|
||||
puts "--- prima report_dcalc ---"
|
||||
set cell_count 0
|
||||
foreach cell_obj [get_cells *] {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set pins [get_pins $cname/*]
|
||||
set in_pins {}
|
||||
set out_pins {}
|
||||
foreach p $pins {
|
||||
set dir [get_property $p direction]
|
||||
if {$dir == "input"} {
|
||||
lappend in_pins $p
|
||||
} elseif {$dir == "output"} {
|
||||
lappend out_pins $p
|
||||
}
|
||||
}
|
||||
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
|
||||
catch {
|
||||
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
|
||||
}
|
||||
incr cell_count
|
||||
if {$cell_count >= 30} break
|
||||
set pins [get_pins $cname/*]
|
||||
set in_pins {}
|
||||
set out_pins {}
|
||||
foreach p $pins {
|
||||
set dir [get_property $p direction]
|
||||
if {$dir == "input"} {
|
||||
lappend in_pins $p
|
||||
} elseif {$dir == "output"} {
|
||||
lappend out_pins $p
|
||||
}
|
||||
}
|
||||
if {[llength $in_pins] > 0 && [llength $out_pins] > 0} {
|
||||
catch {
|
||||
report_dcalc -from [lindex $in_pins 0] -to [lindex $out_pins 0] -max
|
||||
}
|
||||
incr cell_count
|
||||
if {$cell_count >= 30} break
|
||||
}
|
||||
}
|
||||
puts "PASS: prima report_dcalc on $cell_count cells"
|
||||
|
||||
# Prima varying slew
|
||||
puts "--- prima varying slew ---"
|
||||
|
|
@ -171,7 +149,6 @@ foreach slew_val {0.01 0.1 0.5 2.0} {
|
|||
puts "prima slew=$slew_val done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: prima varying slew"
|
||||
|
||||
############################################################
|
||||
# Rapid switching between calculators
|
||||
|
|
@ -180,27 +157,21 @@ puts "PASS: prima varying slew"
|
|||
puts "--- rapid switching ---"
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch to dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch to dmp_ceff_two_pole"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch to lumped_cap"
|
||||
|
||||
catch {set_delay_calculator arnoldi}
|
||||
set_delay_calculator arnoldi
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch back to arnoldi"
|
||||
|
||||
catch {set_delay_calculator prima}
|
||||
set_delay_calculator prima
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: switch back to prima"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks -endpoint_count 1
|
||||
puts "PASS: final dmp_ceff_elmore"
|
||||
|
||||
############################################################
|
||||
# delay_calc_names and is_delay_calc_name
|
||||
|
|
@ -215,6 +186,3 @@ foreach name {dmp_ceff_elmore dmp_ceff_two_pole lumped_cap arnoldi prima} {
|
|||
}
|
||||
set result [sta::is_delay_calc_name nonexistent_calc]
|
||||
puts "is_delay_calc_name nonexistent_calc = $result"
|
||||
puts "PASS: delay calc name queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -24,60 +24,44 @@ set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max path"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple from/to path queries (exercises findVertexDelay for many paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple path queries ---"
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: in1->out1"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out2]
|
||||
puts "PASS: in1->out2"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out3]
|
||||
puts "PASS: in1->out3"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out1]
|
||||
puts "PASS: in2->out1"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: in2->out2"
|
||||
|
||||
report_checks -from [get_ports in3] -to [get_ports out1]
|
||||
puts "PASS: in3->out1"
|
||||
|
||||
report_checks -from [get_ports in4] -to [get_ports out2]
|
||||
puts "PASS: in4->out2"
|
||||
|
||||
report_checks -from [get_ports sel] -to [get_ports out1]
|
||||
puts "PASS: sel->out1"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Through pin queries (exercises more graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through pin queries ---"
|
||||
catch {report_checks -through [get_pins or1/ZN]} msg
|
||||
puts "PASS: through or1/ZN"
|
||||
report_checks -through [get_pins or1/ZN]
|
||||
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
puts "PASS: through nand1/ZN"
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
puts "PASS: through nor1/ZN"
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
puts "PASS: through and1/ZN"
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
|
||||
catch {report_checks -through [get_pins inv1/ZN]} msg
|
||||
puts "PASS: through inv1/ZN"
|
||||
report_checks -through [get_pins inv1/ZN]
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc for all arc types in design
|
||||
|
|
@ -163,19 +147,15 @@ puts "--- incremental delay calculation ---"
|
|||
# Change loads
|
||||
set_load 0.001 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after set_load 0.001 on out1"
|
||||
|
||||
set_load 0.01 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after set_load 0.01 on out1"
|
||||
|
||||
set_load 0.1 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after set_load 0.1 on out1"
|
||||
|
||||
set_load 0.05 [get_ports out2]
|
||||
report_checks -from [get_ports in4] -to [get_ports out2]
|
||||
puts "PASS: incremental after set_load 0.05 on out2"
|
||||
|
||||
# Reset loads
|
||||
set_load 0 [get_ports out1]
|
||||
|
|
@ -184,27 +164,22 @@ set_load 0 [get_ports out2]
|
|||
# Change input transitions
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after slew 0.01 on in1"
|
||||
|
||||
set_input_transition 1.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after slew 1.0 on in1"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
|
||||
# Change clock period
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: incremental after clock period change to 5"
|
||||
|
||||
# Change input/output delays
|
||||
set_input_delay -clock clk 1.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after input_delay 1.0"
|
||||
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: incremental after output_delay 2.0"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test various delay calculators on larger design
|
||||
|
|
@ -214,23 +189,18 @@ puts "--- calculator switching ---"
|
|||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit on large design"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap on large design"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore on large design"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole on large design"
|
||||
|
||||
catch {set_delay_calculator ccs_ceff} msg
|
||||
set_delay_calculator ccs_ceff
|
||||
report_checks
|
||||
puts "PASS: ccs_ceff on large design"
|
||||
|
||||
# Switch back to default
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
|
|
@ -240,37 +210,25 @@ set_delay_calculator dmp_ceff_elmore
|
|||
#---------------------------------------------------------------
|
||||
puts "--- report_checks formatting ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: report_checks with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report_checks full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: report_checks full_clock_expanded"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: report_checks endpoint_count 3"
|
||||
|
||||
report_checks -group_count 5
|
||||
puts "PASS: report_checks group_count 5"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: report_checks sort_by_slack"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: report_check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: report_check_types min"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types max+min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,646 +0,0 @@
|
|||
--- Test 1: baseline timing ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline
|
||||
Startpoint: in4 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in4 (in)
|
||||
0.01 0.01 v nor1/ZN (NOR2_X1)
|
||||
0.00 0.01 v reg2/D (DFF_X1)
|
||||
0.01 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg2/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.01 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.01 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
--- Test 2: incremental delay tolerance ---
|
||||
PASS: set tolerance 0.5
|
||||
No paths found.
|
||||
PASS: after slew change with large tolerance
|
||||
No paths found.
|
||||
PASS: after slew revert with large tolerance
|
||||
PASS: set tolerance 0.001
|
||||
No paths found.
|
||||
PASS: after slew change with small tolerance
|
||||
No paths found.
|
||||
PASS: after slew revert with small tolerance
|
||||
PASS: set tolerance 0.0
|
||||
--- Test 3: incremental load changes ---
|
||||
No paths found.
|
||||
load=0.0001: done
|
||||
No paths found.
|
||||
load=0.001: done
|
||||
No paths found.
|
||||
load=0.005: done
|
||||
No paths found.
|
||||
load=0.01: done
|
||||
No paths found.
|
||||
load=0.05: done
|
||||
No paths found.
|
||||
load=0.1: done
|
||||
No paths found.
|
||||
load=0.5: done
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: load on all outputs
|
||||
--- Test 4: incremental slew changes ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.02 0.02 v buf3/Z (BUF_X4)
|
||||
0.02 0.04 v and1/ZN (AND2_X1)
|
||||
0.05 0.10 v or1/ZN (OR2_X1)
|
||||
0.02 0.12 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.12 ^ reg2/D (DFF_X1)
|
||||
0.12 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.03 9.97 library setup time
|
||||
9.97 data required time
|
||||
---------------------------------------------------------
|
||||
9.97 data required time
|
||||
-0.12 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.85 slack (MET)
|
||||
|
||||
|
||||
PASS: very fast slew
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: medium slew
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in1 (in)
|
||||
0.44 0.44 v buf1/Z (BUF_X1)
|
||||
0.03 0.47 ^ inv1/ZN (INV_X1)
|
||||
0.02 0.49 ^ buf2/Z (BUF_X2)
|
||||
0.03 0.52 ^ or1/ZN (OR2_X1)
|
||||
0.01 0.53 v nor1/ZN (NOR2_X1)
|
||||
0.00 0.53 v reg2/D (DFF_X1)
|
||||
0.53 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.12 9.88 library setup time
|
||||
9.88 data required time
|
||||
---------------------------------------------------------
|
||||
9.88 data required time
|
||||
-0.53 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.35 slack (MET)
|
||||
|
||||
|
||||
PASS: very slow slew
|
||||
Startpoint: in4 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in4 (in)
|
||||
0.24 0.24 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.24 ^ reg2/D (DFF_X1)
|
||||
0.24 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.05 9.95 library setup time
|
||||
9.95 data required time
|
||||
---------------------------------------------------------
|
||||
9.95 data required time
|
||||
-0.24 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.71 slack (MET)
|
||||
|
||||
|
||||
PASS: mixed slews
|
||||
--- Test 5: constraint changes ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
5.00 5.00 clock clk (rise edge)
|
||||
0.00 5.00 clock network delay (ideal)
|
||||
0.00 5.00 clock reconvergence pessimism
|
||||
5.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 4.96 library setup time
|
||||
4.96 data required time
|
||||
---------------------------------------------------------
|
||||
4.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.81 slack (MET)
|
||||
|
||||
|
||||
PASS: clock period 5
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
20.00 20.00 clock clk (rise edge)
|
||||
0.00 20.00 clock network delay (ideal)
|
||||
0.00 20.00 clock reconvergence pessimism
|
||||
20.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 19.96 library setup time
|
||||
19.96 data required time
|
||||
---------------------------------------------------------
|
||||
19.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
19.81 slack (MET)
|
||||
|
||||
|
||||
PASS: clock period 20
|
||||
No paths found.
|
||||
PASS: input_delay 2.0
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
-3.00 7.00 output external delay
|
||||
7.00 data required time
|
||||
---------------------------------------------------------
|
||||
7.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
6.92 slack (MET)
|
||||
|
||||
|
||||
PASS: output_delay 3.0
|
||||
--- Test 6: network modification invalidation ---
|
||||
PASS: make_instance
|
||||
PASS: make_net
|
||||
PASS: connect_pin
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: report after add
|
||||
PASS: disconnect_pin
|
||||
PASS: cleanup
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: report after cleanup
|
||||
--- Test 7: replace cell ---
|
||||
No paths found.
|
||||
PASS: replace buf1 -> BUF_X4
|
||||
No paths found.
|
||||
PASS: replace buf1 -> BUF_X2
|
||||
No paths found.
|
||||
PASS: replace buf1 -> BUF_X1 (restore)
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.02 0.08 v and1/ZN (AND2_X2)
|
||||
0.05 0.12 v or1/ZN (OR2_X2)
|
||||
0.02 0.14 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.14 ^ reg2/D (DFF_X1)
|
||||
0.14 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.14 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.82 slack (MET)
|
||||
|
||||
|
||||
PASS: replace multiple cells
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: restore cells
|
||||
--- Test 8: tolerance with calculator switching ---
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap with tolerance
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_elmore with tolerance
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with tolerance
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
1.00 1.00 ^ buf1/Z (BUF_X1)
|
||||
1.00 2.00 v inv1/ZN (INV_X1)
|
||||
1.00 3.00 v buf2/Z (BUF_X2)
|
||||
1.00 4.00 v or1/ZN (OR2_X1)
|
||||
1.00 5.00 ^ nand1/ZN (NAND2_X1)
|
||||
0.00 5.00 ^ reg1/D (DFF_X1)
|
||||
5.00 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg1/CK (DFF_X1)
|
||||
-1.00 9.00 library setup time
|
||||
9.00 data required time
|
||||
---------------------------------------------------------
|
||||
9.00 data required time
|
||||
-5.00 data arrival time
|
||||
---------------------------------------------------------
|
||||
4.00 slack (MET)
|
||||
|
||||
|
||||
PASS: unit with tolerance
|
||||
Startpoint: in2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 v input external delay
|
||||
0.00 0.00 v in2 (in)
|
||||
0.05 0.05 v buf3/Z (BUF_X4)
|
||||
0.03 0.08 v and1/ZN (AND2_X1)
|
||||
0.05 0.13 v or1/ZN (OR2_X1)
|
||||
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
||||
0.00 0.15 ^ reg2/D (DFF_X1)
|
||||
0.15 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
10.00 ^ reg2/CK (DFF_X1)
|
||||
-0.04 9.96 library setup time
|
||||
9.96 data required time
|
||||
---------------------------------------------------------
|
||||
9.96 data required time
|
||||
-0.15 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.81 slack (MET)
|
||||
|
||||
|
||||
PASS: final report
|
||||
ALL PASSED
|
||||
|
|
@ -25,10 +25,8 @@ set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Set incremental delay tolerance
|
||||
|
|
@ -38,33 +36,26 @@ puts "--- Test 2: incremental delay tolerance ---"
|
|||
|
||||
# Set large tolerance (will suppress many incremental updates)
|
||||
sta::set_delay_calc_incremental_tolerance 0.5
|
||||
puts "PASS: set tolerance 0.5"
|
||||
|
||||
# Change input transition - large tolerance means less recalc
|
||||
set_input_transition 0.2 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew change with large tolerance"
|
||||
|
||||
# Change back
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew revert with large tolerance"
|
||||
|
||||
# Set small tolerance (will recompute more aggressively)
|
||||
sta::set_delay_calc_incremental_tolerance 0.001
|
||||
puts "PASS: set tolerance 0.001"
|
||||
|
||||
set_input_transition 0.2 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew change with small tolerance"
|
||||
|
||||
set_input_transition 0.1 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: after slew revert with small tolerance"
|
||||
|
||||
# Zero tolerance
|
||||
sta::set_delay_calc_incremental_tolerance 0.0
|
||||
puts "PASS: set tolerance 0.0"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Incremental updates with load changes
|
||||
|
|
@ -85,7 +76,6 @@ set_load 0.01 [get_ports out1]
|
|||
set_load 0.01 [get_ports out2]
|
||||
set_load 0.01 [get_ports out3]
|
||||
report_checks
|
||||
puts "PASS: load on all outputs"
|
||||
|
||||
set_load 0 [get_ports out1]
|
||||
set_load 0 [get_ports out2]
|
||||
|
|
@ -100,17 +90,14 @@ puts "--- Test 4: incremental slew changes ---"
|
|||
# Very fast transitions
|
||||
set_input_transition 0.001 [get_ports {in1 in2 in3 in4 sel}]
|
||||
report_checks
|
||||
puts "PASS: very fast slew"
|
||||
|
||||
# Medium transitions
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel}]
|
||||
report_checks
|
||||
puts "PASS: medium slew"
|
||||
|
||||
# Very slow transitions
|
||||
set_input_transition 2.0 [get_ports {in1 in2 in3 in4 sel}]
|
||||
report_checks
|
||||
puts "PASS: very slow slew"
|
||||
|
||||
# Different slews on different inputs
|
||||
set_input_transition 0.01 [get_ports in1]
|
||||
|
|
@ -119,7 +106,6 @@ set_input_transition 0.001 [get_ports in3]
|
|||
set_input_transition 1.0 [get_ports in4]
|
||||
set_input_transition 0.1 [get_ports sel]
|
||||
report_checks
|
||||
puts "PASS: mixed slews"
|
||||
|
||||
# Restore
|
||||
set_input_transition 0.1 [get_ports {in1 in2 in3 in4 sel clk}]
|
||||
|
|
@ -133,25 +119,21 @@ puts "--- Test 5: constraint changes ---"
|
|||
# Change clock period
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: clock period 5"
|
||||
|
||||
create_clock -name clk -period 20 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: clock period 20"
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
|
||||
# Change input delays
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: input_delay 2.0"
|
||||
|
||||
set_input_delay -clock clk 0.0 [get_ports in1]
|
||||
|
||||
# Change output delays
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
report_checks -to [get_ports out1]
|
||||
puts "PASS: output_delay 3.0"
|
||||
|
||||
set_output_delay -clock clk 0.0 [get_ports out1]
|
||||
|
||||
|
|
@ -163,27 +145,20 @@ puts "--- Test 6: network modification invalidation ---"
|
|||
|
||||
# Add new instance
|
||||
set new_inst [make_instance extra_buf NangateOpenCellLibrary/BUF_X4]
|
||||
puts "PASS: make_instance"
|
||||
|
||||
set new_net [make_net extra_net]
|
||||
puts "PASS: make_net"
|
||||
|
||||
connect_pin extra_net extra_buf/A
|
||||
puts "PASS: connect_pin"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after add"
|
||||
|
||||
# Disconnect and delete
|
||||
disconnect_pin extra_net extra_buf/A
|
||||
puts "PASS: disconnect_pin"
|
||||
|
||||
delete_instance extra_buf
|
||||
delete_net extra_net
|
||||
puts "PASS: cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Replace cell triggers delay recalc
|
||||
|
|
@ -194,26 +169,21 @@ puts "--- Test 7: replace cell ---"
|
|||
# Replace buf1 with larger buffer
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: replace buf1 -> BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: replace buf1 -> BUF_X2"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: replace buf1 -> BUF_X1 (restore)"
|
||||
|
||||
# Replace multiple cells
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X2
|
||||
replace_cell or1 NangateOpenCellLibrary/OR2_X2
|
||||
report_checks
|
||||
puts "PASS: replace multiple cells"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X1
|
||||
replace_cell or1 NangateOpenCellLibrary/OR2_X1
|
||||
report_checks
|
||||
puts "PASS: restore cells"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 8: Tolerance with calculator switching
|
||||
|
|
@ -225,25 +195,18 @@ sta::set_delay_calc_incremental_tolerance 0.1
|
|||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with tolerance"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore with tolerance"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with tolerance"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit with tolerance"
|
||||
|
||||
# Restore
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
sta::set_delay_calc_incremental_tolerance 0.0
|
||||
|
||||
report_checks
|
||||
puts "PASS: final report"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -51,19 +51,14 @@ puts "is_delay_calc_name nonexistent: $invalid"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: SPEF with default calc ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef"
|
||||
|
||||
report_checks
|
||||
puts "PASS: default calc with SPEF"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: default min with SPEF"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: in1->out with SPEF"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: in2->out with SPEF"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Prima with varying reduce order
|
||||
|
|
@ -75,52 +70,46 @@ puts "set prima: $msg"
|
|||
|
||||
# Default prima
|
||||
report_checks
|
||||
puts "PASS: prima default order"
|
||||
|
||||
# Prima reduce order 1 (minimal)
|
||||
catch {sta::set_prima_reduce_order 1} msg
|
||||
puts "set_prima_reduce_order 1: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 1"
|
||||
|
||||
# Prima reduce order 2
|
||||
catch {sta::set_prima_reduce_order 2} msg
|
||||
puts "set_prima_reduce_order 2: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 2"
|
||||
|
||||
# Prima reduce order 3
|
||||
catch {sta::set_prima_reduce_order 3} msg
|
||||
puts "set_prima_reduce_order 3: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 3"
|
||||
|
||||
# Prima reduce order 5 (higher order)
|
||||
catch {sta::set_prima_reduce_order 5} msg
|
||||
puts "set_prima_reduce_order 5: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 5"
|
||||
|
||||
# report_dcalc with different orders
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
|
||||
puts "prima dcalc u1 order=5: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
|
||||
puts "prima dcalc u2 order=5: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
|
||||
puts "prima dcalc r1 order=5: done"
|
||||
|
||||
# Switch back to lower order
|
||||
catch {sta::set_prima_reduce_order 2} msg
|
||||
sta::set_prima_reduce_order 2
|
||||
report_checks
|
||||
puts "PASS: prima order back to 2"
|
||||
|
||||
# report_dcalc at order 2
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
|
||||
puts "prima dcalc u1 order=2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max
|
||||
puts "prima dcalc r3 order=2: done"
|
||||
|
||||
# Various slew values with prima
|
||||
|
|
@ -140,10 +129,8 @@ catch {set_delay_calculator arnoldi} msg
|
|||
puts "set arnoldi: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi with SPEF"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: arnoldi min"
|
||||
|
||||
# Various slew values with arnoldi
|
||||
foreach slew_val {1 10 50 100} {
|
||||
|
|
@ -162,29 +149,29 @@ foreach load_val {0.0001 0.001 0.01 0.05} {
|
|||
set_load 0 [get_ports out]
|
||||
|
||||
# report_dcalc with arnoldi
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max
|
||||
puts "arnoldi dcalc u1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y] -max
|
||||
puts "arnoldi dcalc u2 A: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max} msg
|
||||
report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y] -max
|
||||
puts "arnoldi dcalc u2 B: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max
|
||||
puts "arnoldi dcalc r1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -min} msg
|
||||
report_dcalc -from [get_pins r2/CLK] -to [get_pins r2/Q] -min
|
||||
puts "arnoldi dcalc r2 min: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max
|
||||
puts "arnoldi dcalc r3: done"
|
||||
|
||||
# DFF check arcs
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -max
|
||||
puts "arnoldi r1 setup: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min} msg
|
||||
report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/D] -min
|
||||
puts "arnoldi r1 hold: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
|
|
@ -195,31 +182,24 @@ puts "--- Test 5: rapid engine switching ---"
|
|||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole"
|
||||
|
||||
catch {set_delay_calculator prima} msg
|
||||
set_delay_calculator prima
|
||||
report_checks
|
||||
puts "PASS: prima"
|
||||
|
||||
catch {set_delay_calculator arnoldi} msg
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: arnoldi"
|
||||
|
||||
set_delay_calculator unit
|
||||
report_checks
|
||||
puts "PASS: unit"
|
||||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: back to dmp_ceff_elmore"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: find_delays explicit call
|
||||
|
|
@ -228,11 +208,9 @@ puts "PASS: back to dmp_ceff_elmore"
|
|||
puts "--- Test 6: find_delays ---"
|
||||
|
||||
sta::find_delays
|
||||
puts "PASS: find_delays"
|
||||
|
||||
sta::delays_invalid
|
||||
sta::find_delays
|
||||
puts "PASS: delays_invalid + find_delays"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Detailed report_checks with various formats after SPEF
|
||||
|
|
@ -240,21 +218,13 @@ puts "PASS: delays_invalid + find_delays"
|
|||
puts "--- Test 7: report formats ---"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -format full_clock_expanded
|
||||
puts "PASS: full_clock_expanded"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count"
|
||||
|
||||
report_checks -group_count 2
|
||||
puts "PASS: group_count"
|
||||
|
||||
report_checks -digits 6
|
||||
puts "PASS: 6 digits"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,7 +21,6 @@ set_propagated_clock {clk1 clk2 clk3}
|
|||
# Read SPEF parasitics
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test prima delay calculator
|
||||
|
|
@ -31,19 +30,14 @@ catch {set_delay_calculator prima} msg
|
|||
puts "set_delay_calculator prima: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: prima report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: prima min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: prima max path"
|
||||
|
||||
report_checks -fields {slew cap input_pins}
|
||||
puts "PASS: prima with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: prima full_clock"
|
||||
|
||||
# report_dcalc with prima
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
|
|
@ -69,10 +63,8 @@ puts "prima dcalc r3 hold: $msg"
|
|||
|
||||
# Report from different paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: prima in1->out"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: prima in2->out"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Now switch to arnoldi and compare
|
||||
|
|
@ -82,7 +74,6 @@ catch {set_delay_calculator arnoldi} msg
|
|||
puts "set_delay_calculator arnoldi: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "arnoldi dcalc u1 A->Y max: $msg"
|
||||
|
|
@ -97,7 +88,6 @@ catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -min} msg
|
|||
puts "arnoldi dcalc r1 CLK->Q min: $msg"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi with full fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch to lumped_cap with parasitics
|
||||
|
|
@ -106,7 +96,6 @@ puts "--- lumped_cap with parasitics ---"
|
|||
set_delay_calculator lumped_cap
|
||||
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "lumped_cap dcalc u1: $msg"
|
||||
|
|
@ -118,13 +107,10 @@ puts "--- dmp_ceff_two_pole with parasitics ---"
|
|||
set_delay_calculator dmp_ceff_two_pole
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: dmp_ceff_two_pole min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: dmp_ceff_two_pole max"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y] -max} msg
|
||||
puts "dmp_ceff_two_pole dcalc u1: $msg"
|
||||
|
|
@ -139,7 +125,6 @@ catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q] -max} msg
|
|||
puts "dmp_ceff_two_pole dcalc r1 CLK->Q: $msg"
|
||||
|
||||
report_checks -fields {slew cap}
|
||||
puts "PASS: dmp_ceff_two_pole with fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Switch back to default
|
||||
|
|
@ -148,6 +133,3 @@ puts "--- dmp_ceff_elmore (default) ---"
|
|||
set_delay_calculator dmp_ceff_elmore
|
||||
|
||||
report_checks
|
||||
puts "PASS: default dcalc with parasitics"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -17,24 +17,20 @@ source ../../test/helpers.tcl
|
|||
# Read Nangate45 library and search_test1 design
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
read_verilog ../../search/test/search_test1.v
|
||||
link_design search_test1
|
||||
puts "PASS: link search_test1"
|
||||
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
|
||||
set_output_delay -clock clk 2.0 [get_ports out1]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: SDC setup"
|
||||
|
||||
############################################################
|
||||
# Read SPEF parasitics for example1
|
||||
# This exercises SPEF parsing and parasitic model construction
|
||||
############################################################
|
||||
read_spef ../../search/test/search_test1.spef
|
||||
puts "PASS: read SPEF"
|
||||
|
||||
############################################################
|
||||
# Test Prima with Nangate45 + SPEF
|
||||
|
|
@ -45,39 +41,24 @@ catch {set_delay_calculator prima} msg
|
|||
puts "set prima: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: prima report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: prima min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: prima max path"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: prima with fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: prima full_clock"
|
||||
|
||||
# Multiple endpoint paths
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: prima endpoint_count 5"
|
||||
|
||||
# From/to specific paths
|
||||
catch {
|
||||
report_checks -from [get_ports in1] -endpoint_count 3
|
||||
puts "PASS: prima from in1"
|
||||
}
|
||||
report_checks -from [get_ports in1] -endpoint_count 3
|
||||
|
||||
catch {
|
||||
report_checks -to [get_ports out1] -endpoint_count 3
|
||||
puts "PASS: prima to out1"
|
||||
}
|
||||
report_checks -to [get_ports out1] -endpoint_count 3
|
||||
|
||||
catch {
|
||||
report_checks -from [get_ports in2] -endpoint_count 3
|
||||
puts "PASS: prima from in2"
|
||||
}
|
||||
report_checks -from [get_ports in2] -endpoint_count 3
|
||||
|
||||
############################################################
|
||||
# Prima with varying reduce orders
|
||||
|
|
@ -87,30 +68,25 @@ puts "--- prima reduce order ---"
|
|||
catch {sta::set_prima_reduce_order 1} msg
|
||||
puts "set_prima_reduce_order 1: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 1"
|
||||
|
||||
catch {sta::set_prima_reduce_order 2} msg
|
||||
puts "set_prima_reduce_order 2: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 2"
|
||||
|
||||
catch {sta::set_prima_reduce_order 3} msg
|
||||
puts "set_prima_reduce_order 3: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 3"
|
||||
|
||||
catch {sta::set_prima_reduce_order 4} msg
|
||||
puts "set_prima_reduce_order 4: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 4"
|
||||
|
||||
catch {sta::set_prima_reduce_order 5} msg
|
||||
puts "set_prima_reduce_order 5: $msg"
|
||||
report_checks
|
||||
puts "PASS: prima order 5"
|
||||
|
||||
# Reset to default
|
||||
catch {sta::set_prima_reduce_order 3} msg
|
||||
sta::set_prima_reduce_order 3
|
||||
|
||||
############################################################
|
||||
# Prima with varying slew
|
||||
|
|
@ -118,15 +94,12 @@ catch {sta::set_prima_reduce_order 3} msg
|
|||
puts "--- prima varying slew ---"
|
||||
set_input_transition 0.05 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: prima slew=0.05"
|
||||
|
||||
set_input_transition 0.5 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: prima slew=0.5"
|
||||
|
||||
set_input_transition 2.0 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: prima slew=2.0"
|
||||
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
|
||||
|
|
@ -142,7 +115,6 @@ foreach load_val {0.0001 0.001 0.005 0.01 0.05} {
|
|||
}
|
||||
set_load 0 [get_ports out1]
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: prima varying loads"
|
||||
|
||||
############################################################
|
||||
# Prima report_dcalc for specific arcs
|
||||
|
|
@ -158,19 +130,16 @@ puts "first cell: $cell_name"
|
|||
# Try dcalc on various cells
|
||||
foreach cell_obj $all_cells {
|
||||
set cname [get_name $cell_obj]
|
||||
catch {
|
||||
set ref [get_property $cell_obj ref_name]
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {
|
||||
report_dcalc -from $in_pin -to $out_pin -max
|
||||
}
|
||||
set ref [get_property $cell_obj ref_name]
|
||||
set pins [get_pins $cname/*]
|
||||
if {[llength $pins] >= 2} {
|
||||
set in_pin [lindex $pins 0]
|
||||
set out_pin [lindex $pins end]
|
||||
catch {
|
||||
report_dcalc -from $in_pin -to $out_pin -max
|
||||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: prima report_dcalc"
|
||||
|
||||
############################################################
|
||||
# Switch to Arnoldi
|
||||
|
|
@ -181,19 +150,14 @@ catch {set_delay_calculator arnoldi} msg
|
|||
puts "set arnoldi: $msg"
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: arnoldi min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: arnoldi max"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: arnoldi with fields"
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: arnoldi endpoint_count 5"
|
||||
|
||||
# Arnoldi with varying slew
|
||||
puts "--- arnoldi varying slew ---"
|
||||
|
|
@ -203,7 +167,6 @@ foreach slew_val {0.01 0.05 0.1 0.5 1.0 5.0} {
|
|||
puts "arnoldi slew=$slew_val: done"
|
||||
}
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: arnoldi varying slew"
|
||||
|
||||
# Arnoldi with varying loads
|
||||
puts "--- arnoldi varying loads ---"
|
||||
|
|
@ -213,7 +176,6 @@ foreach load_val {0.0001 0.001 0.01 0.05 0.1} {
|
|||
puts "arnoldi load=$load_val: done"
|
||||
}
|
||||
set_load 0 [get_ports out1]
|
||||
puts "PASS: arnoldi varying loads"
|
||||
|
||||
############################################################
|
||||
# Engine switching with SPEF
|
||||
|
|
@ -222,38 +184,30 @@ puts "--- engine switching ---"
|
|||
|
||||
set_delay_calculator dmp_ceff_elmore
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_elmore"
|
||||
|
||||
set_delay_calculator dmp_ceff_two_pole
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole"
|
||||
|
||||
set_delay_calculator lumped_cap
|
||||
report_checks
|
||||
puts "PASS: lumped_cap"
|
||||
|
||||
catch {set_delay_calculator prima}
|
||||
set_delay_calculator prima
|
||||
report_checks
|
||||
puts "PASS: prima after switching"
|
||||
|
||||
catch {set_delay_calculator arnoldi}
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: arnoldi after switching"
|
||||
|
||||
############################################################
|
||||
# Re-read SPEF and re-compute
|
||||
############################################################
|
||||
puts "--- re-read SPEF ---"
|
||||
read_spef ../../search/test/search_test1.spef
|
||||
puts "PASS: re-read SPEF"
|
||||
|
||||
catch {set_delay_calculator prima}
|
||||
set_delay_calculator prima
|
||||
report_checks
|
||||
puts "PASS: prima after SPEF re-read"
|
||||
|
||||
catch {set_delay_calculator arnoldi}
|
||||
set_delay_calculator arnoldi
|
||||
report_checks
|
||||
puts "PASS: arnoldi after SPEF re-read"
|
||||
|
||||
############################################################
|
||||
# Incremental updates
|
||||
|
|
@ -262,14 +216,9 @@ puts "--- incremental updates ---"
|
|||
|
||||
set_load 0.005 [get_ports out1]
|
||||
report_checks
|
||||
puts "PASS: arnoldi incremental load"
|
||||
|
||||
create_clock -name clk -period 5 [get_ports clk]
|
||||
report_checks
|
||||
puts "PASS: arnoldi incremental clock"
|
||||
|
||||
set_input_transition 1.0 [all_inputs]
|
||||
report_checks
|
||||
puts "PASS: arnoldi incremental slew"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,60 +0,0 @@
|
|||
No paths found.
|
||||
PASS: delay calculation completed
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ input external delay
|
||||
0.00 0.00 ^ in1 (in)
|
||||
0.02 0.02 ^ buf1/Z (BUF_X1)
|
||||
0.01 0.02 v inv1/ZN (INV_X1)
|
||||
0.00 0.02 v reg1/D (DFF_X1)
|
||||
0.02 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 clock reconvergence pessimism
|
||||
0.00 ^ reg1/CK (DFF_X1)
|
||||
0.00 0.00 library hold time
|
||||
0.00 data required time
|
||||
---------------------------------------------------------
|
||||
0.00 data required time
|
||||
-0.02 data arrival time
|
||||
---------------------------------------------------------
|
||||
0.02 slack (MET)
|
||||
|
||||
|
||||
PASS: min path delay reported
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
0.00 0.00 ^ reg1/CK (DFF_X1)
|
||||
0.08 0.08 ^ reg1/Q (DFF_X1)
|
||||
0.00 0.08 ^ out1 (out)
|
||||
0.08 data arrival time
|
||||
|
||||
10.00 10.00 clock clk (rise edge)
|
||||
0.00 10.00 clock network delay (ideal)
|
||||
0.00 10.00 clock reconvergence pessimism
|
||||
0.00 10.00 output external delay
|
||||
10.00 data required time
|
||||
---------------------------------------------------------
|
||||
10.00 data required time
|
||||
-0.08 data arrival time
|
||||
---------------------------------------------------------
|
||||
9.92 slack (MET)
|
||||
|
||||
|
||||
PASS: max path delay reported
|
||||
ALL PASSED
|
||||
|
|
@ -9,13 +9,8 @@ set_output_delay -clock clk 0 [get_ports out1]
|
|||
|
||||
# Force delay calculation
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: delay calculation completed"
|
||||
|
||||
# Report arrival/required
|
||||
report_checks -path_delay min
|
||||
puts "PASS: min path delay reported"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: max path delay reported"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,905 +0,0 @@
|
|||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
--- Reading SPEF ---
|
||||
PASS: read_spef completed
|
||||
--- report_checks with parasitics (default dcalc) ---
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.46 503.46 library setup time
|
||||
503.46 data required time
|
||||
---------------------------------------------------------
|
||||
503.46 data required time
|
||||
-201.72 data arrival time
|
||||
---------------------------------------------------------
|
||||
301.74 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with parasitics
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
12.16 13.16 v r1/D (DFFHQx4_ASAP7_75t_R)
|
||||
13.16 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 clock reconvergence pessimism
|
||||
12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
12.51 24.61 library hold time
|
||||
24.61 data required time
|
||||
---------------------------------------------------------
|
||||
24.61 data required time
|
||||
-13.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
-11.46 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: report_checks min path with parasitics
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.30 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
61.03 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.46 503.46 library setup time
|
||||
503.46 data required time
|
||||
---------------------------------------------------------
|
||||
503.46 data required time
|
||||
-201.72 data arrival time
|
||||
---------------------------------------------------------
|
||||
301.74 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks max path with parasitics
|
||||
No paths found.
|
||||
PASS: report_checks in1->out with parasitics
|
||||
No paths found.
|
||||
PASS: report_checks in2->out with parasitics
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
13.92 10.00 0.00 0.00 ^ clk2 (in)
|
||||
48.38 12.11 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
13.98 22.89 63.51 75.62 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
50.73 14.24 89.86 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
13.97 47.36 35.06 124.92 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
66.26 15.35 140.27 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
14.02 56.47 45.68 185.95 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
73.39 15.77 201.72 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
201.72 data arrival time
|
||||
|
||||
0.00 500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock source latency
|
||||
13.81 10.00 0.00 500.00 ^ clk3 (in)
|
||||
47.79 11.92 511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
-8.46 503.46 library setup time
|
||||
503.46 data required time
|
||||
-----------------------------------------------------------------------
|
||||
503.46 data required time
|
||||
-201.72 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
301.74 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks with fields and full_clock
|
||||
--- report_dcalc with parasitics ---
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.27, Ceff=10.50
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 50.73
|
||||
| total_output_net_capacitance = 10.50
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 27.29 35.12
|
||||
80.00 | 32.30 40.08
|
||||
Table value = 35.06
|
||||
PVT scale factor = 1.00
|
||||
Delay = 35.06
|
||||
|
||||
------- input_net_transition = 50.73
|
||||
| total_output_net_capacitance = 10.50
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 20.70 37.28
|
||||
80.00 | 21.40 38.13
|
||||
Table value = 34.55
|
||||
PVT scale factor = 1.00
|
||||
Slew = 34.55
|
||||
Driver waveform slew = 47.36
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.27, Ceff=10.09
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.75
|
||||
| total_output_net_capacitance = 10.09
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 29.18 36.17
|
||||
80.00 | 36.09 43.28
|
||||
Table value = 35.98
|
||||
PVT scale factor = 1.00
|
||||
Delay = 35.98
|
||||
|
||||
------- input_net_transition = 48.75
|
||||
| total_output_net_capacitance = 10.09
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 18.15 31.72
|
||||
80.00 | 19.36 32.63
|
||||
Table value = 28.57
|
||||
PVT scale factor = 1.00
|
||||
Slew = 28.57
|
||||
Driver waveform slew = 40.66
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc BUF arc with parasitics
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.90
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 50.41
|
||||
| total_output_net_capacitance = 10.90
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 31.28 40.48
|
||||
80.00 | 36.30 45.47
|
||||
Table value = 40.79
|
||||
PVT scale factor = 1.00
|
||||
Delay = 40.79
|
||||
|
||||
------- input_net_transition = 50.41
|
||||
| total_output_net_capacitance = 10.90
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 24.52 43.68
|
||||
80.00 | 25.29 44.42
|
||||
Table value = 41.80
|
||||
PVT scale factor = 1.00
|
||||
Slew = 41.80
|
||||
Driver waveform slew = 55.90
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.35
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 48.36
|
||||
| total_output_net_capacitance = 10.35
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 35.35 43.09
|
||||
80.00 | 44.73 52.65
|
||||
Table value = 43.51
|
||||
PVT scale factor = 1.00
|
||||
Delay = 43.51
|
||||
|
||||
------- input_net_transition = 48.36
|
||||
| total_output_net_capacitance = 10.35
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 20.09 35.08
|
||||
80.00 | 21.45 36.06
|
||||
Table value = 32.26
|
||||
PVT scale factor = 1.00
|
||||
Slew = 32.26
|
||||
Driver waveform slew = 45.57
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc AND2 A->Y with parasitics
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
B ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.94
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 66.26
|
||||
| total_output_net_capacitance = 10.94
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 33.56 42.69
|
||||
80.00 | 39.48 48.65
|
||||
Table value = 45.68
|
||||
PVT scale factor = 1.00
|
||||
Delay = 45.68
|
||||
|
||||
------- input_net_transition = 66.26
|
||||
| total_output_net_capacitance = 10.94
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 24.73 43.75
|
||||
80.00 | 25.53 44.49
|
||||
Table value = 42.31
|
||||
PVT scale factor = 1.00
|
||||
Slew = 42.31
|
||||
Driver waveform slew = 56.47
|
||||
|
||||
.............................................
|
||||
|
||||
B v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.39
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 61.46
|
||||
| total_output_net_capacitance = 10.39
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 34.01 41.76
|
||||
80.00 | 42.66 50.55
|
||||
Table value = 44.94
|
||||
PVT scale factor = 1.00
|
||||
Delay = 44.94
|
||||
|
||||
------- input_net_transition = 61.46
|
||||
| total_output_net_capacitance = 10.39
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 20.11 35.08
|
||||
80.00 | 21.52 36.22
|
||||
Table value = 32.77
|
||||
PVT scale factor = 1.00
|
||||
Slew = 32.77
|
||||
Driver waveform slew = 45.94
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc AND2 B->Y with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.22, Ceff=9.22
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.22
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 59.92 64.09
|
||||
80.00 | 65.10 69.26
|
||||
Table value = 63.51
|
||||
PVT scale factor = 1.00
|
||||
Delay = 63.51
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.22
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 13.01 21.04
|
||||
80.00 | 13.01 21.05
|
||||
Table value = 17.83
|
||||
PVT scale factor = 1.00
|
||||
Slew = 17.83
|
||||
Driver waveform slew = 22.83
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.21, Ceff=8.89
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.89
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 57.80 61.63
|
||||
80.00 | 62.64 66.47
|
||||
Table value = 60.90
|
||||
PVT scale factor = 1.00
|
||||
Delay = 60.90
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.89
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 11.30 17.99
|
||||
80.00 | 11.31 17.98
|
||||
Table value = 14.94
|
||||
PVT scale factor = 1.00
|
||||
Slew = 14.94
|
||||
Driver waveform slew = 19.18
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF CLK->Q with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc sense: non_unate
|
||||
Arc type: Reg Clk to Q
|
||||
CLK ^ -> Q ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=6.70, Ceff=9.16
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.16
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 59.92 64.09
|
||||
80.00 | 65.10 69.26
|
||||
Table value = 63.46
|
||||
PVT scale factor = 1.00
|
||||
Delay = 63.46
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 9.16
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 13.01 21.04
|
||||
80.00 | 13.01 21.05
|
||||
Table value = 17.74
|
||||
PVT scale factor = 1.00
|
||||
Slew = 17.74
|
||||
Driver waveform slew = 22.31
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> Q v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=6.70, Ceff=8.85
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.85
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 57.80 61.63
|
||||
80.00 | 62.64 66.47
|
||||
Table value = 60.87
|
||||
PVT scale factor = 1.00
|
||||
Delay = 60.87
|
||||
|
||||
------- input_net_transition = 48.38
|
||||
| total_output_net_capacitance = 8.85
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
40.00 | 11.30 17.99
|
||||
80.00 | 11.31 17.98
|
||||
Table value = 14.89
|
||||
PVT scale factor = 1.00
|
||||
Slew = 14.89
|
||||
Driver waveform slew = 18.76
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF r3 CLK->Q max with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc type: setup
|
||||
CLK ^ -> D ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 73.39
|
||||
| related_pin_transition = 47.79
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | 6.68 5.15
|
||||
80.00 | 8.95 8.54
|
||||
Table value = 8.46
|
||||
PVT scale factor = 1.00
|
||||
Check = 8.46
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> D v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 65.45
|
||||
| related_pin_transition = 47.79
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | -2.23 -7.76
|
||||
80.00 | 5.88 -2.55
|
||||
Table value = 1.49
|
||||
PVT scale factor = 1.00
|
||||
Check = 1.49
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF setup check with parasitics
|
||||
Library: asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
Cell: DFFHQx4_ASAP7_75t_R
|
||||
Arc type: hold
|
||||
CLK ^ -> D ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 72.50
|
||||
| related_pin_transition = 48.38
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | -3.44 0.59
|
||||
80.00 | -1.12 0.23
|
||||
Table value = -1.17
|
||||
PVT scale factor = 1.00
|
||||
Check = -1.17
|
||||
|
||||
.............................................
|
||||
|
||||
CLK ^ -> D v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- constrained_pin_transition = 64.66
|
||||
| related_pin_transition = 48.38
|
||||
| 40.00 80.00
|
||||
v --------------------
|
||||
40.00 | 11.76 17.37
|
||||
80.00 | 9.46 16.46
|
||||
Table value = 11.70
|
||||
PVT scale factor = 1.00
|
||||
Check = 11.70
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: report_dcalc DFF hold check with parasitics
|
||||
--- Testing arnoldi delay calculator ---
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
204.96 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.80 503.12 library setup time
|
||||
503.12 data required time
|
||||
---------------------------------------------------------
|
||||
503.12 data required time
|
||||
-204.96 data arrival time
|
||||
---------------------------------------------------------
|
||||
298.15 slack (MET)
|
||||
|
||||
|
||||
PASS: arnoldi report_checks
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: min
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (ideal)
|
||||
1.00 1.00 v input external delay
|
||||
0.00 1.00 v in1 (in)
|
||||
12.16 13.16 v r1/D (DFFHQx4_ASAP7_75t_R)
|
||||
13.16 data arrival time
|
||||
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 clock reconvergence pessimism
|
||||
12.11 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
12.51 24.61 library hold time
|
||||
24.61 data required time
|
||||
---------------------------------------------------------
|
||||
24.61 data required time
|
||||
-13.16 data arrival time
|
||||
---------------------------------------------------------
|
||||
-11.46 slack (VIOLATED)
|
||||
|
||||
|
||||
PASS: arnoldi min path
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
12.11 12.11 clock network delay (propagated)
|
||||
0.00 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
49.15 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
62.20 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
204.96 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
11.92 511.92 clock network delay (propagated)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-8.80 503.12 library setup time
|
||||
503.12 data required time
|
||||
---------------------------------------------------------
|
||||
503.12 data required time
|
||||
-204.96 data arrival time
|
||||
---------------------------------------------------------
|
||||
298.15 slack (MET)
|
||||
|
||||
|
||||
PASS: arnoldi max path
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------
|
||||
0.00 0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
13.92 10.00 0.00 0.00 ^ clk2 (in)
|
||||
48.38 12.11 12.11 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
13.98 29.94 62.99 75.10 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
54.60 15.52 90.62 ^ u1/A (BUFx2_ASAP7_75t_R)
|
||||
13.97 54.12 33.63 124.25 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
71.52 17.95 142.20 ^ u2/B (AND2x2_ASAP7_75t_R)
|
||||
14.02 63.30 44.25 186.45 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
78.93 18.51 204.96 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
204.96 data arrival time
|
||||
|
||||
0.00 500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock source latency
|
||||
13.81 10.00 0.00 500.00 ^ clk3 (in)
|
||||
47.79 11.92 511.92 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
0.00 511.92 clock reconvergence pessimism
|
||||
-8.80 503.12 library setup time
|
||||
503.12 data required time
|
||||
-----------------------------------------------------------------------
|
||||
503.12 data required time
|
||||
-204.96 data arrival time
|
||||
-----------------------------------------------------------------------
|
||||
298.15 slack (MET)
|
||||
|
||||
|
||||
PASS: arnoldi report_checks with fields
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 54.60
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 35.12 50.39
|
||||
80.00 | 40.08 55.44
|
||||
Table value = 40.18
|
||||
PVT scale factor = 1.00
|
||||
Delay = 40.18
|
||||
|
||||
------- input_net_transition = 54.60
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 37.28 71.28
|
||||
80.00 | 38.13 71.69
|
||||
Table value = 44.77
|
||||
PVT scale factor = 1.00
|
||||
Slew = 44.77
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 52.63
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 36.17 49.65
|
||||
80.00 | 43.28 56.72
|
||||
Table value = 41.27
|
||||
PVT scale factor = 1.00
|
||||
Delay = 41.27
|
||||
|
||||
------- input_net_transition = 52.63
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 31.72 59.66
|
||||
80.00 | 32.63 60.23
|
||||
Table value = 37.92
|
||||
PVT scale factor = 1.00
|
||||
Slew = 37.92
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: arnoldi report_dcalc BUF
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 54.25
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 40.48 58.12
|
||||
80.00 | 45.47 63.31
|
||||
Table value = 46.10
|
||||
PVT scale factor = 1.00
|
||||
Delay = 46.10
|
||||
|
||||
------- input_net_transition = 54.25
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 43.68 82.62
|
||||
80.00 | 44.42 82.97
|
||||
Table value = 52.37
|
||||
PVT scale factor = 1.00
|
||||
Slew = 52.37
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 52.20
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 43.09 58.01
|
||||
80.00 | 52.65 67.66
|
||||
Table value = 49.25
|
||||
PVT scale factor = 1.00
|
||||
Delay = 49.25
|
||||
|
||||
------- input_net_transition = 52.20
|
||||
| total_output_net_capacitance = 14.02
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
40.00 | 35.08 65.82
|
||||
80.00 | 36.06 66.39
|
||||
Table value = 42.02
|
||||
PVT scale factor = 1.00
|
||||
Slew = 42.02
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: arnoldi report_dcalc AND2
|
||||
--- Testing lumped_cap with parasitics ---
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
59.07 59.07 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
35.39 94.45 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
47.16 141.62 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 141.62 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
141.62 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-10.20 489.80 library setup time
|
||||
489.80 data required time
|
||||
---------------------------------------------------------
|
||||
489.80 data required time
|
||||
-141.62 data arrival time
|
||||
---------------------------------------------------------
|
||||
348.18 slack (MET)
|
||||
|
||||
|
||||
PASS: lumped_cap with parasitics report_checks
|
||||
Library: asap7sc7p5t_INVBUF_RVT_FF_nldm_211120
|
||||
Cell: BUFx2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 24.64
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 31.25 46.51
|
||||
40.00 | 35.12 50.39
|
||||
Table value = 35.39
|
||||
PVT scale factor = 1.00
|
||||
Delay = 35.39
|
||||
|
||||
------- input_net_transition = 24.64
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 36.94 71.10
|
||||
40.00 | 37.28 71.28
|
||||
Table value = 44.26
|
||||
PVT scale factor = 1.00
|
||||
Slew = 44.26
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
P = 1.00 V = 0.77 T = 0.00
|
||||
------- input_net_transition = 20.95
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 31.07 44.53
|
||||
40.00 | 36.17 49.65
|
||||
Table value = 34.17
|
||||
PVT scale factor = 1.00
|
||||
Delay = 34.17
|
||||
|
||||
------- input_net_transition = 20.95
|
||||
| total_output_net_capacitance = 13.97
|
||||
| 11.52 23.04
|
||||
v --------------------
|
||||
20.00 | 31.25 59.40
|
||||
40.00 | 31.72 59.66
|
||||
Table value = 37.25
|
||||
PVT scale factor = 1.00
|
||||
Slew = 37.25
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: lumped_cap with parasitics report_dcalc
|
||||
--- Testing dmp_ceff_two_pole with parasitics ---
|
||||
|
||||
Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
Path Type: max
|
||||
|
||||
Delay Time Description
|
||||
---------------------------------------------------------
|
||||
0.00 0.00 clock clk (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
0.00 0.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
55.73 55.73 ^ r2/Q (DFFHQx4_ASAP7_75t_R)
|
||||
30.36 86.09 ^ u1/Y (BUFx2_ASAP7_75t_R)
|
||||
42.76 128.85 ^ u2/Y (AND2x2_ASAP7_75t_R)
|
||||
0.00 128.85 ^ r3/D (DFFHQx4_ASAP7_75t_R)
|
||||
128.85 data arrival time
|
||||
|
||||
500.00 500.00 clock clk (rise edge)
|
||||
0.00 500.00 clock network delay (propagated)
|
||||
0.00 500.00 clock reconvergence pessimism
|
||||
500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
|
||||
-10.53 489.47 library setup time
|
||||
489.47 data required time
|
||||
---------------------------------------------------------
|
||||
489.47 data required time
|
||||
-128.85 data arrival time
|
||||
---------------------------------------------------------
|
||||
360.62 slack (MET)
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with parasitics report_checks
|
||||
Library: asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120
|
||||
Cell: AND2x2_ASAP7_75t_R
|
||||
Arc sense: positive_unate
|
||||
Arc type: combinational
|
||||
A ^ -> Y ^
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.88
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 22.83
|
||||
| total_output_net_capacitance = 10.88
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
20.00 | 27.85 36.94
|
||||
40.00 | 31.28 40.48
|
||||
Table value = 36.43
|
||||
PVT scale factor = 1.00
|
||||
Delay = 36.43
|
||||
|
||||
------- input_net_transition = 22.83
|
||||
| total_output_net_capacitance = 10.88
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
20.00 | 24.09 43.36
|
||||
40.00 | 24.52 43.68
|
||||
Table value = 41.27
|
||||
PVT scale factor = 1.00
|
||||
Slew = 41.27
|
||||
Driver waveform slew = 55.45
|
||||
|
||||
.............................................
|
||||
|
||||
A v -> Y v
|
||||
Pi model C2=6.70 Rpi=2.42 C1=7.32, Ceff=10.29
|
||||
P = 1.00 V = 0.70 T = 25.00
|
||||
------- input_net_transition = 19.29
|
||||
| total_output_net_capacitance = 10.29
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
10.00 | 25.20 32.93
|
||||
20.00 | 28.93 36.68
|
||||
Table value = 34.76
|
||||
PVT scale factor = 1.00
|
||||
Delay = 34.76
|
||||
|
||||
------- input_net_transition = 19.29
|
||||
| total_output_net_capacitance = 10.29
|
||||
| 5.76 11.52
|
||||
v --------------------
|
||||
10.00 | 19.49 34.69
|
||||
20.00 | 19.55 34.72
|
||||
Table value = 31.48
|
||||
PVT scale factor = 1.00
|
||||
Slew = 31.48
|
||||
Driver waveform slew = 45.09
|
||||
|
||||
.............................................
|
||||
|
||||
|
||||
PASS: dmp_ceff_two_pole with parasitics report_dcalc
|
||||
ALL PASSED
|
||||
|
|
@ -22,30 +22,23 @@ set_propagated_clock {clk1 clk2 clk3}
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Reading SPEF ---"
|
||||
read_spef ../../test/reg1_asap7.spef
|
||||
puts "PASS: read_spef completed"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Default delay calculator (dmp_ceff_elmore) with parasitics
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with parasitics (default dcalc) ---"
|
||||
report_checks
|
||||
puts "PASS: report_checks with parasitics"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks min path with parasitics"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report_checks max path with parasitics"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out]
|
||||
puts "PASS: report_checks in1->out with parasitics"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out]
|
||||
puts "PASS: report_checks in2->out with parasitics"
|
||||
|
||||
# With fields for more coverage
|
||||
report_checks -fields {slew cap input_pins} -format full_clock
|
||||
puts "PASS: report_checks with fields and full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_dcalc with parasitics
|
||||
|
|
@ -55,34 +48,27 @@ puts "--- report_dcalc with parasitics ---"
|
|||
# BUF gate arc
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc BUF arc with parasitics"
|
||||
|
||||
# AND gate arc
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc AND2 A->Y with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/B] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc AND2 B->Y with parasitics"
|
||||
|
||||
# DFF clock-to-Q arc
|
||||
catch {report_dcalc -from [get_pins r1/CLK] -to [get_pins r1/Q]} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF CLK->Q with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/Q] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF r3 CLK->Q max with parasitics"
|
||||
|
||||
# DFF setup/hold check arcs
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -max} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF setup check with parasitics"
|
||||
|
||||
catch {report_dcalc -from [get_pins r3/CLK] -to [get_pins r3/D] -min} msg
|
||||
puts $msg
|
||||
puts "PASS: report_dcalc DFF hold check with parasitics"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Arnoldi delay calculator with parasitics
|
||||
|
|
@ -92,24 +78,18 @@ catch {set_delay_calculator arnoldi} msg
|
|||
puts $msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: arnoldi report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: arnoldi min path"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: arnoldi max path"
|
||||
|
||||
report_checks -fields {slew cap input_pins} -format full_clock
|
||||
puts "PASS: arnoldi report_checks with fields"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: arnoldi report_dcalc BUF"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: arnoldi report_dcalc AND2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Lumped cap delay calculator with parasitics
|
||||
|
|
@ -119,11 +99,9 @@ catch {set_delay_calculator lumped_cap} msg
|
|||
puts $msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: lumped_cap with parasitics report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins u1/A] -to [get_pins u1/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: lumped_cap with parasitics report_dcalc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# dmp_ceff_two_pole delay calculator with parasitics
|
||||
|
|
@ -133,10 +111,6 @@ catch {set_delay_calculator dmp_ceff_two_pole} msg
|
|||
puts $msg
|
||||
|
||||
report_checks
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics report_checks"
|
||||
|
||||
catch {report_dcalc -from [get_pins u2/A] -to [get_pins u2/Y]} msg
|
||||
puts $msg
|
||||
puts "PASS: dmp_ceff_two_pole with parasitics report_dcalc"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -25,7 +25,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks baseline
|
||||
--- report_checks -path_delay min ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -54,7 +53,6 @@ Path Type: min
|
|||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_delay min
|
||||
--- report_checks -path_delay max ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
|
|
@ -82,10 +80,8 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -path_delay max
|
||||
--- report_checks -from/-to ---
|
||||
No paths found.
|
||||
PASS: report_checks -from/-to
|
||||
--- report_checks -through ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -114,7 +110,6 @@ Path Type: max
|
|||
9.88 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -through
|
||||
--- get_timing_edges full combinations ---
|
||||
reg1 all edges: 1
|
||||
reg2 all edges: 1
|
||||
|
|
@ -122,11 +117,9 @@ reg2 all edges: 1
|
|||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: report_edges reg1 CK->Q
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: report_edges reg2 CK->Q
|
||||
CK -> QN Reg Clk to Q
|
||||
^ -> ^ 0.06:0.06
|
||||
^ -> v 0.06:0.06
|
||||
|
|
@ -142,7 +135,6 @@ CK -> D setup
|
|||
CK -> D hold
|
||||
^ -> ^ 0.05:0.05
|
||||
^ -> v 0.05:0.05
|
||||
PASS: report_edges from reg1/CK
|
||||
CK -> D setup
|
||||
^ -> ^ 0.03:0.03
|
||||
^ -> v 0.04:0.04
|
||||
|
|
@ -152,11 +144,9 @@ CK -> D hold
|
|||
reg1/Q -> D wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges to reg2/D
|
||||
--- disable_timing on port pin ---
|
||||
reg1 CK Q constraint
|
||||
reg2 CK Q constraint
|
||||
PASS: disabled CK->Q in lib cell
|
||||
Startpoint: d (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -184,8 +174,6 @@ Path Type: max
|
|||
8.93 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after lib cell disable
|
||||
PASS: unset lib cell disable
|
||||
--- set_disable_timing instance and back ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
|
|
@ -215,7 +203,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: instance disable
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -242,14 +229,12 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: instance unset disable
|
||||
--- report_slews for various pins ---
|
||||
d ^ 0.10:0.10 v 0.10:0.10
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
reg1/CK ^ 0.00:0.00 v 0.00:0.00
|
||||
reg1/Q ^ 0.01:0.01 v 0.01:0.01
|
||||
reg2/D ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: report_slews various pins
|
||||
--- report_check_types ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -304,7 +289,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_check_types
|
||||
--- report_checks with -format ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
|
|
@ -332,7 +316,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -format full_clock
|
||||
--- report_checks -unconstrained ---
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q (output port clocked by clk)
|
||||
|
|
@ -360,7 +343,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks unconstrained
|
||||
--- report_checks -group_count 2 ---
|
||||
Warning: graph_advanced.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -416,7 +398,6 @@ Path Type: max
|
|||
8.93 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -group_count 2
|
||||
--- report_checks -endpoint_count 2 ---
|
||||
Warning: graph_advanced.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -471,5 +452,3 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -endpoint_count 2
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -22,24 +22,19 @@ set_input_transition 0.1 [get_ports d]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
puts "PASS: report_checks baseline"
|
||||
|
||||
puts "--- report_checks -path_delay min ---"
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks -path_delay min"
|
||||
|
||||
puts "--- report_checks -path_delay max ---"
|
||||
report_checks -path_delay max
|
||||
puts "PASS: report_checks -path_delay max"
|
||||
|
||||
puts "--- report_checks -from/-to ---"
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
puts "PASS: report_checks -from/-to"
|
||||
|
||||
puts "--- report_checks -through ---"
|
||||
set rc [catch { report_checks -through [get_pins reg1/Q] } msg]
|
||||
if { $rc == 0 } {
|
||||
puts "PASS: report_checks -through"
|
||||
} else {
|
||||
puts "INFO: report_checks -through: $msg"
|
||||
}
|
||||
|
|
@ -56,16 +51,12 @@ puts "reg2 all edges: [llength $edges_all2]"
|
|||
|
||||
puts "--- report_edges for cells ---"
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
puts "PASS: report_edges reg1 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
puts "PASS: report_edges reg2 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg1/CK]
|
||||
puts "PASS: report_edges from reg1/CK"
|
||||
|
||||
report_edges -to [get_pins reg2/D]
|
||||
puts "PASS: report_edges to reg2/D"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# set_disable_timing / report_disabled_edges exercises more paths
|
||||
|
|
@ -73,25 +64,20 @@ puts "PASS: report_edges to reg2/D"
|
|||
puts "--- disable_timing on port pin ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
puts "PASS: disabled CK->Q in lib cell"
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks after lib cell disable"
|
||||
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
report_disabled_edges
|
||||
puts "PASS: unset lib cell disable"
|
||||
|
||||
puts "--- set_disable_timing instance and back ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: instance disable"
|
||||
|
||||
unset_disable_timing [get_cells reg1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: instance unset disable"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew reporting (exercises vertex slew access)
|
||||
|
|
@ -102,32 +88,24 @@ report_slews [get_ports q]
|
|||
report_slews [get_pins reg1/CK]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/D]
|
||||
puts "PASS: report_slews various pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Graph verification
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types"
|
||||
|
||||
puts "--- report_checks with -format ---"
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report_checks -format full_clock"
|
||||
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Additional graph traversals (exercises more vertex/edge paths)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -group_count 2 ---"
|
||||
report_checks -group_count 2
|
||||
puts "PASS: report_checks -group_count 2"
|
||||
|
||||
puts "--- report_checks -endpoint_count 2 ---"
|
||||
report_checks -endpoint_count 2
|
||||
puts "PASS: report_checks -endpoint_count 2"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ Path Type: max
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -60,22 +59,14 @@ Path Type: min
|
|||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks min
|
||||
--- Test 2: path queries ---
|
||||
No paths found.
|
||||
PASS: d1->q1
|
||||
No paths found.
|
||||
PASS: d1->q2 (reconvergent)
|
||||
No paths found.
|
||||
PASS: d2->q1
|
||||
No paths found.
|
||||
PASS: d3->q3
|
||||
No paths found.
|
||||
PASS: d4->q3
|
||||
No paths found.
|
||||
PASS: d1->q4 (reconvergent)
|
||||
No paths found.
|
||||
PASS: d3->q4 (reconvergent)
|
||||
--- Test 3: report with fields ---
|
||||
Warning: graph_bidirect.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
|
|
@ -111,7 +102,6 @@ Fanout Cap Slew Delay Time Description
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report with all fields
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -142,7 +132,6 @@ Path Type: max
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report full_clock
|
||||
Startpoint: d4 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -173,7 +162,6 @@ Path Type: min
|
|||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: min with slew/cap fields
|
||||
--- Test 4: fanin/fanout ---
|
||||
fanin to q2: 3
|
||||
fanout from d1: 13
|
||||
|
|
@ -716,7 +704,6 @@ Driver pins
|
|||
Load pins
|
||||
reg3/D input (DFF_X1) 1.06-1.14
|
||||
|
||||
PASS: report_net all
|
||||
Instance buf1
|
||||
Cell: BUF_X1
|
||||
Library: NangateOpenCellLibrary
|
||||
|
|
@ -893,7 +880,6 @@ Instance reg4
|
|||
IQN internal (unconnected)
|
||||
VDD power (unconnected)
|
||||
VSS ground (unconnected)
|
||||
PASS: report_instance all
|
||||
--- Test 7: modify graph ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -925,7 +911,6 @@ Path Type: max
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report after add instance
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -956,5 +941,3 @@ Path Type: max
|
|||
9.83 slack (MET)
|
||||
|
||||
|
||||
PASS: report after delete instance
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
# Test graph construction with bidirectional pins, reconvergent paths,
|
||||
# and various edge/vertex operations.
|
||||
# Targets: Graph.cc uncovered paths:
|
||||
# makePinVertices for bidirect pins (lines 425-427)
|
||||
# pinVertices for bidirect direction (lines 453-455)
|
||||
# pinDrvrVertex for bidirect (lines 463-464)
|
||||
# makePortInstanceEdges: bidirect from_bidirect_drvr_vertex path (lines 223-229)
|
||||
# makeWireEdgesFromPin with multiple drivers (lines 277-301)
|
||||
# hasFaninOne (line 507-511)
|
||||
# gateEdgeArc (line 544+)
|
||||
# deleteVertex (lines 476-504) via delete operations
|
||||
# isIsolatedNet (lines 309-331)
|
||||
# makePinVertices for bidirect pins
|
||||
# pinVertices for bidirect direction
|
||||
# pinDrvrVertex for bidirect
|
||||
# makePortInstanceEdges: bidirect from_bidirect_drvr_vertex path
|
||||
# makeWireEdgesFromPin with multiple drivers
|
||||
# hasFaninOne
|
||||
# gateEdgeArc
|
||||
# deleteVertex via delete operations
|
||||
# isIsolatedNet
|
||||
# vertex/edge iterators
|
||||
|
||||
source ../../test/helpers.tcl
|
||||
|
|
@ -28,106 +28,82 @@ set_output_delay -clock clk 0 [get_ports {q1 q2 q3 q4}]
|
|||
set_input_transition 0.1 [get_ports {d1 d2 d3 d4 clk}]
|
||||
|
||||
report_checks
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: report_checks min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Multiple path queries (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 2: path queries ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: d1->q2 (reconvergent)"
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q1]
|
||||
puts "PASS: d2->q1"
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q3]
|
||||
puts "PASS: d3->q3"
|
||||
|
||||
report_checks -from [get_ports d4] -to [get_ports q3]
|
||||
puts "PASS: d4->q3"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q4]
|
||||
puts "PASS: d1->q4 (reconvergent)"
|
||||
|
||||
report_checks -from [get_ports d3] -to [get_ports q4]
|
||||
puts "PASS: d3->q4 (reconvergent)"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Fields that exercise graph delay/slew queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 3: report with fields ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: report with all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: report full_clock"
|
||||
|
||||
report_checks -path_delay min -fields {slew cap}
|
||||
puts "PASS: min with slew/cap fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Fanin/fanout queries through reconvergent paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 4: fanin/fanout ---"
|
||||
catch {
|
||||
set fi [get_fanin -to [get_ports q2] -flat]
|
||||
puts "fanin to q2: [llength $fi]"
|
||||
} msg
|
||||
set fi [get_fanin -to [get_ports q2] -flat]
|
||||
puts "fanin to q2: [llength $fi]"
|
||||
|
||||
catch {
|
||||
set fo [get_fanout -from [get_ports d1] -flat]
|
||||
puts "fanout from d1: [llength $fo]"
|
||||
} msg
|
||||
set fo [get_fanout -from [get_ports d1] -flat]
|
||||
puts "fanout from d1: [llength $fo]"
|
||||
|
||||
catch {
|
||||
set fi_cells [get_fanin -to [get_ports q2] -only_cells]
|
||||
puts "fanin cells to q2: [llength $fi_cells]"
|
||||
} msg
|
||||
set fi_cells [get_fanin -to [get_ports q2] -only_cells]
|
||||
puts "fanin cells to q2: [llength $fi_cells]"
|
||||
|
||||
catch {
|
||||
set fo_cells [get_fanout -from [get_ports d1] -only_cells]
|
||||
puts "fanout cells from d1: [llength $fo_cells]"
|
||||
} msg
|
||||
set fo_cells [get_fanout -from [get_ports d1] -only_cells]
|
||||
puts "fanout cells from d1: [llength $fo_cells]"
|
||||
|
||||
catch {
|
||||
set fi_q3 [get_fanin -to [get_ports q3] -flat]
|
||||
puts "fanin to q3: [llength $fi_q3]"
|
||||
} msg
|
||||
set fi_q3 [get_fanin -to [get_ports q3] -flat]
|
||||
puts "fanin to q3: [llength $fi_q3]"
|
||||
|
||||
catch {
|
||||
set fo_d3 [get_fanout -from [get_ports d3] -flat]
|
||||
puts "fanout from d3: [llength $fo_d3]"
|
||||
} msg
|
||||
set fo_d3 [get_fanout -from [get_ports d3] -flat]
|
||||
puts "fanout from d3: [llength $fo_d3]"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: report_dcalc exercises graph edge arc queries
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 5: report_dcalc ---"
|
||||
catch {report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max} msg
|
||||
report_dcalc -from [get_pins buf1/A] -to [get_pins buf1/Z] -max
|
||||
puts "dcalc buf1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max} msg
|
||||
report_dcalc -from [get_pins and1/A1] -to [get_pins and1/ZN] -max
|
||||
puts "dcalc and1 A1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max} msg
|
||||
report_dcalc -from [get_pins and1/A2] -to [get_pins and1/ZN] -max
|
||||
puts "dcalc and1 A2: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max} msg
|
||||
report_dcalc -from [get_pins or1/A1] -to [get_pins or1/ZN] -max
|
||||
puts "dcalc or1 A1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max} msg
|
||||
report_dcalc -from [get_pins nand1/A1] -to [get_pins nand1/ZN] -max
|
||||
puts "dcalc nand1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max} msg
|
||||
report_dcalc -from [get_pins nor1/A1] -to [get_pins nor1/ZN] -max
|
||||
puts "dcalc nor1: done"
|
||||
|
||||
catch {report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
report_dcalc -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "dcalc reg1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
|
|
@ -141,14 +117,12 @@ set all_nets [get_nets *]
|
|||
puts "total nets: [llength $all_nets]"
|
||||
|
||||
foreach net_name {n1 n2 n3 n4 n5 n6 n7 n8 n9 n10} {
|
||||
catch {report_net $net_name} msg
|
||||
report_net $net_name
|
||||
}
|
||||
puts "PASS: report_net all"
|
||||
|
||||
foreach inst_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 reg4} {
|
||||
report_instance $inst_name
|
||||
}
|
||||
puts "PASS: report_instance all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Add and remove instances (exercises deleteVertex, graph modify)
|
||||
|
|
@ -159,13 +133,9 @@ set new_inst [make_instance test_buf BUF_X1]
|
|||
connect_pin test_net test_buf/A
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after add instance"
|
||||
|
||||
disconnect_pin test_net test_buf/A
|
||||
delete_instance test_buf
|
||||
delete_net test_net
|
||||
|
||||
report_checks
|
||||
puts "PASS: report after delete instance"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@ Corner: fast
|
|||
8.88 slack (MET)
|
||||
|
||||
|
||||
PASS: fast corner
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -62,7 +61,6 @@ Corner: fast
|
|||
1.03 slack (MET)
|
||||
|
||||
|
||||
PASS: fast corner min
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -96,7 +94,6 @@ Corner: fast
|
|||
8.88 slack (MET)
|
||||
|
||||
|
||||
PASS: fast corner max
|
||||
--- slow corner ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -131,7 +128,6 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: slow corner
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -161,7 +157,6 @@ Corner: slow
|
|||
1.10 slack (MET)
|
||||
|
||||
|
||||
PASS: slow corner min
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -195,7 +190,6 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: slow corner max
|
||||
--- report_dcalc per corner ---
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: BUF_X1
|
||||
|
|
@ -811,7 +805,6 @@ Check = 0.00
|
|||
.............................................
|
||||
|
||||
slow reg1 hold: done
|
||||
PASS: report_dcalc per corner
|
||||
--- report_checks with fields ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -851,7 +844,6 @@ Corner: fast
|
|||
8.88 slack (MET)
|
||||
|
||||
|
||||
PASS: fast fields
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -890,7 +882,6 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: slow fields
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -924,7 +915,6 @@ Corner: fast
|
|||
8.88 slack (MET)
|
||||
|
||||
|
||||
PASS: fast full_clock
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -958,20 +948,13 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: slow full_clock
|
||||
--- multi-corner paths ---
|
||||
No paths found.
|
||||
PASS: fast d1->q1
|
||||
No paths found.
|
||||
PASS: slow d1->q1
|
||||
No paths found.
|
||||
PASS: fast d2->q2
|
||||
No paths found.
|
||||
PASS: slow d2->q2
|
||||
No paths found.
|
||||
PASS: fast en->q1
|
||||
No paths found.
|
||||
PASS: slow en->q1
|
||||
--- timing edges multi-corner ---
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
|
|
@ -988,7 +971,6 @@ A1 -> ZN combinational
|
|||
A2 -> ZN combinational
|
||||
^ -> ^ 0.01:0.02:0.06:0.06
|
||||
v -> v 0.02:0.03:0.18:0.18
|
||||
PASS: timing edges multi-corner
|
||||
--- load changes multi-corner ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -1023,7 +1005,6 @@ Corner: fast
|
|||
8.88 slack (MET)
|
||||
|
||||
|
||||
PASS: fast after load change
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -1057,7 +1038,6 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: slow after load change
|
||||
--- unconstrained multi-corner ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -1092,7 +1072,6 @@ Corner: fast
|
|||
8.88 slack (MET)
|
||||
|
||||
|
||||
PASS: fast unconstrained
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -1126,7 +1105,6 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: slow unconstrained
|
||||
--- disable with multi-corner ---
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -1190,7 +1168,6 @@ Corner: slow
|
|||
8.43 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1 multi-corner
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -1257,5 +1234,3 @@ Corner: slow
|
|||
8.38 slack (MET)
|
||||
|
||||
|
||||
PASS: enable buf1 multi-corner
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -29,104 +29,86 @@ set_input_transition 0.1 [get_ports {d1 d2 en}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- fast corner ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast corner"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: fast corner min"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: fast corner max"
|
||||
|
||||
puts "--- slow corner ---"
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow corner"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: slow corner min"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: slow corner max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc (exercises delay subtraction/comparison)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_dcalc per corner ---"
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
report_dcalc -corner fast -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "fast inv1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]} msg
|
||||
report_dcalc -corner slow -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "slow inv1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins and1/A1] -to [get_pins and1/ZN]} msg
|
||||
report_dcalc -corner fast -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "fast and1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins and1/A1] -to [get_pins and1/ZN]} msg
|
||||
report_dcalc -corner slow -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "slow and1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins or1/A1] -to [get_pins or1/ZN]} msg
|
||||
report_dcalc -corner fast -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "fast or1 A1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins or1/A1] -to [get_pins or1/ZN]} msg
|
||||
report_dcalc -corner slow -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "slow or1 A1 dcalc: done"
|
||||
|
||||
# DFF arcs
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
puts "PASS: report_dcalc per corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields across corners (exercises graph slew access)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks with fields ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins}
|
||||
puts "PASS: fast fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins}
|
||||
puts "PASS: slow fields"
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
puts "PASS: fast full_clock"
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
puts "PASS: slow full_clock"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner paths (different paths in fast vs slow)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner paths ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: fast d1->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: slow d1->q1"
|
||||
|
||||
report_checks -corner fast -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: fast d2->q2"
|
||||
|
||||
report_checks -corner slow -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: slow d2->q2"
|
||||
|
||||
report_checks -corner fast -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: fast en->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: slow en->q1"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Edge queries with multi-corner
|
||||
|
|
@ -145,7 +127,6 @@ report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
|||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
report_edges -from [get_pins or1/A2] -to [get_pins or1/ZN]
|
||||
puts "PASS: timing edges multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner (exercises delay recomputation)
|
||||
|
|
@ -155,10 +136,8 @@ set_load 0.01 [get_ports q1]
|
|||
set_load 0.05 [get_ports q2]
|
||||
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after load change"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after load change"
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
|
|
@ -168,10 +147,8 @@ set_load 0 [get_ports q2]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- unconstrained multi-corner ---"
|
||||
report_checks -corner fast -unconstrained
|
||||
puts "PASS: fast unconstrained"
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
puts "PASS: slow unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable with multi-corner
|
||||
|
|
@ -180,11 +157,7 @@ puts "--- disable with multi-corner ---"
|
|||
set_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable buf1 multi-corner"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: enable buf1 multi-corner"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline max
|
||||
Startpoint: d3 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -59,7 +58,6 @@ Path Type: min
|
|||
1.03 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
Warning: graph_delete_modify.tcl line 1, unknown field nets.
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -94,9 +92,7 @@ Fanout Cap Slew Delay Time Description
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline fields
|
||||
--- Test 2: add/delete multiple instances ---
|
||||
PASS: added buffer chain
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -127,7 +123,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after add chain
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -158,7 +153,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after partial disconnect
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -189,8 +183,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after reconnect
|
||||
PASS: full cleanup
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -221,7 +213,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after full cleanup
|
||||
--- Test 3: replace_cell ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -256,7 +247,6 @@ Path Type: max
|
|||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.05:0.05
|
||||
PASS: buf1 -> BUF_X4
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -287,7 +277,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 -> BUF_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -318,7 +307,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 restored
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -349,7 +337,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 -> AND2_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -380,7 +367,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 restored
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -411,7 +397,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 -> INV_X2
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -442,7 +427,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 restored
|
||||
--- Test 4: add/delete register ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -474,8 +458,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with added register
|
||||
PASS: register removed
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -506,7 +488,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after register removal
|
||||
--- Test 5: rapid connect/disconnect ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -601,7 +582,6 @@ Path Type: max
|
|||
|
||||
|
||||
cycle 3 done
|
||||
PASS: rapid cycles
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -632,7 +612,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after rapid cycles
|
||||
--- Test 6: edge queries ---
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
|
|
@ -645,14 +624,12 @@ reg1 edges: 1
|
|||
reg2 edges: 1
|
||||
reg3 edges: 1
|
||||
reg4 edges: 1
|
||||
PASS: edge queries
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
reg1/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
PASS: slew queries
|
||||
--- Test 7: through pins ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -747,5 +724,3 @@ Path Type: max
|
|||
|
||||
|
||||
through and1: done
|
||||
PASS: through pin queries
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# Test graph modification: add/delete vertices via connect_pin/disconnect_pin,
|
||||
# delete_instance, replace_cell, and repeated graph rebuild.
|
||||
# Targets:
|
||||
# Graph.cc: deleteVertex (lines 476-504), deleteInEdge, deleteOutEdge,
|
||||
# Graph.cc: deleteVertex, deleteInEdge, deleteOutEdge,
|
||||
# makePinVertices, makeVertex, makeWireEdgesFromPin (multi-driver),
|
||||
# hasFaninOne, makeInstEdges after replace_cell,
|
||||
# removeWireEdge, removeInstEdge on disconnect/reconnect,
|
||||
|
|
@ -23,13 +23,10 @@ set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline ---"
|
||||
report_checks
|
||||
puts "PASS: baseline max"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: baseline fields"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add multiple instances and nets, then delete
|
||||
|
|
@ -49,20 +46,16 @@ connect_pin test_net_a test_buf_a/A
|
|||
connect_pin test_net_b test_buf_a/Z
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
connect_pin test_net_c test_buf_b/Z
|
||||
puts "PASS: added buffer chain"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after add chain"
|
||||
|
||||
# Disconnect middle and verify
|
||||
disconnect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
puts "PASS: timing after partial disconnect"
|
||||
|
||||
# Reconnect
|
||||
connect_pin test_net_b test_buf_b/A
|
||||
report_checks
|
||||
puts "PASS: timing after reconnect"
|
||||
|
||||
# Full cleanup
|
||||
disconnect_pin test_net_a test_buf_a/A
|
||||
|
|
@ -74,10 +67,8 @@ delete_instance test_buf_b
|
|||
delete_net test_net_a
|
||||
delete_net test_net_b
|
||||
delete_net test_net_c
|
||||
puts "PASS: full cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after full cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Replace cell multiple times
|
||||
|
|
@ -88,31 +79,24 @@ puts "--- Test 3: replace_cell ---"
|
|||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1 -> BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X2
|
||||
report_checks
|
||||
puts "PASS: buf1 -> BUF_X2"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: buf1 restored"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X2
|
||||
report_checks
|
||||
puts "PASS: and1 -> AND2_X2"
|
||||
|
||||
replace_cell and1 NangateOpenCellLibrary/AND2_X1
|
||||
report_checks
|
||||
puts "PASS: and1 restored"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
puts "PASS: inv1 -> INV_X2"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
puts "PASS: inv1 restored"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Add and delete register instances
|
||||
|
|
@ -129,22 +113,19 @@ connect_pin reg_test_qnet test_reg/Q
|
|||
|
||||
# Connect clock to new register
|
||||
set clk_net_name "clk"
|
||||
catch {connect_pin $clk_net_name test_reg/CK} msg
|
||||
connect_pin $clk_net_name test_reg/CK
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with added register"
|
||||
|
||||
# Remove the register
|
||||
catch {disconnect_pin $clk_net_name test_reg/CK} msg
|
||||
disconnect_pin $clk_net_name test_reg/CK
|
||||
disconnect_pin reg_test_net test_reg/D
|
||||
disconnect_pin reg_test_qnet test_reg/Q
|
||||
delete_instance test_reg
|
||||
delete_net reg_test_net
|
||||
delete_net reg_test_qnet
|
||||
puts "PASS: register removed"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after register removal"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Rapid connect/disconnect on same pin
|
||||
|
|
@ -175,10 +156,8 @@ puts "cycle 3 done"
|
|||
|
||||
delete_instance tmp_buf
|
||||
delete_net tmp_net
|
||||
puts "PASS: rapid cycles"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after rapid cycles"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Edge queries after all modifications
|
||||
|
|
@ -189,7 +168,6 @@ foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3 reg4} {
|
|||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: edge queries"
|
||||
|
||||
# Slew queries
|
||||
report_slews [get_ports d1]
|
||||
|
|
@ -198,21 +176,16 @@ report_slews [get_ports d3]
|
|||
report_slews [get_pins buf1/Z]
|
||||
report_slews [get_pins and1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
puts "PASS: slew queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin paths
|
||||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through pins ---"
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
puts "through nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
puts "through nor1: done"
|
||||
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
puts "through and1: done"
|
||||
|
||||
puts "PASS: through pin queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline report_checks
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -60,7 +59,6 @@ Path Type: min
|
|||
0.04 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -93,18 +91,12 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline max
|
||||
--- multiple paths ---
|
||||
No paths found.
|
||||
PASS: d1->q1
|
||||
No paths found.
|
||||
PASS: d1->q2
|
||||
No paths found.
|
||||
PASS: d2->q2
|
||||
No paths found.
|
||||
PASS: en->q1
|
||||
No paths found.
|
||||
PASS: en->q2
|
||||
--- through paths ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -139,7 +131,6 @@ Path Type: max
|
|||
|
||||
|
||||
through inv1/ZN: done
|
||||
PASS: through inv1/ZN
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -173,7 +164,6 @@ Path Type: max
|
|||
|
||||
|
||||
through and1/ZN: done
|
||||
PASS: through and1/ZN
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -207,7 +197,6 @@ Path Type: max
|
|||
|
||||
|
||||
through or1/ZN: done
|
||||
PASS: through or1/ZN
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -241,7 +230,6 @@ Path Type: max
|
|||
|
||||
|
||||
through buf3/Z: done
|
||||
PASS: through buf3/Z
|
||||
--- timing edges for multi-input cells ---
|
||||
and1 edges: 1
|
||||
or1 edges: 1
|
||||
|
|
@ -250,35 +238,28 @@ reg2 edges: 1
|
|||
and1 A1->ZN edges: 1
|
||||
and1 A2->ZN edges: 1
|
||||
or1 A1->ZN edges: 1
|
||||
PASS: timing edge queries
|
||||
--- report_edges ---
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.06:0.06
|
||||
PASS: report_edges buf1
|
||||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.01:0.01
|
||||
PASS: report_edges inv1
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.03:0.03
|
||||
PASS: report_edges from and1/A1
|
||||
A2 -> ZN combinational
|
||||
^ -> ^ 0.05:0.05
|
||||
v -> v 0.07:0.07
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.03:0.03
|
||||
PASS: report_edges to and1/ZN
|
||||
d1 -> buf1/A wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges from port d1
|
||||
reg2/Q -> q2 wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges to port q2
|
||||
--- set_case_analysis ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -312,9 +293,7 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks en=1
|
||||
No paths found.
|
||||
PASS: d1->q1 with en=1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -345,7 +324,6 @@ Path Type: max
|
|||
8.84 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks en=0
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -378,7 +356,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks after unset_case_analysis
|
||||
--- disable/enable timing multiple cells ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -410,7 +387,6 @@ Path Type: max
|
|||
8.84 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -441,7 +417,6 @@ Path Type: max
|
|||
8.84 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1+inv1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -472,7 +447,6 @@ Path Type: max
|
|||
8.84 slack (MET)
|
||||
|
||||
|
||||
PASS: enable buf1
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -505,7 +479,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: enable inv1
|
||||
buf1 A Z constraint
|
||||
buf3 A Z constraint
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -534,7 +507,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: disable lib cell arc
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -567,7 +539,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: unset lib cell arc
|
||||
--- report_check_types ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -601,7 +572,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: report_check_types max_delay
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -630,7 +600,6 @@ Path Type: min
|
|||
0.04 slack (MET)
|
||||
|
||||
|
||||
PASS: report_check_types min_delay
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -691,7 +660,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: report_check_types max+min
|
||||
--- report_slews ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
|
|
@ -704,7 +672,6 @@ and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
|||
or1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
reg1/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
reg2/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
PASS: report_slews various pins
|
||||
--- report_checks -unconstrained ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -738,7 +705,6 @@ Path Type: max
|
|||
8.82 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks unconstrained
|
||||
--- report_checks counts ---
|
||||
Warning: graph_incremental.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
|
|
@ -829,7 +795,6 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: group_count 3
|
||||
Warning: graph_incremental.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -925,7 +890,6 @@ Path Type: max
|
|||
8.84 slack (MET)
|
||||
|
||||
|
||||
PASS: endpoint_count 3
|
||||
Warning: graph_incremental.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: en (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -1073,5 +1037,3 @@ Path Type: min
|
|||
1.06 slack (MET)
|
||||
|
||||
|
||||
PASS: endpoint_count 5 min
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -23,52 +23,40 @@ set_input_transition 0.1 [get_ports {d1 d2 en}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- baseline report_checks ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multiple paths through design
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multiple paths ---"
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: d1->q2"
|
||||
|
||||
report_checks -from [get_ports d2] -to [get_ports q2]
|
||||
puts "PASS: d2->q2"
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q1]
|
||||
puts "PASS: en->q1"
|
||||
|
||||
report_checks -from [get_ports en] -to [get_ports q2]
|
||||
puts "PASS: en->q2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# -through paths (exercises graph traversal)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through paths ---"
|
||||
catch { report_checks -through [get_pins inv1/ZN] } msg
|
||||
report_checks -through [get_pins inv1/ZN]
|
||||
puts "through inv1/ZN: done"
|
||||
puts "PASS: through inv1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins and1/ZN] } msg
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
puts "through and1/ZN: done"
|
||||
puts "PASS: through and1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins or1/ZN] } msg
|
||||
report_checks -through [get_pins or1/ZN]
|
||||
puts "through or1/ZN: done"
|
||||
puts "PASS: through or1/ZN"
|
||||
|
||||
catch { report_checks -through [get_pins buf3/Z] } msg
|
||||
report_checks -through [get_pins buf3/Z]
|
||||
puts "through buf3/Z: done"
|
||||
puts "PASS: through buf3/Z"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Timing edge queries for multi-input cells
|
||||
|
|
@ -96,29 +84,21 @@ puts "and1 A2->ZN edges: [llength $edges_ft2]"
|
|||
set edges_ft3 [get_timing_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]]
|
||||
puts "or1 A1->ZN edges: [llength $edges_ft3]"
|
||||
|
||||
puts "PASS: timing edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_edges for various pin combinations
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: report_edges buf1"
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: report_edges inv1"
|
||||
|
||||
report_edges -from [get_pins and1/A1]
|
||||
puts "PASS: report_edges from and1/A1"
|
||||
|
||||
report_edges -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges to and1/ZN"
|
||||
|
||||
report_edges -from [get_ports d1]
|
||||
puts "PASS: report_edges from port d1"
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
puts "PASS: report_edges to port q2"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Constant propagation via set_case_analysis
|
||||
|
|
@ -126,20 +106,16 @@ puts "PASS: report_edges to port q2"
|
|||
puts "--- set_case_analysis ---"
|
||||
set_case_analysis 1 [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks en=1"
|
||||
|
||||
report_checks -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: d1->q1 with en=1"
|
||||
|
||||
# Change constant value
|
||||
set_case_analysis 0 [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks en=0"
|
||||
|
||||
# Remove case analysis
|
||||
unset_case_analysis [get_ports en]
|
||||
report_checks
|
||||
puts "PASS: report_checks after unset_case_analysis"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing with multiple cells
|
||||
|
|
@ -147,43 +123,34 @@ puts "PASS: report_checks after unset_case_analysis"
|
|||
puts "--- disable/enable timing multiple cells ---"
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: enable buf1"
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: enable inv1"
|
||||
|
||||
# Disable specific lib cell arc
|
||||
set_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: disable lib cell arc"
|
||||
|
||||
unset_disable_timing -from A -to Z [get_lib_cells NangateOpenCellLibrary/BUF_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: unset lib cell arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: report_check_types max_delay"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: report_check_types min_delay"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: report_check_types max+min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for various pins
|
||||
|
|
@ -200,26 +167,19 @@ report_slews [get_pins and1/ZN]
|
|||
report_slews [get_pins or1/ZN]
|
||||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
puts "PASS: report_slews various pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with -unconstrained
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks -unconstrained ---"
|
||||
report_checks -unconstrained
|
||||
puts "PASS: report_checks unconstrained"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with group_count and endpoint_count
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks counts ---"
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -endpoint_count 3
|
||||
puts "PASS: endpoint_count 3"
|
||||
|
||||
report_checks -endpoint_count 5 -path_delay min
|
||||
puts "PASS: endpoint_count 5 min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,2 +1 @@
|
|||
No paths found.
|
||||
PASS: graph created and timing reported
|
||||
|
|
|
|||
|
|
@ -8,4 +8,3 @@ create_clock -name clk -period 10 [get_ports clk]
|
|||
|
||||
# report_checks exercises the graph
|
||||
report_checks -from [get_ports d] -to [get_ports q]
|
||||
puts "PASS: graph created and timing reported"
|
||||
|
|
|
|||
|
|
@ -58,7 +58,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast baseline
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -118,7 +117,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow baseline
|
||||
Startpoint: d3 (input port clocked by clk1)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -178,7 +176,6 @@ Corner: fast
|
|||
0.05 slack (MET)
|
||||
|
||||
|
||||
PASS: fast min
|
||||
Startpoint: d3 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -238,7 +235,6 @@ Corner: slow
|
|||
0.23 slack (MET)
|
||||
|
||||
|
||||
PASS: slow min
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -298,7 +294,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast max
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -358,20 +353,13 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow max
|
||||
--- multi-corner per-path ---
|
||||
No paths found.
|
||||
PASS: fast d1->q1
|
||||
No paths found.
|
||||
PASS: slow d1->q1
|
||||
No paths found.
|
||||
PASS: fast d3->q1
|
||||
No paths found.
|
||||
PASS: slow d3->q1
|
||||
No paths found.
|
||||
PASS: fast d1->q2 (cross-clock)
|
||||
No paths found.
|
||||
PASS: slow d1->q2 (cross-clock)
|
||||
--- multi-corner report_dcalc ---
|
||||
Library: NangateOpenCellLibrary_fast
|
||||
Cell: BUF_X1
|
||||
|
|
@ -989,9 +977,6 @@ Driver waveform slew = 0.02
|
|||
slow reg3 CK->Q: done
|
||||
--- network modification and graph update ---
|
||||
Warning: graph_modify.tcl line 1, library 'NangateOpenCellLibrary' not found.
|
||||
PASS: make_instance added_buf
|
||||
PASS: make_net added_net
|
||||
PASS: connect added_buf/A
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1051,7 +1036,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast after add
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1111,9 +1095,7 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow after add
|
||||
Warning: graph_modify.tcl line 1, pin added_buf/A not found.
|
||||
PASS: cleanup added instance
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1173,7 +1155,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast after delete
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1233,7 +1214,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow after delete
|
||||
--- replace_cell ---
|
||||
Warning: graph_modify.tcl line 1, library 'NangateOpenCellLibrary' not found.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
|
|
@ -1295,7 +1275,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast after buf1->BUF_X4
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1355,7 +1334,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow after buf1->BUF_X4
|
||||
Warning: graph_modify.tcl line 1, library 'NangateOpenCellLibrary' not found.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1416,7 +1394,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: replaced back
|
||||
--- load changes multi-corner ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1536,7 +1513,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: q1 load 0.01
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1655,7 +1631,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: q2 load 0.05
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1774,7 +1749,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: q3 load 0.1
|
||||
--- disable timing multi-corner ---
|
||||
Startpoint: d3 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1894,7 +1868,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: disable and1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2013,7 +1986,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: disable and1+or1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2132,7 +2104,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: enable all
|
||||
--- case analysis multi-corner ---
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -2252,7 +2223,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: d1=1 multi-corner
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2371,7 +2341,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: d1 unset multi-corner
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2490,7 +2459,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: d4=0 multi-corner
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2550,7 +2518,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: d4 unset
|
||||
--- report_slews multi-corner ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
q1 ^ 0.00:0.02 v 0.00:0.01
|
||||
|
|
@ -2558,7 +2525,6 @@ q2 ^ 0.00:0.01 v 0.00:0.01
|
|||
nand1/ZN ^ 0.01:0.07 v 0.01:0.03
|
||||
nor1/ZN ^ 0.01:0.09 v 0.01:0.02
|
||||
reg3/Q ^ 0.00:0.02 v 0.00:0.02
|
||||
PASS: slews multi-corner
|
||||
--- report_edges multi-corner ---
|
||||
A1 -> ZN combinational
|
||||
^ -> v 0.02:0.02:0.05:0.05
|
||||
|
|
@ -2584,7 +2550,6 @@ A1 -> ZN combinational
|
|||
A2 -> ZN combinational
|
||||
^ -> ^ 0.02:0.02:0.09:0.09
|
||||
v -> v 0.02:0.02:0.16:0.16
|
||||
PASS: report_edges multi-corner
|
||||
--- fields per corner ---
|
||||
Warning: graph_modify.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
|
|
@ -2650,7 +2615,6 @@ Fanout Cap Slew Delay Time Description
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast with fields
|
||||
Warning: graph_modify.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -2715,7 +2679,6 @@ Fanout Cap Slew Delay Time Description
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow with fields
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2775,7 +2738,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast full_clock
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2835,7 +2797,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow full_clock
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2895,7 +2856,6 @@ Corner: fast
|
|||
4.93 slack (MET)
|
||||
|
||||
|
||||
PASS: fast unconstrained
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2955,7 +2915,6 @@ Corner: slow
|
|||
4.61 slack (MET)
|
||||
|
||||
|
||||
PASS: slow unconstrained
|
||||
Warning: graph_modify.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -3108,7 +3067,6 @@ Corner: fast
|
|||
13.94 slack (MET)
|
||||
|
||||
|
||||
PASS: fast group_count 3
|
||||
Warning: graph_modify.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -3377,5 +3335,3 @@ Corner: slow
|
|||
13.69 slack (MET)
|
||||
|
||||
|
||||
PASS: slow endpoint_count 5
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -31,86 +31,74 @@ set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner baseline ---"
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast baseline"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow baseline"
|
||||
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: fast min"
|
||||
|
||||
report_checks -corner slow -path_delay min
|
||||
puts "PASS: slow min"
|
||||
|
||||
report_checks -corner fast -path_delay max
|
||||
puts "PASS: fast max"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: slow max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner per-path (exercises delay comparison across corners)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner per-path ---"
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: fast d1->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q1]
|
||||
puts "PASS: slow d1->q1"
|
||||
|
||||
report_checks -corner fast -from [get_ports d3] -to [get_ports q1]
|
||||
puts "PASS: fast d3->q1"
|
||||
|
||||
report_checks -corner slow -from [get_ports d3] -to [get_ports q1]
|
||||
puts "PASS: slow d3->q1"
|
||||
|
||||
# Cross-clock domain paths
|
||||
report_checks -corner fast -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: fast d1->q2 (cross-clock)"
|
||||
|
||||
report_checks -corner slow -from [get_ports d1] -to [get_ports q2]
|
||||
puts "PASS: slow d1->q2 (cross-clock)"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Multi-corner report_dcalc
|
||||
# Exercises: delay value comparison across corners
|
||||
#---------------------------------------------------------------
|
||||
puts "--- multi-corner report_dcalc ---"
|
||||
catch {report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -corner fast -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "fast buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]} msg
|
||||
report_dcalc -corner slow -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "slow buf1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins nand1/A1] -to [get_pins nand1/ZN]} msg
|
||||
report_dcalc -corner fast -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "fast nand1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins nand1/A1] -to [get_pins nand1/ZN]} msg
|
||||
report_dcalc -corner slow -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "slow nand1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins nor1/A1] -to [get_pins nor1/ZN]} msg
|
||||
report_dcalc -corner fast -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "fast nor1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins nor1/A1] -to [get_pins nor1/ZN]} msg
|
||||
report_dcalc -corner slow -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "slow nor1 dcalc: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "fast reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max} msg
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/Q] -max
|
||||
puts "slow reg1 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max} msg
|
||||
report_dcalc -corner fast -from [get_pins reg1/CK] -to [get_pins reg1/D] -max
|
||||
puts "fast reg1 setup: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min} msg
|
||||
report_dcalc -corner slow -from [get_pins reg1/CK] -to [get_pins reg1/D] -min
|
||||
puts "slow reg1 hold: done"
|
||||
|
||||
# Cross-clock domain DFF
|
||||
catch {report_dcalc -corner fast -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max} msg
|
||||
report_dcalc -corner fast -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max
|
||||
puts "fast reg3 CK->Q: done"
|
||||
|
||||
catch {report_dcalc -corner slow -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max} msg
|
||||
report_dcalc -corner slow -from [get_pins reg3/CK] -to [get_pins reg3/Q] -max
|
||||
puts "slow reg3 CK->Q: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
|
|
@ -119,33 +107,25 @@ puts "slow reg3 CK->Q: done"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- network modification and graph update ---"
|
||||
set new_buf [make_instance added_buf NangateOpenCellLibrary/BUF_X1]
|
||||
puts "PASS: make_instance added_buf"
|
||||
|
||||
set new_net [make_net added_net]
|
||||
puts "PASS: make_net added_net"
|
||||
|
||||
connect_pin added_net added_buf/A
|
||||
puts "PASS: connect added_buf/A"
|
||||
|
||||
# Report checks after adding (graph updated incrementally)
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after add"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after add"
|
||||
|
||||
# Disconnect and delete
|
||||
disconnect_pin added_net added_buf/A
|
||||
delete_instance added_buf
|
||||
delete_net added_net
|
||||
puts "PASS: cleanup added instance"
|
||||
|
||||
# Report after deletion
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after delete"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after delete"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and check timing
|
||||
|
|
@ -154,15 +134,12 @@ puts "PASS: slow after delete"
|
|||
puts "--- replace_cell ---"
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks -corner fast
|
||||
puts "PASS: fast after buf1->BUF_X4"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: slow after buf1->BUF_X4"
|
||||
|
||||
# Replace back
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: replaced back"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes with multi-corner
|
||||
|
|
@ -172,17 +149,14 @@ puts "--- load changes multi-corner ---"
|
|||
set_load 0.01 [get_ports q1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q1 load 0.01"
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q2 load 0.05"
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: q3 load 0.1"
|
||||
|
||||
# Reset loads
|
||||
set_load 0 [get_ports q1]
|
||||
|
|
@ -197,18 +171,15 @@ puts "--- disable timing multi-corner ---"
|
|||
set_disable_timing [get_cells and1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable and1"
|
||||
|
||||
set_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: disable and1+or1"
|
||||
|
||||
unset_disable_timing [get_cells and1]
|
||||
unset_disable_timing [get_cells or1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: enable all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis with multi-corner
|
||||
|
|
@ -217,21 +188,17 @@ puts "--- case analysis multi-corner ---"
|
|||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d1=1 multi-corner"
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d1 unset multi-corner"
|
||||
|
||||
set_case_analysis 0 [get_ports d4]
|
||||
report_checks -corner fast
|
||||
report_checks -corner slow
|
||||
puts "PASS: d4=0 multi-corner"
|
||||
|
||||
unset_case_analysis [get_ports d4]
|
||||
report_checks
|
||||
puts "PASS: d4 unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews per corner
|
||||
|
|
@ -243,7 +210,6 @@ report_slews [get_ports q2]
|
|||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
report_slews [get_pins reg3/Q]
|
||||
puts "PASS: slews multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report edges (exercises EdgeLess comparator)
|
||||
|
|
@ -257,34 +223,23 @@ report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
|||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
puts "PASS: report_edges multi-corner"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with fields per corner
|
||||
#---------------------------------------------------------------
|
||||
puts "--- fields per corner ---"
|
||||
report_checks -corner fast -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: fast with fields"
|
||||
|
||||
report_checks -corner slow -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: slow with fields"
|
||||
|
||||
report_checks -corner fast -format full_clock
|
||||
puts "PASS: fast full_clock"
|
||||
|
||||
report_checks -corner slow -format full_clock
|
||||
puts "PASS: slow full_clock"
|
||||
|
||||
report_checks -corner fast -unconstrained
|
||||
puts "PASS: fast unconstrained"
|
||||
|
||||
report_checks -corner slow -unconstrained
|
||||
puts "PASS: slow unconstrained"
|
||||
|
||||
report_checks -corner fast -group_count 3
|
||||
puts "PASS: fast group_count 3"
|
||||
|
||||
report_checks -corner slow -endpoint_count 5
|
||||
puts "PASS: slow endpoint_count 5"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline report_checks
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -114,7 +113,6 @@ Path Type: min
|
|||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -172,7 +170,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline max
|
||||
--- all path combinations ---
|
||||
No paths found.
|
||||
d1->q1: done
|
||||
|
|
@ -531,59 +528,45 @@ reg3 CK->Q: 1
|
|||
A -> Z combinational
|
||||
^ -> ^ 0.04:0.04
|
||||
v -> v 0.06:0.06
|
||||
PASS: report_edges buf1
|
||||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.04:0.04
|
||||
PASS: report_edges inv1
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.03:0.03
|
||||
PASS: report_edges and1 A1
|
||||
A2 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.03:0.03
|
||||
PASS: report_edges and1 A2
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.05:0.05
|
||||
PASS: report_edges or1 A1
|
||||
A1 -> ZN combinational
|
||||
^ -> v 0.02:0.02
|
||||
v -> ^ 0.03:0.03
|
||||
PASS: report_edges nand1 A1
|
||||
A1 -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.03:0.03
|
||||
PASS: report_edges nor1 A1
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: report_edges reg1 CK->Q
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: report_edges reg3 CK->Q
|
||||
d1 -> buf1/A wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges from d1
|
||||
d3 -> inv1/A wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges from d3
|
||||
reg2/Q -> q1 wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges to q1
|
||||
buf3/Z -> q2 wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges to q2
|
||||
buf4/Z -> q3 wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: report_edges to q3
|
||||
--- disable/enable timing ---
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -642,7 +625,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -700,7 +682,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1+inv1
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: q1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -754,7 +735,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1+inv1+nand1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -812,7 +792,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: enable buf1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -870,7 +849,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: enable inv1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -928,7 +906,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: enable nand1
|
||||
and1 A1 ZN constraint
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -987,7 +964,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable and1 A1->ZN arc
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1045,7 +1021,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: enable and1 A1->ZN arc
|
||||
Startpoint: d3 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1103,7 +1078,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable nand1 A1 arc
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1161,7 +1135,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: enable nand1 A1 arc
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1219,7 +1192,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable nor1 A1 arc
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1277,7 +1249,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: enable nor1 A1 arc
|
||||
--- case analysis ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1336,7 +1307,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: rst=1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1394,7 +1364,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: rst=0
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1452,7 +1421,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: rst unset
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1510,7 +1478,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: d3=1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1568,7 +1535,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: d3 unset
|
||||
--- report_slews ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
|
|
@ -1588,7 +1554,6 @@ or2/ZN ^ 0.01:0.01 v 0.01:0.01
|
|||
reg1/Q ^ 0.01:0.01 v 0.01:0.01
|
||||
reg2/Q ^ 0.01:0.01 v 0.00:0.00
|
||||
reg3/Q ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: report_slews all pins
|
||||
--- report_check_types ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1647,7 +1612,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: check_types max
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1705,7 +1669,6 @@ Path Type: min
|
|||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: check_types min
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1820,7 +1783,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: check_types max+min
|
||||
--- report_checks options ---
|
||||
Warning: graph_operations.tcl line 1, unknown field nets.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
|
|
@ -1884,7 +1846,6 @@ Fanout Cap Slew Delay Time Description
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: all fields
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1942,7 +1903,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: full_clock
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -2000,7 +1960,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: unconstrained
|
||||
Warning: graph_operations.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -2148,7 +2107,6 @@ Path Type: max
|
|||
13.90 slack (MET)
|
||||
|
||||
|
||||
PASS: group_count 3
|
||||
Warning: graph_operations.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -2408,7 +2366,6 @@ Path Type: max
|
|||
13.90 slack (MET)
|
||||
|
||||
|
||||
PASS: endpoint_count 5
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
|
||||
Path Group: clk2
|
||||
|
|
@ -2466,7 +2423,6 @@ Path Type: max
|
|||
7.87 slack (MET)
|
||||
|
||||
|
||||
PASS: sort_by_slack
|
||||
Warning: graph_operations.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
|
|
@ -2635,5 +2591,3 @@ Path Type: min
|
|||
1.10 slack (MET)
|
||||
|
||||
|
||||
PASS: min endpoint_count 3
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -27,13 +27,10 @@ set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline report_checks"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# All path combinations (exercises vertex/edge traversal thoroughly)
|
||||
|
|
@ -41,9 +38,7 @@ puts "PASS: baseline max"
|
|||
puts "--- all path combinations ---"
|
||||
foreach from_port {d1 d2 d3 d4} {
|
||||
foreach to_port {q1 q2 q3} {
|
||||
catch {
|
||||
report_checks -from [get_ports $from_port] -to [get_ports $to_port]
|
||||
} msg
|
||||
report_checks -from [get_ports $from_port] -to [get_ports $to_port]
|
||||
puts "${from_port}->${to_port}: done"
|
||||
}
|
||||
}
|
||||
|
|
@ -53,23 +48,23 @@ foreach from_port {d1 d2 d3 d4} {
|
|||
# Exercises: graph traversal through reconvergent fan-out
|
||||
#---------------------------------------------------------------
|
||||
puts "--- through reconvergent paths ---"
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
puts "through nand1/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
puts "through nor1/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins and2/ZN]} msg
|
||||
report_checks -through [get_pins and2/ZN]
|
||||
puts "through and2/ZN: done"
|
||||
|
||||
catch {report_checks -through [get_pins or2/ZN]} msg
|
||||
report_checks -through [get_pins or2/ZN]
|
||||
puts "through or2/ZN: done"
|
||||
|
||||
# Through multiple intermediate points
|
||||
catch {report_checks -through [get_pins and1/ZN] -through [get_pins nand1/ZN]} msg
|
||||
report_checks -through [get_pins and1/ZN] -through [get_pins nand1/ZN]
|
||||
puts "through and1->nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins or1/ZN] -through [get_pins nand1/ZN]} msg
|
||||
report_checks -through [get_pins or1/ZN] -through [get_pins nand1/ZN]
|
||||
puts "through or1->nand1: done"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
|
|
@ -77,10 +72,8 @@ puts "through or1->nand1: done"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- timing edges all cells ---"
|
||||
foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 reg3 buf3 buf4} {
|
||||
catch {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
} msg
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
|
||||
# From/to specific pins
|
||||
|
|
@ -112,48 +105,34 @@ puts "reg3 CK->Q: [llength $edges_reg3_ck_q]"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- report_edges ---"
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: report_edges buf1"
|
||||
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: report_edges inv1"
|
||||
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges and1 A1"
|
||||
|
||||
report_edges -from [get_pins and1/A2] -to [get_pins and1/ZN]
|
||||
puts "PASS: report_edges and1 A2"
|
||||
|
||||
report_edges -from [get_pins or1/A1] -to [get_pins or1/ZN]
|
||||
puts "PASS: report_edges or1 A1"
|
||||
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
puts "PASS: report_edges nand1 A1"
|
||||
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
puts "PASS: report_edges nor1 A1"
|
||||
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
puts "PASS: report_edges reg1 CK->Q"
|
||||
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
puts "PASS: report_edges reg3 CK->Q"
|
||||
|
||||
# From only
|
||||
report_edges -from [get_ports d1]
|
||||
puts "PASS: report_edges from d1"
|
||||
|
||||
report_edges -from [get_ports d3]
|
||||
puts "PASS: report_edges from d3"
|
||||
|
||||
# To only
|
||||
report_edges -to [get_ports q1]
|
||||
puts "PASS: report_edges to q1"
|
||||
|
||||
report_edges -to [get_ports q2]
|
||||
puts "PASS: report_edges to q2"
|
||||
|
||||
report_edges -to [get_ports q3]
|
||||
puts "PASS: report_edges to q3"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on various cells
|
||||
|
|
@ -164,56 +143,44 @@ puts "--- disable/enable timing ---"
|
|||
# Disable individual cells
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1"
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1+inv1+nand1"
|
||||
|
||||
# Enable back one by one
|
||||
unset_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: enable buf1"
|
||||
|
||||
unset_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: enable inv1"
|
||||
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: enable nand1"
|
||||
|
||||
# Disable specific arcs on lib cells
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: disable and1 A1->ZN arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/AND2_X1]
|
||||
report_disabled_edges
|
||||
report_checks
|
||||
puts "PASS: enable and1 A1->ZN arc"
|
||||
|
||||
# Disable/enable on NOR and NAND
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
puts "PASS: disable nand1 A1 arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NAND2_X1]
|
||||
report_checks
|
||||
puts "PASS: enable nand1 A1 arc"
|
||||
|
||||
set_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
puts "PASS: disable nor1 A1 arc"
|
||||
|
||||
unset_disable_timing -from A1 -to ZN [get_lib_cells NangateOpenCellLibrary/NOR2_X1]
|
||||
report_checks
|
||||
puts "PASS: enable nor1 A1 arc"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis / constant propagation
|
||||
|
|
@ -222,24 +189,19 @@ puts "PASS: enable nor1 A1 arc"
|
|||
puts "--- case analysis ---"
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=1"
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=0"
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst unset"
|
||||
|
||||
# Case analysis on data inputs
|
||||
set_case_analysis 1 [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3=1"
|
||||
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3 unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Report slews for pins in multi-clock design
|
||||
|
|
@ -264,44 +226,31 @@ report_slews [get_pins or2/ZN]
|
|||
report_slews [get_pins reg1/Q]
|
||||
report_slews [get_pins reg2/Q]
|
||||
report_slews [get_pins reg3/Q]
|
||||
puts "PASS: report_slews all pins"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types (exercises check edge categorization)
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
report_check_types -max_delay -min_delay -verbose
|
||||
puts "PASS: check_types max+min"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_checks with various options
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_checks options ---"
|
||||
report_checks -fields {slew cap input_pins nets fanout}
|
||||
puts "PASS: all fields"
|
||||
|
||||
report_checks -format full_clock
|
||||
puts "PASS: full_clock"
|
||||
|
||||
report_checks -unconstrained
|
||||
puts "PASS: unconstrained"
|
||||
|
||||
report_checks -group_count 3
|
||||
puts "PASS: group_count 3"
|
||||
|
||||
report_checks -endpoint_count 5
|
||||
puts "PASS: endpoint_count 5"
|
||||
|
||||
report_checks -sort_by_slack
|
||||
puts "PASS: sort_by_slack"
|
||||
|
||||
report_checks -endpoint_count 3 -path_delay min
|
||||
puts "PASS: min endpoint_count 3"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -38,7 +38,6 @@ reg1/Q -> D wire
|
|||
v -> v 0.00:0.00
|
||||
--- report_disabled_edges (baseline) ---
|
||||
--- set_disable_timing on instance ---
|
||||
PASS: set_disable_timing on reg1
|
||||
--- report_disabled_edges after disable ---
|
||||
reg1 CK Q constraint
|
||||
reg1 CK QN constraint
|
||||
|
|
@ -70,15 +69,12 @@ Path Type: max
|
|||
|
||||
|
||||
--- unset_disable_timing on instance ---
|
||||
PASS: unset_disable_timing on reg1
|
||||
--- report_disabled_edges after unset ---
|
||||
--- set_disable_timing with -from/-to on lib cell ---
|
||||
PASS: set_disable_timing -from CK -to Q
|
||||
--- report_disabled_edges after lib cell disable ---
|
||||
reg1 CK Q constraint
|
||||
reg2 CK Q constraint
|
||||
--- unset_disable_timing lib cell ---
|
||||
PASS: unset_disable_timing lib cell
|
||||
--- report_checks baseline ---
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -179,4 +175,3 @@ reg2 timing edges count: 1
|
|||
d ^ 0.00:0.00 v 0.00:0.00
|
||||
--- report_slews on q port ---
|
||||
q ^ 0.01:0.01 v 0.00:0.00
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@ report_disabled_edges
|
|||
|
||||
puts "--- set_disable_timing on instance ---"
|
||||
set_disable_timing [get_cells reg1]
|
||||
puts "PASS: set_disable_timing on reg1"
|
||||
|
||||
puts "--- report_disabled_edges after disable ---"
|
||||
report_disabled_edges
|
||||
|
|
@ -47,21 +46,18 @@ report_checks
|
|||
|
||||
puts "--- unset_disable_timing on instance ---"
|
||||
unset_disable_timing [get_cells reg1]
|
||||
puts "PASS: unset_disable_timing on reg1"
|
||||
|
||||
puts "--- report_disabled_edges after unset ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- set_disable_timing with -from/-to on lib cell ---"
|
||||
set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: set_disable_timing -from CK -to Q"
|
||||
|
||||
puts "--- report_disabled_edges after lib cell disable ---"
|
||||
report_disabled_edges
|
||||
|
||||
puts "--- unset_disable_timing lib cell ---"
|
||||
unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
|
||||
puts "PASS: unset_disable_timing lib cell"
|
||||
|
||||
puts "--- report_checks baseline ---"
|
||||
report_checks
|
||||
|
|
@ -90,5 +86,3 @@ report_slews [get_ports d]
|
|||
|
||||
puts "--- report_slews on q port ---"
|
||||
report_slews [get_ports q]
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline timing
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
inv1 edges: 1
|
||||
|
|
@ -37,9 +36,7 @@ and1 edges: 1
|
|||
or1 edges: 1
|
||||
nand1 edges: 1
|
||||
nor1 edges: 1
|
||||
PASS: baseline edge queries
|
||||
--- Test 2: chain add/delete ---
|
||||
PASS: 4-stage chain created
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -70,12 +67,10 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with chain
|
||||
chain_buf0 edges: 1
|
||||
chain_buf1 edges: 1
|
||||
chain_buf2 edges: 1
|
||||
chain_buf3 edges: 1
|
||||
PASS: chain deleted
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -106,9 +101,7 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after chain delete
|
||||
--- Test 3: fan-out/fan-in ---
|
||||
PASS: fanout-3 net created
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -139,7 +132,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with fanout
|
||||
fo_drv edges: 1
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -171,7 +163,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: fanout-2 timing
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -202,8 +193,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: fanout-1 timing
|
||||
PASS: fanout cleanup
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -234,7 +223,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after fanout cleanup
|
||||
--- Test 4: cell replacement cycle ---
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -446,7 +434,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 replacement cycle
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -597,9 +584,7 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: and1 replacement cycle
|
||||
--- Test 5: register add/delete ---
|
||||
PASS: 3 registers added
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -630,8 +615,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing with added registers
|
||||
PASS: registers deleted
|
||||
Startpoint: d2 (input port clocked by clk)
|
||||
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -662,13 +645,11 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after register deletion
|
||||
--- Test 6: slew and edge reports ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
d3 ^ 0.10:0.10 v 0.10:0.10
|
||||
clk ^ 0.10:0.10 v 0.10:0.10
|
||||
PASS: port slews
|
||||
buf1/A ^ 0.10:0.10 v 0.10:0.10
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
and1/A1 ^ 0.01:0.01 v 0.01:0.01
|
||||
|
|
@ -677,7 +658,6 @@ inv1/A ^ 0.10:0.10 v 0.10:0.10
|
|||
inv1/ZN ^ 0.02:0.02 v 0.02:0.02
|
||||
nand1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
nor1/ZN ^ 0.01:0.01 v 0.01:0.01
|
||||
PASS: pin slews
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.06:0.06
|
||||
|
|
@ -687,7 +667,6 @@ A1 -> ZN combinational
|
|||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.04:0.04
|
||||
PASS: edge reports
|
||||
--- Test 7: through-pin queries ---
|
||||
Startpoint: d1 (input port clocked by clk)
|
||||
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
||||
|
|
@ -869,7 +848,6 @@ Path Type: max
|
|||
8.85 slack (MET)
|
||||
|
||||
|
||||
PASS: through-pin queries
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: q1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -974,5 +952,3 @@ Path Type: max
|
|||
8.92 slack (MET)
|
||||
|
||||
|
||||
PASS: endpoint queries
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
# makeEdge, deleteEdge, edge arc queries, bidirectional pin handling,
|
||||
# hasFaninOne, vertex iteration, edge linking.
|
||||
# Targets: Graph.cc uncovered:
|
||||
# deleteVertex (lines 476-504): edge cleanup during vertex deletion
|
||||
# deleteVertex: edge cleanup during vertex deletion
|
||||
# deleteInEdge / deleteOutEdge: linked list manipulation for edges
|
||||
# hasFaninOne: single fanin check
|
||||
# pinDrvrVertex / pinLoadVertex: bidirect driver vertex lookup
|
||||
|
|
@ -29,14 +29,12 @@ set_input_transition 0.1 [get_ports {d1 d2 d3 rst clk}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 1: baseline edge count ---"
|
||||
report_checks
|
||||
puts "PASS: baseline timing"
|
||||
|
||||
# Query edges for each cell
|
||||
foreach cell_name {buf1 buf2 inv1 and1 or1 nand1 nor1} {
|
||||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: baseline edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 2: Add chain of buffers, verify edges, then delete one by one
|
||||
|
|
@ -60,10 +58,8 @@ for {set i 0} {$i < 4} {incr i} {
|
|||
set j [expr {$i + 1}]
|
||||
connect_pin "chain_n$j" "chain_buf$i/Z"
|
||||
}
|
||||
puts "PASS: 4-stage chain created"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with chain"
|
||||
|
||||
# Query chain edges
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
|
|
@ -81,10 +77,8 @@ for {set i 3} {$i >= 0} {incr i -1} {
|
|||
for {set i 0} {$i <= 4} {incr i} {
|
||||
delete_net "chain_n$i"
|
||||
}
|
||||
puts "PASS: chain deleted"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after chain delete"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 3: Multiple fan-out and fan-in scenarios
|
||||
|
|
@ -105,10 +99,7 @@ connect_pin fanout_net fo_load1/A
|
|||
connect_pin fanout_net fo_load2/A
|
||||
connect_pin fanout_net fo_load3/A
|
||||
|
||||
puts "PASS: fanout-3 net created"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with fanout"
|
||||
|
||||
# Query edge count on fanout driver
|
||||
set drv_edges [get_timing_edges -of_objects [get_cells fo_drv]]
|
||||
|
|
@ -117,11 +108,9 @@ puts "fo_drv edges: [llength $drv_edges]"
|
|||
# Disconnect loads one by one
|
||||
disconnect_pin fanout_net fo_load3/A
|
||||
report_checks
|
||||
puts "PASS: fanout-2 timing"
|
||||
|
||||
disconnect_pin fanout_net fo_load2/A
|
||||
report_checks
|
||||
puts "PASS: fanout-1 timing"
|
||||
|
||||
# Cleanup
|
||||
disconnect_pin fanout_net fo_load1/A
|
||||
|
|
@ -133,10 +122,8 @@ delete_instance fo_load3
|
|||
delete_instance fo_drv
|
||||
delete_net fanout_net
|
||||
delete_net fo_in
|
||||
puts "PASS: fanout cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after fanout cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 4: Replace cell multiple times and verify edge rebuild
|
||||
|
|
@ -149,14 +136,12 @@ foreach lib_cell {BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X4 BUF_X2 BUF_X1} {
|
|||
replace_cell buf1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks -path_delay max
|
||||
}
|
||||
puts "PASS: buf1 replacement cycle"
|
||||
|
||||
# Replace AND gate
|
||||
foreach lib_cell {AND2_X1 AND2_X2 AND2_X4 AND2_X2 AND2_X1} {
|
||||
replace_cell and1 "NangateOpenCellLibrary/$lib_cell"
|
||||
report_checks
|
||||
}
|
||||
puts "PASS: and1 replacement cycle"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 5: Register add/delete to exercise reg_clk_vertices
|
||||
|
|
@ -171,26 +156,22 @@ for {set i 0} {$i < 3} {incr i} {
|
|||
set ri [make_instance "test_reg$i" NangateOpenCellLibrary/DFF_X1]
|
||||
connect_pin "reg_d$i" "test_reg$i/D"
|
||||
connect_pin "reg_q$i" "test_reg$i/Q"
|
||||
catch {connect_pin clk "test_reg$i/CK"} msg
|
||||
connect_pin clk "test_reg$i/CK"
|
||||
}
|
||||
puts "PASS: 3 registers added"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing with added registers"
|
||||
|
||||
# Delete the registers
|
||||
for {set i 0} {$i < 3} {incr i} {
|
||||
catch {disconnect_pin clk "test_reg$i/CK"} msg
|
||||
disconnect_pin clk "test_reg$i/CK"
|
||||
disconnect_pin "reg_d$i" "test_reg$i/D"
|
||||
disconnect_pin "reg_q$i" "test_reg$i/Q"
|
||||
delete_instance "test_reg$i"
|
||||
delete_net "reg_d$i"
|
||||
delete_net "reg_q$i"
|
||||
}
|
||||
puts "PASS: registers deleted"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after register deletion"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 6: Slew and timing edge reports
|
||||
|
|
@ -202,7 +183,6 @@ report_slews [get_ports d1]
|
|||
report_slews [get_ports d2]
|
||||
report_slews [get_ports d3]
|
||||
report_slews [get_ports clk]
|
||||
puts "PASS: port slews"
|
||||
|
||||
report_slews [get_pins buf1/A]
|
||||
report_slews [get_pins buf1/Z]
|
||||
|
|
@ -212,13 +192,11 @@ report_slews [get_pins inv1/A]
|
|||
report_slews [get_pins inv1/ZN]
|
||||
report_slews [get_pins nand1/ZN]
|
||||
report_slews [get_pins nor1/ZN]
|
||||
puts "PASS: pin slews"
|
||||
|
||||
# Edge reports
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
report_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: edge reports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Test 7: Through-pin and endpoint queries
|
||||
|
|
@ -226,19 +204,15 @@ puts "PASS: edge reports"
|
|||
#---------------------------------------------------------------
|
||||
puts "--- Test 7: through-pin queries ---"
|
||||
|
||||
catch {report_checks -through [get_pins buf1/Z]} msg
|
||||
catch {report_checks -through [get_pins and1/ZN]} msg
|
||||
catch {report_checks -through [get_pins inv1/ZN]} msg
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
catch {report_checks -through [get_pins or1/ZN]} msg
|
||||
puts "PASS: through-pin queries"
|
||||
report_checks -through [get_pins buf1/Z]
|
||||
report_checks -through [get_pins and1/ZN]
|
||||
report_checks -through [get_pins inv1/ZN]
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
report_checks -through [get_pins or1/ZN]
|
||||
|
||||
# Endpoint
|
||||
catch {report_checks -to [get_ports q1]} msg
|
||||
catch {report_checks -to [get_ports q2]} msg
|
||||
catch {report_checks -to [get_ports q3]} msg
|
||||
catch {report_checks -to [get_ports q4]} msg
|
||||
puts "PASS: endpoint queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
report_checks -to [get_ports q1]
|
||||
report_checks -to [get_ports q2]
|
||||
report_checks -to [get_ports q3]
|
||||
report_checks -to [get_ports q4]
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -114,7 +113,6 @@ Path Type: min
|
|||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline min
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -172,7 +170,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: baseline max
|
||||
--- timing edges per cell ---
|
||||
buf1 edges: 1
|
||||
buf2 edges: 1
|
||||
|
|
@ -189,44 +186,37 @@ reg2 edges: 1
|
|||
reg3 edges: 1
|
||||
buf3 edges: 1
|
||||
buf4 edges: 1
|
||||
PASS: edge queries
|
||||
--- specific edge queries ---
|
||||
A -> Z combinational
|
||||
^ -> ^ 0.04:0.04
|
||||
v -> v 0.06:0.06
|
||||
PASS: buf1 edges
|
||||
A -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.04:0.04
|
||||
PASS: inv1 edges
|
||||
A1 -> ZN combinational
|
||||
^ -> v 0.02:0.02
|
||||
v -> ^ 0.03:0.03
|
||||
A2 -> ZN combinational
|
||||
^ -> v 0.02:0.02
|
||||
v -> ^ 0.03:0.03
|
||||
PASS: nand1 edges
|
||||
A1 -> ZN combinational
|
||||
^ -> v 0.01:0.01
|
||||
v -> ^ 0.03:0.03
|
||||
A2 -> ZN combinational
|
||||
^ -> v 0.02:0.02
|
||||
v -> ^ 0.04:0.04
|
||||
PASS: nor1 edges
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.03:0.03
|
||||
A2 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.03:0.03
|
||||
PASS: and2 edges
|
||||
A1 -> ZN combinational
|
||||
^ -> ^ 0.02:0.02
|
||||
v -> v 0.04:0.04
|
||||
A2 -> ZN combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.04:0.04
|
||||
PASS: or2 edges
|
||||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
|
|
@ -236,7 +226,6 @@ CK -> Q Reg Clk to Q
|
|||
CK -> Q Reg Clk to Q
|
||||
^ -> ^ 0.08:0.08
|
||||
^ -> v 0.08:0.08
|
||||
PASS: DFF edges
|
||||
d1 -> buf1/A wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
|
|
@ -249,7 +238,6 @@ d3 -> inv1/A wire
|
|||
d4 -> inv2/A wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: wire edges from ports
|
||||
reg2/Q -> q1 wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
|
|
@ -259,7 +247,6 @@ buf3/Z -> q2 wire
|
|||
buf4/Z -> q3 wire
|
||||
^ -> ^ 0.00:0.00
|
||||
v -> v 0.00:0.00
|
||||
PASS: wire edges to ports
|
||||
--- slew queries ---
|
||||
d1 ^ 0.10:0.10 v 0.10:0.10
|
||||
d2 ^ 0.10:0.10 v 0.10:0.10
|
||||
|
|
@ -267,11 +254,9 @@ d3 ^ 0.10:0.10 v 0.10:0.10
|
|||
d4 ^ 0.10:0.10 v 0.10:0.10
|
||||
clk1 ^ 0.10:0.10 v 0.10:0.10
|
||||
clk2 ^ 0.10:0.10 v 0.10:0.10
|
||||
PASS: input slews
|
||||
q1 ^ 0.01:0.01 v 0.00:0.00
|
||||
q2 ^ 0.00:0.00 v 0.00:0.00
|
||||
q3 ^ 0.00:0.00 v 0.00:0.00
|
||||
PASS: output slews
|
||||
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
buf2/Z ^ 0.01:0.01 v 0.01:0.01
|
||||
inv1/ZN ^ 0.02:0.02 v 0.02:0.02
|
||||
|
|
@ -287,9 +272,7 @@ reg2/Q ^ 0.01:0.01 v 0.00:0.00
|
|||
reg3/Q ^ 0.01:0.01 v 0.01:0.01
|
||||
buf3/Z ^ 0.00:0.00 v 0.00:0.00
|
||||
buf4/Z ^ 0.00:0.00 v 0.00:0.00
|
||||
PASS: internal slews
|
||||
--- network modification ---
|
||||
PASS: add instance
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -347,8 +330,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after add
|
||||
PASS: cleanup
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -406,7 +387,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: timing after cleanup
|
||||
--- replace cell ---
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -468,7 +448,6 @@ Path Type: max
|
|||
A -> Z combinational
|
||||
^ -> ^ 0.03:0.03
|
||||
v -> v 0.05:0.05
|
||||
PASS: buf1->BUF_X4
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -526,7 +505,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: buf1 restored
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -584,7 +562,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1->INV_X2
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -642,7 +619,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: inv1 restored
|
||||
--- disable/enable timing ---
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -701,7 +677,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable buf1
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -759,7 +734,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable inv1
|
||||
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Endpoint: q1 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -813,7 +787,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: disable nand1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -871,7 +844,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: re-enable all
|
||||
--- case analysis ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -930,7 +902,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: rst=1
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -988,7 +959,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: rst=0
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1046,7 +1016,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: rst unset
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1104,7 +1073,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: d1=1
|
||||
Startpoint: d2 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1162,7 +1130,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: d3=0
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1220,7 +1187,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: all unset
|
||||
--- load changes ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1279,7 +1245,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: q1 load=0.01
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1337,7 +1302,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: q2 load=0.05
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1395,7 +1359,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: q3 load=0.1
|
||||
--- through pin queries ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1523,7 +1486,6 @@ Path Type: max
|
|||
|
||||
|
||||
through or2: done
|
||||
PASS: through pin queries
|
||||
--- report_check_types ---
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: q3 (output port clocked by clk1)
|
||||
|
|
@ -1582,7 +1544,6 @@ Path Type: max
|
|||
4.88 slack (MET)
|
||||
|
||||
|
||||
PASS: check_types max
|
||||
Startpoint: d1 (input port clocked by clk1)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
|
||||
Path Group: clk1
|
||||
|
|
@ -1640,5 +1601,3 @@ Path Type: min
|
|||
0.08 slack (MET)
|
||||
|
||||
|
||||
PASS: check_types min
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -27,13 +27,10 @@ set_input_transition 0.1 [get_ports {d1 d2 d3 d4 rst clk1 clk2}]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- baseline timing ---"
|
||||
report_checks
|
||||
puts "PASS: baseline"
|
||||
|
||||
report_checks -path_delay min
|
||||
puts "PASS: baseline min"
|
||||
|
||||
report_checks -path_delay max
|
||||
puts "PASS: baseline max"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Query all timing edges: exercises edge iteration
|
||||
|
|
@ -43,7 +40,6 @@ foreach cell_name {buf1 buf2 inv1 inv2 and1 or1 nand1 nor1 and2 or2 reg1 reg2 re
|
|||
set edges [get_timing_edges -of_objects [get_cells $cell_name]]
|
||||
puts "$cell_name edges: [llength $edges]"
|
||||
}
|
||||
puts "PASS: edge queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Specific edge queries: from/to pins
|
||||
|
|
@ -53,50 +49,41 @@ puts "--- specific edge queries ---"
|
|||
|
||||
# BUF edges (rise/rise, fall/fall)
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1 edges"
|
||||
|
||||
# INV edges (rise/fall, fall/rise)
|
||||
report_edges -from [get_pins inv1/A] -to [get_pins inv1/ZN]
|
||||
puts "PASS: inv1 edges"
|
||||
|
||||
# NAND edges
|
||||
report_edges -from [get_pins nand1/A1] -to [get_pins nand1/ZN]
|
||||
report_edges -from [get_pins nand1/A2] -to [get_pins nand1/ZN]
|
||||
puts "PASS: nand1 edges"
|
||||
|
||||
# NOR edges
|
||||
report_edges -from [get_pins nor1/A1] -to [get_pins nor1/ZN]
|
||||
report_edges -from [get_pins nor1/A2] -to [get_pins nor1/ZN]
|
||||
puts "PASS: nor1 edges"
|
||||
|
||||
# AND2 edges
|
||||
report_edges -from [get_pins and2/A1] -to [get_pins and2/ZN]
|
||||
report_edges -from [get_pins and2/A2] -to [get_pins and2/ZN]
|
||||
puts "PASS: and2 edges"
|
||||
|
||||
# OR2 edges
|
||||
report_edges -from [get_pins or2/A1] -to [get_pins or2/ZN]
|
||||
report_edges -from [get_pins or2/A2] -to [get_pins or2/ZN]
|
||||
puts "PASS: or2 edges"
|
||||
|
||||
# DFF edges (CK->Q)
|
||||
report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
|
||||
report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
|
||||
report_edges -from [get_pins reg3/CK] -to [get_pins reg3/Q]
|
||||
puts "PASS: DFF edges"
|
||||
|
||||
# Wire edges (port to first gate)
|
||||
report_edges -from [get_ports d1]
|
||||
report_edges -from [get_ports d2]
|
||||
report_edges -from [get_ports d3]
|
||||
report_edges -from [get_ports d4]
|
||||
puts "PASS: wire edges from ports"
|
||||
|
||||
# Wire edges to output ports
|
||||
report_edges -to [get_ports q1]
|
||||
report_edges -to [get_ports q2]
|
||||
report_edges -to [get_ports q3]
|
||||
puts "PASS: wire edges to ports"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Slew queries: exercises slew getters in Graph.cc
|
||||
|
|
@ -110,13 +97,11 @@ report_slews [get_ports d3]
|
|||
report_slews [get_ports d4]
|
||||
report_slews [get_ports clk1]
|
||||
report_slews [get_ports clk2]
|
||||
puts "PASS: input slews"
|
||||
|
||||
# Output port slews
|
||||
report_slews [get_ports q1]
|
||||
report_slews [get_ports q2]
|
||||
report_slews [get_ports q3]
|
||||
puts "PASS: output slews"
|
||||
|
||||
# Internal pin slews
|
||||
report_slews [get_pins buf1/Z]
|
||||
|
|
@ -134,7 +119,6 @@ report_slews [get_pins reg2/Q]
|
|||
report_slews [get_pins reg3/Q]
|
||||
report_slews [get_pins buf3/Z]
|
||||
report_slews [get_pins buf4/Z]
|
||||
puts "PASS: internal slews"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Network modification: add/remove instances
|
||||
|
|
@ -148,11 +132,9 @@ set new_net [make_net extra_net]
|
|||
set new_net2 [make_net extra_net2]
|
||||
connect_pin extra_net extra_buf/A
|
||||
connect_pin extra_net2 extra_buf/Z
|
||||
puts "PASS: add instance"
|
||||
|
||||
# Timing after addition (exercises incremental graph update)
|
||||
report_checks
|
||||
puts "PASS: timing after add"
|
||||
|
||||
# Disconnect and remove
|
||||
disconnect_pin extra_net extra_buf/A
|
||||
|
|
@ -160,10 +142,8 @@ disconnect_pin extra_net2 extra_buf/Z
|
|||
delete_instance extra_buf
|
||||
delete_net extra_net
|
||||
delete_net extra_net2
|
||||
puts "PASS: cleanup"
|
||||
|
||||
report_checks
|
||||
puts "PASS: timing after cleanup"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Replace cell and verify edge update
|
||||
|
|
@ -173,19 +153,15 @@ puts "--- replace cell ---"
|
|||
replace_cell buf1 NangateOpenCellLibrary/BUF_X4
|
||||
report_checks
|
||||
report_edges -from [get_pins buf1/A] -to [get_pins buf1/Z]
|
||||
puts "PASS: buf1->BUF_X4"
|
||||
|
||||
replace_cell buf1 NangateOpenCellLibrary/BUF_X1
|
||||
report_checks
|
||||
puts "PASS: buf1 restored"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X2
|
||||
report_checks
|
||||
puts "PASS: inv1->INV_X2"
|
||||
|
||||
replace_cell inv1 NangateOpenCellLibrary/INV_X1
|
||||
report_checks
|
||||
puts "PASS: inv1 restored"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Disable/enable timing on edges
|
||||
|
|
@ -195,21 +171,17 @@ puts "--- disable/enable timing ---"
|
|||
|
||||
set_disable_timing [get_cells buf1]
|
||||
report_checks
|
||||
puts "PASS: disable buf1"
|
||||
|
||||
set_disable_timing [get_cells inv1]
|
||||
report_checks
|
||||
puts "PASS: disable inv1"
|
||||
|
||||
set_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: disable nand1"
|
||||
|
||||
unset_disable_timing [get_cells buf1]
|
||||
unset_disable_timing [get_cells inv1]
|
||||
unset_disable_timing [get_cells nand1]
|
||||
report_checks
|
||||
puts "PASS: re-enable all"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Case analysis: exercises setConstant, clearConstants
|
||||
|
|
@ -218,28 +190,22 @@ puts "--- case analysis ---"
|
|||
|
||||
set_case_analysis 1 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=1"
|
||||
|
||||
set_case_analysis 0 [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst=0"
|
||||
|
||||
unset_case_analysis [get_ports rst]
|
||||
report_checks
|
||||
puts "PASS: rst unset"
|
||||
|
||||
set_case_analysis 1 [get_ports d1]
|
||||
report_checks
|
||||
puts "PASS: d1=1"
|
||||
|
||||
set_case_analysis 0 [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: d3=0"
|
||||
|
||||
unset_case_analysis [get_ports d1]
|
||||
unset_case_analysis [get_ports d3]
|
||||
report_checks
|
||||
puts "PASS: all unset"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# Load changes trigger delay recomputation on graph edges
|
||||
|
|
@ -248,15 +214,12 @@ puts "--- load changes ---"
|
|||
|
||||
set_load 0.01 [get_ports q1]
|
||||
report_checks
|
||||
puts "PASS: q1 load=0.01"
|
||||
|
||||
set_load 0.05 [get_ports q2]
|
||||
report_checks
|
||||
puts "PASS: q2 load=0.05"
|
||||
|
||||
set_load 0.1 [get_ports q3]
|
||||
report_checks
|
||||
puts "PASS: q3 load=0.1"
|
||||
|
||||
set_load 0 [get_ports q1]
|
||||
set_load 0 [get_ports q2]
|
||||
|
|
@ -267,28 +230,22 @@ set_load 0 [get_ports q3]
|
|||
#---------------------------------------------------------------
|
||||
puts "--- through pin queries ---"
|
||||
|
||||
catch {report_checks -through [get_pins nand1/ZN]} msg
|
||||
report_checks -through [get_pins nand1/ZN]
|
||||
puts "through nand1: done"
|
||||
|
||||
catch {report_checks -through [get_pins nor1/ZN]} msg
|
||||
report_checks -through [get_pins nor1/ZN]
|
||||
puts "through nor1: done"
|
||||
|
||||
catch {report_checks -through [get_pins and2/ZN]} msg
|
||||
report_checks -through [get_pins and2/ZN]
|
||||
puts "through and2: done"
|
||||
|
||||
catch {report_checks -through [get_pins or2/ZN]} msg
|
||||
report_checks -through [get_pins or2/ZN]
|
||||
puts "through or2: done"
|
||||
|
||||
puts "PASS: through pin queries"
|
||||
|
||||
#---------------------------------------------------------------
|
||||
# report_check_types exercises check edge categorization
|
||||
#---------------------------------------------------------------
|
||||
puts "--- report_check_types ---"
|
||||
report_check_types -max_delay -verbose
|
||||
puts "PASS: check_types max"
|
||||
|
||||
report_check_types -min_delay -verbose
|
||||
puts "PASS: check_types min"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -104,11 +104,11 @@ add_test(
|
|||
set_tests_properties(tcl.liberty.opcond_scale PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.ccsn_ecsm
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_ccsn_ecsm
|
||||
NAME tcl.liberty.ccsn
|
||||
COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> liberty_ccsn
|
||||
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
set_tests_properties(tcl.liberty.ccsn_ecsm PROPERTIES LABELS "tcl;module_liberty")
|
||||
set_tests_properties(tcl.liberty.ccsn PROPERTIES LABELS "tcl;module_liberty")
|
||||
|
||||
add_test(
|
||||
NAME tcl.liberty.cell_deep
|
||||
|
|
|
|||
|
|
@ -1,69 +1,44 @@
|
|||
PASS: read Nangate45
|
||||
PASS: find_liberty_cells_matching INV_* (6 cells)
|
||||
PASS: find_liberty_cells_matching regexp BUF (6 cells)
|
||||
PASS: find_liberty_cells_matching nocase nand2 (0 cells)
|
||||
INV_X1 is_leaf = 1
|
||||
INV_X1 is_buffer = 0
|
||||
INV_X1 is_inverter = 1
|
||||
PASS: INV_X1 classification
|
||||
BUF_X1 is_leaf = 1
|
||||
BUF_X1 is_buffer = 1
|
||||
BUF_X1 is_inverter = 0
|
||||
PASS: BUF_X1 classification
|
||||
NAND2_X1 is_leaf = 1
|
||||
NAND2_X1 is_buffer = 0
|
||||
NAND2_X1 is_inverter = 0
|
||||
PASS: NAND2_X1 classification
|
||||
DFF_X1 is_leaf = 1
|
||||
DFF_X1 is_buffer = 0
|
||||
DFF_X1 is_inverter = 0
|
||||
PASS: DFF_X1 classification
|
||||
INV_X1 lib name = NangateOpenCellLibrary
|
||||
PASS: cell liberty_library
|
||||
SDFF_X1 has test_cell
|
||||
PASS: test_cell query
|
||||
INV_X1/A function =
|
||||
INV_X1/ZN function = !A
|
||||
PASS: port function
|
||||
TINV_X1/EN function =
|
||||
TINV_X1/ZN tristate_enable = !EN
|
||||
PASS: tristate_enable
|
||||
INV_X1/A bus_name = A
|
||||
PASS: bus_name
|
||||
INV_X1/A is_bus = 0
|
||||
INV_X1/A is_bus_bit = 0
|
||||
INV_X1/A is_bundle = 0
|
||||
INV_X1/A is_bundle_member = 0
|
||||
INV_X1/A has_members = 0
|
||||
PASS: port bus/bundle queries
|
||||
INV_X1/A is_pwr_gnd = 0
|
||||
PASS: is_pwr_gnd
|
||||
INV_X1/A scan_signal_type = none
|
||||
PASS: scan_signal_type
|
||||
SDFF_X1/SI scan_signal_type = none
|
||||
SDFF_X1/SI is_bus = 0
|
||||
PASS: scan port queries
|
||||
INV_X1 all ports = 4
|
||||
PASS: find_liberty_ports_matching *
|
||||
NAND2_X1 A* ports = 2
|
||||
PASS: find_liberty_ports_matching A*
|
||||
NAND2_X1 regexp ports = 2
|
||||
PASS: find_liberty_ports_matching regexp
|
||||
NAND2_X1 nocase zn ports = 0
|
||||
PASS: find_liberty_ports_matching nocase
|
||||
INV_X1 ports via iterator = 4
|
||||
PASS: LibertyCellPortIterator
|
||||
AOI21_X1 ports via iterator = 6
|
||||
PASS: AOI21_X1 port iterator
|
||||
Arc: INV_X1 A -> ZN role=combinational is_check=0
|
||||
sdf_cond=
|
||||
PASS: INV_X1 timing arc sets
|
||||
DFF Arc: DFF_X1 CK -> D role=hold is_check=1
|
||||
DFF Arc: DFF_X1 CK -> D role=setup is_check=1
|
||||
DFF Arc: DFF_X1 CK -> CK role=width is_check=1
|
||||
DFF Arc: DFF_X1 CK -> Q role=Reg Clk to Q is_check=0
|
||||
DFF Arc: DFF_X1 CK -> QN role=Reg Clk to Q is_check=0
|
||||
PASS: DFF_X1 timing arc sets
|
||||
DFFR Arc: DFFR_X1 CK -> D role=hold is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> D role=setup is_check=1
|
||||
DFFR Arc: DFFR_X1 CK -> RN role=recovery is_check=1
|
||||
|
|
@ -80,10 +55,8 @@ DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
|||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
|
||||
PASS: DFFR_X1 timing arc sets
|
||||
Arc detail: A rise -> ZN fall role=combinational
|
||||
Arc detail: A fall -> ZN rise role=combinational
|
||||
PASS: timing arc details
|
||||
DFF arc: rise -> rise role=hold
|
||||
DFF arc: rise -> fall role=hold
|
||||
DFF arc: rise -> rise role=setup
|
||||
|
|
@ -94,27 +67,19 @@ PASS: timing arc details
|
|||
DFF arc: rise -> fall role=Reg Clk to Q
|
||||
DFF arc: rise -> rise role=Reg Clk to Q
|
||||
DFF arc: rise -> fall role=Reg Clk to Q
|
||||
PASS: DFF arc edge details
|
||||
Default opcond process = 1.0
|
||||
Default opcond voltage = 1.100000023841858
|
||||
Default opcond temperature = 25.0
|
||||
PASS: operating conditions
|
||||
Typical opcond process = 1.0
|
||||
Typical opcond voltage = 1.100000023841858
|
||||
Typical opcond temperature = 25.0
|
||||
PASS: named operating conditions
|
||||
Found wireload 5K_hvratio_1_1
|
||||
PASS: find_wireload
|
||||
Found wireload selection
|
||||
PASS: find_wireload_selection
|
||||
Library: NangateOpenCellLibrary
|
||||
PASS: liberty_library_iterator (1 libraries)
|
||||
INV_X1/A cap max = 1.700229965024007e-15
|
||||
INV_X1/A cap min = 1.5493600563490969e-15
|
||||
PASS: port capacitance with corner
|
||||
PwrGnd port: VDD dir=power
|
||||
PwrGnd port: VSS dir=ground
|
||||
PASS: pwr_gnd port queries
|
||||
FA_X1 port: VDD dir=power is_bus=0
|
||||
FA_X1 port: VSS dir=ground is_bus=0
|
||||
FA_X1 port: A dir=input is_bus=0
|
||||
|
|
@ -122,5 +87,3 @@ PASS: pwr_gnd port queries
|
|||
FA_X1 port: CI dir=input is_bus=0
|
||||
FA_X1 port: CO dir=output is_bus=0
|
||||
FA_X1 port: S dir=output is_bus=0
|
||||
PASS: FA_X1 port iterator
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ source ../../test/helpers.tcl
|
|||
# Read library
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
############################################################
|
||||
# find_liberty_cells_matching with pattern/regexp/nocase
|
||||
|
|
@ -28,15 +27,12 @@ set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
|||
|
||||
# Glob pattern matching
|
||||
set cells [$lib find_liberty_cells_matching "INV_*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching INV_* ([llength $cells] cells)"
|
||||
|
||||
# Regexp matching
|
||||
set cells_re [$lib find_liberty_cells_matching {^BUF_X[0-9]+$} 1 0]
|
||||
puts "PASS: find_liberty_cells_matching regexp BUF ([llength $cells_re] cells)"
|
||||
|
||||
# Case-insensitive matching
|
||||
set cells_nc [$lib find_liberty_cells_matching "nand2_*" 0 1]
|
||||
puts "PASS: find_liberty_cells_matching nocase nand2 ([llength $cells_nc] cells)"
|
||||
|
||||
############################################################
|
||||
# Cell property queries: is_leaf, is_buffer, is_inverter
|
||||
|
|
@ -45,46 +41,38 @@ set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
|||
puts "INV_X1 is_leaf = [$inv_cell is_leaf]"
|
||||
puts "INV_X1 is_buffer = [$inv_cell is_buffer]"
|
||||
puts "INV_X1 is_inverter = [$inv_cell is_inverter]"
|
||||
puts "PASS: INV_X1 classification"
|
||||
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
puts "BUF_X1 is_leaf = [$buf_cell is_leaf]"
|
||||
puts "BUF_X1 is_buffer = [$buf_cell is_buffer]"
|
||||
puts "BUF_X1 is_inverter = [$buf_cell is_inverter]"
|
||||
puts "PASS: BUF_X1 classification"
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
puts "NAND2_X1 is_leaf = [$nand_cell is_leaf]"
|
||||
puts "NAND2_X1 is_buffer = [$nand_cell is_buffer]"
|
||||
puts "NAND2_X1 is_inverter = [$nand_cell is_inverter]"
|
||||
puts "PASS: NAND2_X1 classification"
|
||||
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
puts "DFF_X1 is_leaf = [$dff_cell is_leaf]"
|
||||
puts "DFF_X1 is_buffer = [$dff_cell is_buffer]"
|
||||
puts "DFF_X1 is_inverter = [$dff_cell is_inverter]"
|
||||
puts "PASS: DFF_X1 classification"
|
||||
|
||||
############################################################
|
||||
# Cell liberty_library method
|
||||
############################################################
|
||||
set cell_lib [$inv_cell liberty_library]
|
||||
puts "INV_X1 lib name = [$cell_lib name]"
|
||||
puts "PASS: cell liberty_library"
|
||||
|
||||
############################################################
|
||||
# Cell test_cell (for scan cells)
|
||||
############################################################
|
||||
catch {
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set test_cell [$sdff_cell test_cell]
|
||||
if {$test_cell ne ""} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set test_cell [$sdff_cell test_cell]
|
||||
if {$test_cell ne ""} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
puts "PASS: test_cell query"
|
||||
|
||||
############################################################
|
||||
# Port queries: bus_name, function, tristate_enable, scan_signal_type
|
||||
|
|
@ -95,7 +83,6 @@ set inv_a [$inv_cell find_liberty_port A]
|
|||
set inv_zn [$inv_cell find_liberty_port ZN]
|
||||
puts "INV_X1/A function = [$inv_a function]"
|
||||
puts "INV_X1/ZN function = [$inv_zn function]"
|
||||
puts "PASS: port function"
|
||||
|
||||
# Tristate enable
|
||||
set tinv_cell [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
|
|
@ -103,11 +90,9 @@ set tinv_en [$tinv_cell find_liberty_port EN]
|
|||
set tinv_out [$tinv_cell find_liberty_port ZN]
|
||||
puts "TINV_X1/EN function = [$tinv_en function]"
|
||||
puts "TINV_X1/ZN tristate_enable = [$tinv_out tristate_enable]"
|
||||
puts "PASS: tristate_enable"
|
||||
|
||||
# Bus name (for bus ports - may be same as name for non-bus)
|
||||
puts "INV_X1/A bus_name = [$inv_a bus_name]"
|
||||
puts "PASS: bus_name"
|
||||
|
||||
# Is bus/bundle queries
|
||||
puts "INV_X1/A is_bus = [$inv_a is_bus]"
|
||||
|
|
@ -115,47 +100,37 @@ puts "INV_X1/A is_bus_bit = [$inv_a is_bus_bit]"
|
|||
puts "INV_X1/A is_bundle = [$inv_a is_bundle]"
|
||||
puts "INV_X1/A is_bundle_member = [$inv_a is_bundle_member]"
|
||||
puts "INV_X1/A has_members = [$inv_a has_members]"
|
||||
puts "PASS: port bus/bundle queries"
|
||||
|
||||
# is_pwr_gnd
|
||||
puts "INV_X1/A is_pwr_gnd = [$inv_a is_pwr_gnd]"
|
||||
puts "PASS: is_pwr_gnd"
|
||||
|
||||
# scan_signal_type
|
||||
puts "INV_X1/A scan_signal_type = [$inv_a scan_signal_type]"
|
||||
puts "PASS: scan_signal_type"
|
||||
|
||||
# Check SDFF scan port
|
||||
catch {
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_si [$sdff_cell find_liberty_port SI]
|
||||
if {$sdff_si ne ""} {
|
||||
puts "SDFF_X1/SI scan_signal_type = [$sdff_si scan_signal_type]"
|
||||
puts "SDFF_X1/SI is_bus = [$sdff_si is_bus]"
|
||||
}
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_si [$sdff_cell find_liberty_port SI]
|
||||
if {$sdff_si ne ""} {
|
||||
puts "SDFF_X1/SI scan_signal_type = [$sdff_si scan_signal_type]"
|
||||
puts "SDFF_X1/SI is_bus = [$sdff_si is_bus]"
|
||||
}
|
||||
puts "PASS: scan port queries"
|
||||
|
||||
############################################################
|
||||
# find_liberty_ports_matching on a cell
|
||||
############################################################
|
||||
set ports [$inv_cell find_liberty_ports_matching "*" 0 0]
|
||||
puts "INV_X1 all ports = [llength $ports]"
|
||||
puts "PASS: find_liberty_ports_matching *"
|
||||
|
||||
set ports [$nand_cell find_liberty_ports_matching "A*" 0 0]
|
||||
puts "NAND2_X1 A* ports = [llength $ports]"
|
||||
puts "PASS: find_liberty_ports_matching A*"
|
||||
|
||||
# Regexp port matching
|
||||
set ports_re [$nand_cell find_liberty_ports_matching {^A[0-9]$} 1 0]
|
||||
puts "NAND2_X1 regexp ports = [llength $ports_re]"
|
||||
puts "PASS: find_liberty_ports_matching regexp"
|
||||
|
||||
# Case-insensitive port matching
|
||||
set ports_nc [$nand_cell find_liberty_ports_matching "zn" 0 1]
|
||||
puts "NAND2_X1 nocase zn ports = [llength $ports_nc]"
|
||||
puts "PASS: find_liberty_ports_matching nocase"
|
||||
|
||||
############################################################
|
||||
# LibertyCellPortIterator
|
||||
|
|
@ -168,7 +143,6 @@ while {[$port_iter has_next]} {
|
|||
}
|
||||
$port_iter finish
|
||||
puts "INV_X1 ports via iterator = $port_count"
|
||||
puts "PASS: LibertyCellPortIterator"
|
||||
|
||||
# Port iterator on a more complex cell
|
||||
set aoi_cell [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
|
|
@ -181,7 +155,6 @@ while {[$port_iter has_next]} {
|
|||
}
|
||||
$port_iter finish
|
||||
puts "AOI21_X1 ports via iterator = $port_count"
|
||||
puts "PASS: AOI21_X1 port iterator"
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries: full_name, sdf_cond, role
|
||||
|
|
@ -194,12 +167,9 @@ foreach arc_set $arc_sets {
|
|||
set role [$arc_set role]
|
||||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "Arc: $fn role=$role is_check=$is_check"
|
||||
catch {
|
||||
set sdf [$arc_set sdf_cond]
|
||||
puts " sdf_cond=$sdf"
|
||||
}
|
||||
set sdf [$arc_set sdf_cond]
|
||||
puts " sdf_cond=$sdf"
|
||||
}
|
||||
puts "PASS: INV_X1 timing arc sets"
|
||||
|
||||
# DFF timing arcs (setup/hold/clk-to-q)
|
||||
set arc_sets [$dff_cell timing_arc_sets]
|
||||
|
|
@ -209,7 +179,6 @@ foreach arc_set $arc_sets {
|
|||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "DFF Arc: $fn role=$role is_check=$is_check"
|
||||
}
|
||||
puts "PASS: DFF_X1 timing arc sets"
|
||||
|
||||
# DFFR has more arcs (recovery/removal)
|
||||
set dffr_cell [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
|
|
@ -220,7 +189,6 @@ foreach arc_set $arc_sets {
|
|||
set is_check [sta::timing_role_is_check $role]
|
||||
puts "DFFR Arc: $fn role=$role is_check=$is_check"
|
||||
}
|
||||
puts "PASS: DFFR_X1 timing arc sets"
|
||||
|
||||
############################################################
|
||||
# TimingArc details: from_edge_name, to_edge_name
|
||||
|
|
@ -237,7 +205,6 @@ foreach arc_set $arc_sets {
|
|||
puts " Arc detail: ${from_name} ${from_edge} -> ${to_name} ${to_edge} role=$arc_role"
|
||||
}
|
||||
}
|
||||
puts "PASS: timing arc details"
|
||||
|
||||
# DFF arc details (different roles: setup, hold, clk-to-q)
|
||||
set arc_sets [$dff_cell timing_arc_sets]
|
||||
|
|
@ -250,7 +217,6 @@ foreach arc_set $arc_sets {
|
|||
puts " DFF arc: ${from_edge} -> ${to_edge} role=$arc_role"
|
||||
}
|
||||
}
|
||||
puts "PASS: DFF arc edge details"
|
||||
|
||||
############################################################
|
||||
# Operating conditions queries
|
||||
|
|
@ -261,37 +227,27 @@ if {$op_cond ne ""} {
|
|||
puts "Default opcond voltage = [$op_cond voltage]"
|
||||
puts "Default opcond temperature = [$op_cond temperature]"
|
||||
}
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
# Named operating conditions
|
||||
catch {
|
||||
set typical_cond [$lib find_operating_conditions typical]
|
||||
if {$typical_cond ne ""} {
|
||||
puts "Typical opcond process = [$typical_cond process]"
|
||||
puts "Typical opcond voltage = [$typical_cond voltage]"
|
||||
puts "Typical opcond temperature = [$typical_cond temperature]"
|
||||
}
|
||||
set typical_cond [$lib find_operating_conditions typical]
|
||||
if {$typical_cond ne ""} {
|
||||
puts "Typical opcond process = [$typical_cond process]"
|
||||
puts "Typical opcond voltage = [$typical_cond voltage]"
|
||||
puts "Typical opcond temperature = [$typical_cond temperature]"
|
||||
}
|
||||
puts "PASS: named operating conditions"
|
||||
|
||||
############################################################
|
||||
# Wireload queries
|
||||
############################################################
|
||||
catch {
|
||||
set wl [$lib find_wireload "5K_hvratio_1_1"]
|
||||
if {$wl ne ""} {
|
||||
puts "Found wireload 5K_hvratio_1_1"
|
||||
}
|
||||
set wl [$lib find_wireload "5K_hvratio_1_1"]
|
||||
if {$wl ne ""} {
|
||||
puts "Found wireload 5K_hvratio_1_1"
|
||||
}
|
||||
puts "PASS: find_wireload"
|
||||
|
||||
catch {
|
||||
set wlsel [$lib find_wireload_selection "WiresloaSelection"]
|
||||
if {$wlsel ne ""} {
|
||||
puts "Found wireload selection"
|
||||
}
|
||||
set wlsel [$lib find_wireload_selection "WiresloaSelection"]
|
||||
if {$wlsel ne ""} {
|
||||
puts "Found wireload selection"
|
||||
}
|
||||
puts "PASS: find_wireload_selection"
|
||||
|
||||
############################################################
|
||||
# LibertyLibraryIterator
|
||||
|
|
@ -304,20 +260,16 @@ while {[$lib_iter has_next]} {
|
|||
incr lib_count
|
||||
}
|
||||
$lib_iter finish
|
||||
puts "PASS: liberty_library_iterator ($lib_count libraries)"
|
||||
|
||||
############################################################
|
||||
# Port capacitance with corner/min_max
|
||||
############################################################
|
||||
set corner [lindex [sta::corners] 0]
|
||||
set inv_a_port [$inv_cell find_liberty_port A]
|
||||
catch {
|
||||
set cap_max [$inv_a_port capacitance $corner "max"]
|
||||
puts "INV_X1/A cap max = $cap_max"
|
||||
set cap_min [$inv_a_port capacitance $corner "min"]
|
||||
puts "INV_X1/A cap min = $cap_min"
|
||||
}
|
||||
puts "PASS: port capacitance with corner"
|
||||
set cap_max [$inv_a_port capacitance $corner "max"]
|
||||
puts "INV_X1/A cap max = $cap_max"
|
||||
set cap_min [$inv_a_port capacitance $corner "min"]
|
||||
puts "INV_X1/A cap min = $cap_min"
|
||||
|
||||
############################################################
|
||||
# Power ground port queries
|
||||
|
|
@ -330,19 +282,13 @@ while {[$port_iter has_next]} {
|
|||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "PASS: pwr_gnd port queries"
|
||||
|
||||
# Check a cell with bus ports (FA_X1 has bus-like ports)
|
||||
catch {
|
||||
set fa_cell [get_lib_cell NangateOpenCellLibrary/FA_X1]
|
||||
set port_iter [$fa_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
puts " FA_X1 port: [$port bus_name] dir=$dir is_bus=[$port is_bus]"
|
||||
}
|
||||
$port_iter finish
|
||||
set fa_cell [get_lib_cell NangateOpenCellLibrary/FA_X1]
|
||||
set port_iter [$fa_cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
puts " FA_X1 port: [$port bus_name] dir=$dir is_bus=[$port is_bus]"
|
||||
}
|
||||
puts "PASS: FA_X1 port iterator"
|
||||
|
||||
puts "ALL PASSED"
|
||||
$port_iter finish
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
PASS: read fakeram45_64x7
|
||||
fakeram cell found
|
||||
clk dir=input bus=0 bit=0 bundle=0 bm=0 members=0 func="" tri=""
|
||||
rd_out dir=output bus=1 bit=0 bundle=0 bm=0 members=1 func="" tri=""
|
||||
|
|
@ -23,18 +22,13 @@ fakeram cell found
|
|||
member[1]: w_mask_in[5] dir=input bit=1
|
||||
member[2]: w_mask_in[4] dir=input bit=1
|
||||
total members=7
|
||||
PASS: fakeram bus port iteration
|
||||
fakeram45_64x32: bus_ports=4 total_bits=102
|
||||
fakeram45_256x16: bus_ports=4 total_bits=56
|
||||
fakeram45_512x64: bus_ports=4 total_bits=201
|
||||
fakeram45_1024x32: bus_ports=4 total_bits=106
|
||||
fakeram45_64x96: bus_ports=4 total_bits=294
|
||||
PASS: SRAM macro bus ports
|
||||
PASS: read gf180mcu SRAM
|
||||
Warning: liberty_busport_mem_iter.tcl line 1, library 'gf180mcu_fd_ip_sram__sram256x8m8wm1' not found.
|
||||
gf180mcu cells: 0
|
||||
PASS: gf180mcu SRAM bus ports
|
||||
PASS: read Nangate45
|
||||
INV_X1 leaf=1 buf=0 inv=1 area=0.532000 du=0 arcs=1
|
||||
INV_X2 leaf=1 buf=0 inv=1 area=0.798000 du=0 arcs=1
|
||||
BUF_X1 leaf=1 buf=1 inv=0 area=0.798000 du=0 arcs=1
|
||||
|
|
@ -68,20 +62,17 @@ FILLCELL_X1 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
|||
FILLCELL_X2 leaf=1 buf=0 inv=0 area=0.266000 du=1 arcs=0
|
||||
LOGIC0_X1 leaf=1 buf=0 inv=0 area=0.532000 du=1 arcs=0
|
||||
LOGIC1_X1 leaf=1 buf=0 inv=0 area=0.532000 du=1 arcs=0
|
||||
PASS: cell classification
|
||||
--- test_cell / scan queries ---
|
||||
SDFF_X1 test_cell is null
|
||||
SDFFR_X1 test_cell is null
|
||||
SDFFRS_X1 test_cell is null
|
||||
DFF_X1 has no test_cell (expected)
|
||||
PASS: test_cell queries
|
||||
--- function and tristate queries ---
|
||||
TINV_X1/VDD dir=power func="" tri=""
|
||||
TINV_X1/VSS dir=ground func="" tri=""
|
||||
TINV_X1/EN dir=input func="" tri=""
|
||||
TINV_X1/I dir=input func="" tri=""
|
||||
TINV_X1/ZN dir=tristate func="!I" tri="!EN"
|
||||
PASS: TINV tristate queries
|
||||
CLKGATETST_X1/VDD dir=power func=""
|
||||
CLKGATETST_X1/VSS dir=ground func=""
|
||||
CLKGATETST_X1/IQ dir=internal func=""
|
||||
|
|
@ -89,7 +80,6 @@ CLKGATETST_X1/CK dir=input func=""
|
|||
CLKGATETST_X1/E dir=input func=""
|
||||
CLKGATETST_X1/SE dir=input func=""
|
||||
CLKGATETST_X1/GCK dir=output func=""
|
||||
PASS: CLKGATETST queries
|
||||
INV_X1/ZN func=!A
|
||||
BUF_X1/Z func=A
|
||||
NAND2_X1/ZN func=!(A1*A2)
|
||||
|
|
@ -105,18 +95,11 @@ HA_X1/CO func=A*B
|
|||
HA_X1/S func=A^B
|
||||
FA_X1/CO func=(A*B)+(CI*(A+B))
|
||||
FA_X1/S func=CI^(A^B)
|
||||
PASS: output function queries
|
||||
PASS: read Sky130
|
||||
sky130_fd_sc_hd__ebufn_1/A dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_1/TE_B dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_1/Z dir=tristate func="A" tri="!TE_B"
|
||||
sky130_fd_sc_hd__ebufn_2/A dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_2/TE_B dir=input func="" tri=""
|
||||
sky130_fd_sc_hd__ebufn_2/Z dir=tristate func="A" tri="!TE_B"
|
||||
PASS: Sky130 tristate port queries
|
||||
Warning: ../../test/nangate45/fake_macros.lib line 32, default_max_transition is 0.0.
|
||||
PASS: read fake_macros
|
||||
PASS: write_liberty fakeram
|
||||
Warning: /workspace/sta/OpenSTA/liberty/test/results/liberty_busport_mem_iter_write.lib line 1, library fakeram45_64x7 already exists.
|
||||
PASS: read roundtrip library
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ source ../../test/helpers.tcl
|
|||
# Read SRAM macro library (has bus ports)
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/fakeram45_64x7.lib
|
||||
puts "PASS: read fakeram45_64x7"
|
||||
|
||||
# Query bus port properties
|
||||
set cell [get_lib_cell fakeram45_64x7/fakeram45_64x7]
|
||||
|
|
@ -56,72 +55,63 @@ while {[$port_iter has_next]} {
|
|||
}
|
||||
}
|
||||
$port_iter finish
|
||||
puts "PASS: fakeram bus port iteration"
|
||||
|
||||
############################################################
|
||||
# Read other SRAM macros with different bus widths
|
||||
############################################################
|
||||
foreach lib_name {fakeram45_64x32 fakeram45_256x16 fakeram45_512x64
|
||||
fakeram45_1024x32 fakeram45_64x96} {
|
||||
catch {
|
||||
read_liberty ../../test/nangate45/${lib_name}.lib
|
||||
set cell [get_lib_cell ${lib_name}/${lib_name}]
|
||||
if {$cell != "NULL"} {
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
set bit_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus]} {
|
||||
incr bus_count
|
||||
set mem_iter [$port member_iterator]
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
incr bit_count
|
||||
}
|
||||
$mem_iter finish
|
||||
read_liberty ../../test/nangate45/${lib_name}.lib
|
||||
set cell [get_lib_cell ${lib_name}/${lib_name}]
|
||||
if {$cell != "NULL"} {
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
set bit_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus]} {
|
||||
incr bus_count
|
||||
set mem_iter [$port member_iterator]
|
||||
while {[$mem_iter has_next]} {
|
||||
set mem [$mem_iter next]
|
||||
incr bit_count
|
||||
}
|
||||
$mem_iter finish
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$lib_name: bus_ports=$bus_count total_bits=$bit_count"
|
||||
}
|
||||
$port_iter finish
|
||||
puts "$lib_name: bus_ports=$bus_count total_bits=$bit_count"
|
||||
}
|
||||
}
|
||||
puts "PASS: SRAM macro bus ports"
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro from GF180MCU
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
puts "PASS: read gf180mcu SRAM"
|
||||
|
||||
catch {
|
||||
set gf_cells [get_lib_cells gf180mcu_fd_ip_sram__sram256x8m8wm1/*]
|
||||
puts "gf180mcu cells: [llength $gf_cells]"
|
||||
foreach cell_obj $gf_cells {
|
||||
set cname [get_full_name $cell_obj]
|
||||
catch {
|
||||
set cell [get_lib_cell $cname]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus] || [$port has_members]} {
|
||||
incr bus_count
|
||||
}
|
||||
set gf_cells [get_lib_cells gf180mcu_fd_ip_sram__sram256x8m8wm1/*]
|
||||
puts "gf180mcu cells: [llength $gf_cells]"
|
||||
foreach cell_obj $gf_cells {
|
||||
set cname [get_full_name $cell_obj]
|
||||
catch {
|
||||
set cell [get_lib_cell $cname]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
set bus_count 0
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
if {[$port is_bus] || [$port has_members]} {
|
||||
incr bus_count
|
||||
}
|
||||
$port_iter finish
|
||||
puts " [get_name $cell_obj]: bus_ports=$bus_count"
|
||||
}
|
||||
$port_iter finish
|
||||
puts " [get_name $cell_obj]: bus_ports=$bus_count"
|
||||
}
|
||||
}
|
||||
puts "PASS: gf180mcu SRAM bus ports"
|
||||
|
||||
############################################################
|
||||
# Read Nangate for cell classification queries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
# Cell classification
|
||||
foreach cell_name {INV_X1 INV_X2 BUF_X1 BUF_X2 CLKBUF_X1
|
||||
|
|
@ -131,21 +121,18 @@ foreach cell_name {INV_X1 INV_X2 BUF_X1 BUF_X2 CLKBUF_X1
|
|||
SDFF_X1 SDFFR_X1 SDFFRS_X1 TLAT_X1
|
||||
TINV_X1 CLKGATETST_X1 HA_X1 FA_X1
|
||||
ANTENNA_X1 FILLCELL_X1 FILLCELL_X2 LOGIC0_X1 LOGIC1_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set is_leaf [$cell is_leaf]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
set area [get_property $cell area]
|
||||
set du [get_property $cell dont_use]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
set arc_count [llength $arc_sets]
|
||||
puts "$cell_name leaf=$is_leaf buf=$is_buf inv=$is_inv area=$area du=$du arcs=$arc_count"
|
||||
}
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
if {$cell != "NULL"} {
|
||||
set is_leaf [$cell is_leaf]
|
||||
set is_buf [$cell is_buffer]
|
||||
set is_inv [$cell is_inverter]
|
||||
set area [get_property $cell area]
|
||||
set du [get_property $cell dont_use]
|
||||
set arc_sets [$cell timing_arc_sets]
|
||||
set arc_count [llength $arc_sets]
|
||||
puts "$cell_name leaf=$is_leaf buf=$is_buf inv=$is_inv area=$area du=$du arcs=$arc_count"
|
||||
}
|
||||
}
|
||||
puts "PASS: cell classification"
|
||||
|
||||
############################################################
|
||||
# Test cell and scan signal type queries
|
||||
|
|
@ -153,47 +140,38 @@ puts "PASS: cell classification"
|
|||
puts "--- test_cell / scan queries ---"
|
||||
|
||||
# SDFF has test_cell
|
||||
catch {
|
||||
set sdff [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set tc [$sdff test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
set sdff [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set tc [$sdff test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFF_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFF_X1 test_cell is null"
|
||||
}
|
||||
|
||||
catch {
|
||||
set sdffr [get_lib_cell NangateOpenCellLibrary/SDFFR_X1]
|
||||
set tc [$sdffr test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFFR_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFR_X1 test_cell is null"
|
||||
}
|
||||
set sdffr [get_lib_cell NangateOpenCellLibrary/SDFFR_X1]
|
||||
set tc [$sdffr test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFFR_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFR_X1 test_cell is null"
|
||||
}
|
||||
|
||||
catch {
|
||||
set sdffrs [get_lib_cell NangateOpenCellLibrary/SDFFRS_X1]
|
||||
set tc [$sdffrs test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFFRS_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFRS_X1 test_cell is null"
|
||||
}
|
||||
set sdffrs [get_lib_cell NangateOpenCellLibrary/SDFFRS_X1]
|
||||
set tc [$sdffrs test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "SDFFRS_X1 has test_cell"
|
||||
} else {
|
||||
puts "SDFFRS_X1 test_cell is null"
|
||||
}
|
||||
|
||||
# Regular DFF should NOT have test_cell
|
||||
catch {
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set tc [$dff test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "DFF_X1 has test_cell (unexpected)"
|
||||
} else {
|
||||
puts "DFF_X1 has no test_cell (expected)"
|
||||
}
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set tc [$dff test_cell]
|
||||
if {$tc != "NULL"} {
|
||||
puts "DFF_X1 has test_cell (unexpected)"
|
||||
} else {
|
||||
puts "DFF_X1 has no test_cell (expected)"
|
||||
}
|
||||
puts "PASS: test_cell queries"
|
||||
|
||||
############################################################
|
||||
# Port function and tristate enable queries
|
||||
|
|
@ -201,107 +179,87 @@ puts "PASS: test_cell queries"
|
|||
puts "--- function and tristate queries ---"
|
||||
|
||||
# Tristate inverter
|
||||
catch {
|
||||
set tinv [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
set port_iter [$tinv liberty_port_iterator]
|
||||
set tinv [get_lib_cell NangateOpenCellLibrary/TINV_X1]
|
||||
set port_iter [$tinv liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
puts "TINV_X1/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
# Clock gate tester
|
||||
set clkgt [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
set port_iter [$clkgt liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
puts "CLKGATETST_X1/$name dir=$dir func=\"$func\""
|
||||
}
|
||||
$port_iter finish
|
||||
|
||||
# Output functions for various logic cells
|
||||
foreach cell_name {INV_X1 BUF_X1 NAND2_X1 NOR2_X1 AND2_X1 OR2_X1
|
||||
XOR2_X1 XNOR2_X1 AOI21_X1 OAI21_X1 MUX2_X1
|
||||
HA_X1 FA_X1} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
if {$dir == "output"} {
|
||||
set func [$port function]
|
||||
if {$func != ""} {
|
||||
puts "$cell_name/[get_name $port] func=$func"
|
||||
}
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read Sky130 for tristate and latch port queries
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
||||
# Tristate buffer port queries
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2} {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
puts "TINV_X1/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
set is_pg [$port is_pwr_gnd]
|
||||
if {!$is_pg} {
|
||||
puts "$cell_name/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: TINV tristate queries"
|
||||
|
||||
# Clock gate tester
|
||||
catch {
|
||||
set clkgt [get_lib_cell NangateOpenCellLibrary/CLKGATETST_X1]
|
||||
set port_iter [$clkgt liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
puts "CLKGATETST_X1/$name dir=$dir func=\"$func\""
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: CLKGATETST queries"
|
||||
|
||||
# Output functions for various logic cells
|
||||
foreach cell_name {INV_X1 BUF_X1 NAND2_X1 NOR2_X1 AND2_X1 OR2_X1
|
||||
XOR2_X1 XNOR2_X1 AOI21_X1 OAI21_X1 MUX2_X1
|
||||
HA_X1 FA_X1} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
if {$dir == "output"} {
|
||||
set func [$port function]
|
||||
if {$func != ""} {
|
||||
puts "$cell_name/[get_name $port] func=$func"
|
||||
}
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
puts "PASS: output function queries"
|
||||
|
||||
############################################################
|
||||
# Read Sky130 for tristate and latch port queries
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
# Tristate buffer port queries
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2} {
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/$cell_name]
|
||||
set port_iter [$cell liberty_port_iterator]
|
||||
while {[$port_iter has_next]} {
|
||||
set port [$port_iter next]
|
||||
set name [get_name $port]
|
||||
set dir [sta::liberty_port_direction $port]
|
||||
set func [$port function]
|
||||
set tri [$port tristate_enable]
|
||||
set is_pg [$port is_pwr_gnd]
|
||||
if {!$is_pg} {
|
||||
puts "$cell_name/$name dir=$dir func=\"$func\" tri=\"$tri\""
|
||||
}
|
||||
}
|
||||
$port_iter finish
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 tristate port queries"
|
||||
|
||||
############################################################
|
||||
# Read fake_macros library for memory/macro classification
|
||||
############################################################
|
||||
catch {
|
||||
read_liberty ../../test/nangate45/fake_macros.lib
|
||||
puts "PASS: read fake_macros"
|
||||
}
|
||||
read_liberty ../../test/nangate45/fake_macros.lib
|
||||
|
||||
############################################################
|
||||
# Write roundtrip with bus ports
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_busport_mem_iter_write.lib]
|
||||
sta::write_liberty fakeram45_64x7 $outfile
|
||||
puts "PASS: write_liberty fakeram"
|
||||
|
||||
# Read back
|
||||
catch {
|
||||
read_liberty $outfile
|
||||
puts "PASS: read roundtrip library"
|
||||
} msg
|
||||
if {[string match "Error*" $msg]} {
|
||||
puts "INFO: roundtrip issue: [string range $msg 0 80]"
|
||||
}
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,922 @@
|
|||
Cell A2O1A1Ixp33_ASAP7_75t_L
|
||||
Library asap7sc7p5t_AO_LVT_FF_ccsn_211120
|
||||
File ../../test/asap7_ccsn.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!B)+(!A2*!B))+!C
|
||||
A1 input 0.49-0.63
|
||||
A2 input 0.53-0.63
|
||||
B input 0.47-0.66
|
||||
C input 0.36-0.63
|
||||
Cell DFFHQNx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
QN output function=IQN
|
||||
CLK input 0.40-0.52
|
||||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
Cell DFFHQNx2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
QN output function=IQN
|
||||
CLK input 0.40-0.52
|
||||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
Warning: liberty_ccsn.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R' not found.
|
||||
Warning: liberty_ccsn.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R' not found.
|
||||
Cell ICGx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
IQ internal
|
||||
GCLK output
|
||||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
Cell ICGx2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
IQ internal
|
||||
GCLK output
|
||||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13277, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13310, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13343, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13376, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
Cell AO211x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)+B)+C
|
||||
A1 input 0.77-1.00
|
||||
A2 input 0.84-0.95
|
||||
B input 0.70-0.90
|
||||
C input 0.51-0.94
|
||||
Cell AO21x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(A1*A2)+B
|
||||
A1 input 0.46-0.62
|
||||
A2 input 0.38-0.63
|
||||
B input 0.50-0.63
|
||||
Cell AO21x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(A1*A2)+B
|
||||
A1 input 0.46-0.62
|
||||
A2 input 0.38-0.64
|
||||
B input 0.50-0.64
|
||||
Cell AO221x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)+(B1*B2))+C
|
||||
A1 input 0.40-0.52
|
||||
A2 input 0.43-0.49
|
||||
B1 input 0.33-0.57
|
||||
B2 input 0.37-0.54
|
||||
C input 0.41-0.53
|
||||
Cell AO221x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)+(B1*B2))+C
|
||||
A1 input 0.40-0.52
|
||||
A2 input 0.43-0.49
|
||||
B1 input 0.33-0.57
|
||||
B2 input 0.37-0.54
|
||||
C input 0.41-0.53
|
||||
Cell AO222x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)+(B1*B2))+(C1*C2)
|
||||
A1 input 0.45-0.61
|
||||
A2 input 0.50-0.58
|
||||
B1 input 0.45-0.61
|
||||
B2 input 0.46-0.56
|
||||
C1 input 0.39-0.65
|
||||
C2 input 0.43-0.61
|
||||
Cell AO22x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(A1*A2)+(B1*B2)
|
||||
A1 input 0.37-0.42
|
||||
A2 input 0.34-0.45
|
||||
B1 input 0.32-0.44
|
||||
B2 input 0.28-0.47
|
||||
Cell AO22x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(A1*A2)+(B1*B2)
|
||||
A1 input 0.51-0.57
|
||||
A2 input 0.46-0.62
|
||||
B1 input 0.45-0.61
|
||||
B2 input 0.38-0.65
|
||||
Cell AO31x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)*A3)+B
|
||||
A1 input 0.90-1.24
|
||||
A2 input 0.98-1.16
|
||||
A3 input 1.02-1.15
|
||||
B input 0.56-1.00
|
||||
Cell AO322x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+(B1*B2))+(C1*C2)
|
||||
A1 input 0.45-0.63
|
||||
A2 input 0.47-0.56
|
||||
A3 input 0.49-0.56
|
||||
B1 input 0.41-0.54
|
||||
B2 input 0.43-0.51
|
||||
C1 input 0.34-0.57
|
||||
C2 input 0.37-0.54
|
||||
Cell AO32x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)*A3)+(B1*B2)
|
||||
A1 input 0.38-0.56
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.45-0.52
|
||||
B1 input 0.30-0.49
|
||||
B2 input 0.33-0.44
|
||||
Cell AO32x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)*A3)+(B1*B2)
|
||||
A1 input 0.39-0.56
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.45-0.52
|
||||
B1 input 0.30-0.49
|
||||
B2 input 0.33-0.44
|
||||
Cell AO331x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+((B1*B2)*B3))+C
|
||||
A1 input 0.44-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.47-0.56
|
||||
C input 0.41-0.67
|
||||
Cell AO331x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+((B1*B2)*B3))+C
|
||||
A1 input 0.44-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.47-0.56
|
||||
C input 0.41-0.67
|
||||
Cell AO332x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+((B1*B2)*B3))+(C1*C2)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.39-0.65
|
||||
C2 input 0.43-0.61
|
||||
Cell AO332x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+((B1*B2)*B3))+(C1*C2)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.39-0.65
|
||||
C2 input 0.43-0.61
|
||||
Cell AO333x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+((B1*B2)*B3))+((C1*C2)*C3)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.46-0.56
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.43-0.61
|
||||
C1 input 0.38-0.65
|
||||
C2 input 0.42-0.59
|
||||
C3 input 0.43-0.61
|
||||
Cell AO333x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*A2)*A3)+((B1*B2)*B3))+((C1*C2)*C3)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.58
|
||||
B1 input 0.46-0.56
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.43-0.61
|
||||
C1 input 0.38-0.65
|
||||
C2 input 0.42-0.59
|
||||
C3 input 0.43-0.61
|
||||
Cell AO33x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*A2)*A3)+((B1*B2)*B3)
|
||||
A1 input 0.38-0.55
|
||||
A2 input 0.40-0.48
|
||||
A3 input 0.45-0.51
|
||||
B1 input 0.36-0.58
|
||||
B2 input 0.39-0.52
|
||||
B3 input 0.41-0.54
|
||||
Cell AOI211x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!B)*!C)+((!A2*!B)*!C)
|
||||
A1 input 0.81-0.92
|
||||
A2 input 0.76-1.00
|
||||
B input 0.77-0.98
|
||||
C input 0.61-1.06
|
||||
Cell AOI211xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!B)*!C)+((!A2*!B)*!C)
|
||||
A1 input 0.37-0.54
|
||||
A2 input 0.34-0.57
|
||||
B input 0.31-0.52
|
||||
C input 0.41-0.52
|
||||
Cell AOI21x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!B)+(!A2*!B)
|
||||
A1 input 0.88-1.24
|
||||
A2 input 0.96-1.09
|
||||
B input 0.74-1.24
|
||||
Cell AOI21xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!B)+(!A2*!B)
|
||||
A1 input 0.33-0.44
|
||||
A2 input 0.37-0.41
|
||||
B input 0.30-0.49
|
||||
Cell AOI21xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!B)+(!A2*!B)
|
||||
A1 input 0.43-0.60
|
||||
A2 input 0.50-0.57
|
||||
B input 0.35-0.60
|
||||
Cell AOI221x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((!A1*!B1)*!C)+((!A1*!B2)*!C))+((!A2*!B1)*!C))+((!A2*!B2)*!C)
|
||||
A1 input 0.77-0.98
|
||||
A2 input 0.83-0.93
|
||||
B1 input 0.77-0.98
|
||||
B2 input 0.78-0.94
|
||||
C input 0.53-0.95
|
||||
Cell AOI221xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((!A1*!B1)*!C)+((!A1*!B2)*!C))+((!A2*!B1)*!C))+((!A2*!B2)*!C)
|
||||
A1 input 0.40-0.52
|
||||
A2 input 0.43-0.49
|
||||
B1 input 0.33-0.57
|
||||
B2 input 0.36-0.54
|
||||
C input 0.41-0.53
|
||||
Cell AOI222xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((!A1*!B1)*!C1)+((!A1*!B1)*!C2))+((!A1*!B2)*!C1))+((!A1*!B2)*!C2))+((!A2*!B1)*!C1))+((!A2*!B1)*!C2))+((!A2*!B2)*!C1))+((!A2*!B2)*!C2)
|
||||
A1 input 0.33-0.57
|
||||
A2 input 0.36-0.54
|
||||
B1 input 0.39-0.52
|
||||
B2 input 0.40-0.49
|
||||
C1 input 0.40-0.53
|
||||
C2 input 0.44-0.49
|
||||
Cell AOI22x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!B1)+(!A1*!B2))+(!A2*!B1))+(!A2*!B2)
|
||||
A1 input 0.87-1.20
|
||||
A2 input 0.78-1.33
|
||||
B1 input 0.98-1.10
|
||||
B2 input 0.90-1.25
|
||||
Cell AOI22xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!B1)+(!A1*!B2))+(!A2*!B1))+(!A2*!B2)
|
||||
A1 input 0.37-0.41
|
||||
A2 input 0.32-0.44
|
||||
B1 input 0.32-0.44
|
||||
B2 input 0.28-0.47
|
||||
Cell AOI22xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!B1)+(!A1*!B2))+(!A2*!B1))+(!A2*!B2)
|
||||
A1 input 0.51-0.57
|
||||
A2 input 0.44-0.62
|
||||
B1 input 0.44-0.61
|
||||
B2 input 0.38-0.65
|
||||
Cell AOI311xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!B)*!C)+((!A2*!B)*!C))+((!A3*!B)*!C)
|
||||
A1 input 0.43-0.62
|
||||
A2 input 0.45-0.54
|
||||
A3 input 0.51-0.57
|
||||
B input 0.42-0.54
|
||||
C input 0.32-0.57
|
||||
Cell AOI31xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!B)+(!A2*!B))+(!A3*!B)
|
||||
A1 input 0.37-0.55
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.43-0.48
|
||||
B input 0.32-0.51
|
||||
Cell AOI31xp67_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!B)+(!A2*!B))+(!A3*!B)
|
||||
A1 input 0.89-1.25
|
||||
A2 input 0.97-1.15
|
||||
A3 input 1.02-1.15
|
||||
B input 0.56-0.99
|
||||
Cell AOI321xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((!A1*!B1)*!C)+((!A1*!B2)*!C))+((!A2*!B1)*!C))+((!A2*!B2)*!C))+((!A3*!B1)*!C))+((!A3*!B2)*!C)
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.45-0.54
|
||||
A3 input 0.51-0.57
|
||||
B1 input 0.37-0.53
|
||||
B2 input 0.33-0.56
|
||||
C input 0.44-0.58
|
||||
Cell AOI322xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((((((!A1*!B1)*!C1)+((!A1*!B1)*!C2))+((!A1*!B2)*!C1))+((!A1*!B2)*!C2))+((!A2*!B1)*!C1))+((!A2*!B1)*!C2))+((!A2*!B2)*!C1))+((!A2*!B2)*!C2))+((!A3*!B1)*!C1))+((!A3*!B1)*!C2))+((!A3*!B2)*!C1))+((!A3*!B2)*!C2)
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.44-0.54
|
||||
A3 input 0.46-0.56
|
||||
B1 input 0.42-0.56
|
||||
B2 input 0.44-0.49
|
||||
C1 input 0.34-0.57
|
||||
C2 input 0.39-0.56
|
||||
Cell AOI32xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((!A1*!B1)+(!A1*!B2))+(!A2*!B1))+(!A2*!B2))+(!A3*!B1))+(!A3*!B2)
|
||||
A1 input 0.37-0.55
|
||||
A2 input 0.40-0.48
|
||||
A3 input 0.45-0.51
|
||||
B1 input 0.33-0.45
|
||||
B2 input 0.29-0.47
|
||||
Cell AOI331xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((((((!A1*!B1)*!C1)+((!A1*!B2)*!C1))+((!A1*!B3)*!C1))+((!A2*!B1)*!C1))+((!A2*!B2)*!C1))+((!A2*!B3)*!C1))+((!A3*!B1)*!C1))+((!A3*!B2)*!C1))+((!A3*!B3)*!C1)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.56
|
||||
B1 input 0.42-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.47-0.56
|
||||
C1 input 0.41-0.67
|
||||
Cell AOI332xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((((((((((((!A1*!B1)*!C1)+((!A1*!B1)*!C2))+((!A1*!B2)*!C1))+((!A1*!B2)*!C2))+((!A1*!B3)*!C1))+((!A1*!B3)*!C2))+((!A2*!B1)*!C1))+((!A2*!B1)*!C2))+((!A2*!B2)*!C1))+((!A2*!B2)*!C2))+((!A2*!B3)*!C1))+((!A2*!B3)*!C2))+((!A3*!B1)*!C1))+((!A3*!B1)*!C2))+((!A3*!B2)*!C1))+((!A3*!B2)*!C2))+((!A3*!B3)*!C1))+((!A3*!B3)*!C2)
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.46-0.54
|
||||
A3 input 0.50-0.56
|
||||
B1 input 0.42-0.61
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.39-0.65
|
||||
C2 input 0.43-0.61
|
||||
Cell AOI333xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((((((((((((((((((((((((!A1*!B1)*!C1)+((!A1*!B1)*!C2))+((!A1*!B1)*!C3))+((!A1*!B2)*!C1))+((!A1*!B2)*!C2))+((!A1*!B2)*!C3))+((!A1*!B3)*!C1))+((!A1*!B3)*!C2))+((!A1*!B3)*!C3))+((!A2*!B1)*!C1))+((!A2*!B1)*!C2))+((!A2*!B1)*!C3))+((!A2*!B2)*!C1))+((!A2*!B2)*!C2))+((!A2*!B2)*!C3))+((!A2*!B3)*!C1))+((!A2*!B3)*!C2))+((!A2*!B3)*!C3))+((!A3*!B1)*!C1))+((!A3*!B1)*!C2))+((!A3*!B1)*!C3))+((!A3*!B2)*!C1))+((!A3*!B2)*!C2))+((!A3*!B2)*!C3))+((!A3*!B3)*!C1))+((!A3*!B3)*!C2))+((!A3*!B3)*!C3)
|
||||
A1 input 0.38-0.65
|
||||
A2 input 0.41-0.59
|
||||
A3 input 0.43-0.61
|
||||
B1 input 0.42-0.61
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.42-0.61
|
||||
C2 input 0.46-0.54
|
||||
C3 input 0.50-0.56
|
||||
Cell AOI33xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_AO_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((!A1*!B1)+(!A1*!B2))+(!A1*!B3))+(!A2*!B1))+(!A2*!B2))+(!A2*!B3))+(!A3*!B1))+(!A3*!B2))+(!A3*!B3)
|
||||
A1 input 0.43-0.48
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.36-0.53
|
||||
B1 input 0.34-0.56
|
||||
B2 input 0.37-0.50
|
||||
B3 input 0.39-0.52
|
||||
Cell OA211x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*B)*C)+((A2*B)*C)
|
||||
A1 input 0.37-0.54
|
||||
A2 input 0.34-0.57
|
||||
B input 0.34-0.44
|
||||
C input 0.37-0.45
|
||||
Cell OA21x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(A1*B)+(A2*B)
|
||||
A1 input 0.46-0.62
|
||||
A2 input 0.38-0.65
|
||||
B input 0.50-0.64
|
||||
Cell OA221x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((A1*B1)*C)+((A1*B2)*C))+((A2*B1)*C))+((A2*B2)*C)
|
||||
A1 input 0.85-0.96
|
||||
A2 input 0.78-1.03
|
||||
B1 input 0.79-0.94
|
||||
B2 input 0.76-1.01
|
||||
C input 0.53-0.99
|
||||
Cell OA222x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((A1*B1)*C1)+((A1*B1)*C2))+((A1*B2)*C1))+((A1*B2)*C2))+((A2*B1)*C1))+((A2*B1)*C2))+((A2*B2)*C1))+((A2*B2)*C2)
|
||||
A1 input 0.38-0.65
|
||||
A2 input 0.44-0.61
|
||||
B1 input 0.44-0.61
|
||||
B2 input 0.46-0.56
|
||||
C1 input 0.45-0.61
|
||||
C2 input 0.50-0.58
|
||||
Cell OA22x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((A1*B1)+(A1*B2))+(A2*B1))+(A2*B2)
|
||||
A1 input 0.44-0.61
|
||||
A2 input 0.39-0.65
|
||||
B1 input 0.50-0.56
|
||||
B2 input 0.46-0.62
|
||||
Cell OA31x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((A1*B1)+(A2*B1))+(A3*B1)
|
||||
A1 input 0.79-0.98
|
||||
A2 input 0.71-0.98
|
||||
A3 input 0.71-1.16
|
||||
B1 input 0.44-0.56
|
||||
Cell OA331x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((((((A1*B1)*C1)+((A1*B2)*C1))+((A1*B3)*C1))+((A2*B1)*C1))+((A2*B2)*C1))+((A2*B3)*C1))+((A3*B1)*C1))+((A3*B2)*C1))+((A3*B3)*C1)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.45-0.54
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.47-0.56
|
||||
C1 input 0.41-0.67
|
||||
Cell OA331x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((((((A1*B1)*C1)+((A1*B2)*C1))+((A1*B3)*C1))+((A2*B1)*C1))+((A2*B2)*C1))+((A2*B3)*C1))+((A3*B1)*C1))+((A3*B2)*C1))+((A3*B3)*C1)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.45-0.54
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.47-0.56
|
||||
C1 input 0.41-0.67
|
||||
Cell OA332x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((((((((((((A1*B1)*C1)+((A1*B1)*C2))+((A1*B2)*C1))+((A1*B2)*C2))+((A1*B3)*C1))+((A1*B3)*C2))+((A2*B1)*C1))+((A2*B1)*C2))+((A2*B2)*C1))+((A2*B2)*C2))+((A2*B3)*C1))+((A2*B3)*C2))+((A3*B1)*C1))+((A3*B1)*C2))+((A3*B2)*C1))+((A3*B2)*C2))+((A3*B3)*C1))+((A3*B3)*C2)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.38-0.65
|
||||
C2 input 0.44-0.61
|
||||
Cell OA332x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((((((((((((A1*B1)*C1)+((A1*B1)*C2))+((A1*B2)*C1))+((A1*B2)*C2))+((A1*B3)*C1))+((A1*B3)*C2))+((A2*B1)*C1))+((A2*B1)*C2))+((A2*B2)*C1))+((A2*B2)*C2))+((A2*B3)*C1))+((A2*B3)*C2))+((A3*B1)*C1))+((A3*B1)*C2))+((A3*B2)*C1))+((A3*B2)*C2))+((A3*B3)*C1))+((A3*B3)*C2)
|
||||
A1 input 0.43-0.61
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.50-0.57
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.38-0.65
|
||||
C2 input 0.44-0.61
|
||||
Cell OA333x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((((((((((((((((((((((((A1*B1)*C1)+((A1*B1)*C2))+((A1*B1)*C3))+((A1*B2)*C1))+((A1*B2)*C2))+((A1*B2)*C3))+((A1*B3)*C1))+((A1*B3)*C2))+((A1*B3)*C3))+((A2*B1)*C1))+((A2*B1)*C2))+((A2*B1)*C3))+((A2*B2)*C1))+((A2*B2)*C2))+((A2*B2)*C3))+((A2*B3)*C1))+((A2*B3)*C2))+((A2*B3)*C3))+((A3*B1)*C1))+((A3*B1)*C2))+((A3*B1)*C3))+((A3*B2)*C1))+((A3*B2)*C2))+((A3*B2)*C3))+((A3*B3)*C1))+((A3*B3)*C2))+((A3*B3)*C3)
|
||||
A1 input 0.38-0.65
|
||||
A2 input 0.37-0.59
|
||||
A3 input 0.44-0.61
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.44-0.55
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.43-0.61
|
||||
C2 input 0.46-0.55
|
||||
C3 input 0.50-0.57
|
||||
Cell OA333x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((((((((((((((((((((((((((A1*B1)*C1)+((A1*B1)*C2))+((A1*B1)*C3))+((A1*B2)*C1))+((A1*B2)*C2))+((A1*B2)*C3))+((A1*B3)*C1))+((A1*B3)*C2))+((A1*B3)*C3))+((A2*B1)*C1))+((A2*B1)*C2))+((A2*B1)*C3))+((A2*B2)*C1))+((A2*B2)*C2))+((A2*B2)*C3))+((A2*B3)*C1))+((A2*B3)*C2))+((A2*B3)*C3))+((A3*B1)*C1))+((A3*B1)*C2))+((A3*B1)*C3))+((A3*B2)*C1))+((A3*B2)*C2))+((A3*B2)*C3))+((A3*B3)*C1))+((A3*B3)*C2))+((A3*B3)*C3)
|
||||
A1 input 0.39-0.65
|
||||
A2 input 0.37-0.59
|
||||
A3 input 0.44-0.61
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.43-0.61
|
||||
C2 input 0.46-0.55
|
||||
C3 input 0.50-0.57
|
||||
Cell OA33x2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((((((((A1*B1)+(A1*B2))+(A1*B3))+(A2*B1))+(A2*B2))+(A2*B3))+(A3*B1))+(A3*B2))+(A3*B3)
|
||||
A1 input 0.50-0.58
|
||||
A2 input 0.46-0.55
|
||||
A3 input 0.43-0.61
|
||||
B1 input 0.45-0.61
|
||||
B2 input 0.37-0.59
|
||||
B3 input 0.39-0.65
|
||||
Cell OAI211xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)+!B)+!C
|
||||
A1 input 0.36-0.54
|
||||
A2 input 0.34-0.57
|
||||
B input 0.39-0.52
|
||||
C input 0.41-0.52
|
||||
Cell OAI21x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!A2)+!B
|
||||
A1 input 0.89-1.24
|
||||
A2 input 0.95-1.08
|
||||
B input 0.85-1.38
|
||||
Cell OAI21xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!A2)+!B
|
||||
A1 input 0.33-0.44
|
||||
A2 input 0.28-0.47
|
||||
B input 0.36-0.46
|
||||
Cell OAI21xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!A2)+!B
|
||||
A1 input 0.45-0.62
|
||||
A2 input 0.38-0.65
|
||||
B input 0.49-0.62
|
||||
Cell OAI221xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)+(!B1*!B2))+!C
|
||||
A1 input 0.40-0.52
|
||||
A2 input 0.43-0.49
|
||||
B1 input 0.33-0.57
|
||||
B2 input 0.36-0.54
|
||||
C input 0.41-0.53
|
||||
Cell OAI222xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)+(!B1*!B2))+(!C1*!C2)
|
||||
A1 input 0.38-0.65
|
||||
A2 input 0.43-0.61
|
||||
B1 input 0.43-0.61
|
||||
B2 input 0.46-0.56
|
||||
C1 input 0.44-0.61
|
||||
C2 input 0.50-0.57
|
||||
Cell OAI22x1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!A2)+(!B1*!B2)
|
||||
A1 input 0.86-1.20
|
||||
A2 input 0.79-1.34
|
||||
B1 input 0.97-1.10
|
||||
B2 input 0.90-1.25
|
||||
Cell OAI22xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!A2)+(!B1*!B2)
|
||||
A1 input 0.34-0.47
|
||||
A2 input 0.30-0.49
|
||||
B1 input 0.38-0.42
|
||||
B2 input 0.34-0.46
|
||||
Cell OAI22xp5_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(!A1*!A2)+(!B1*!B2)
|
||||
A1 input 0.44-0.61
|
||||
A2 input 0.38-0.65
|
||||
B1 input 0.50-0.57
|
||||
B2 input 0.44-0.61
|
||||
Cell OAI311xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!A2)*!A3)+!B1)+!C1
|
||||
A1 input 0.43-0.62
|
||||
A2 input 0.45-0.54
|
||||
A3 input 0.51-0.57
|
||||
B1 input 0.41-0.54
|
||||
C1 input 0.32-0.56
|
||||
Cell OAI31xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)*!A3)+!B
|
||||
A1 input 0.38-0.55
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.43-0.49
|
||||
B input 0.32-0.51
|
||||
Cell OAI31xp67_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)*!A3)+!B
|
||||
A1 input 0.87-1.24
|
||||
A2 input 0.96-1.14
|
||||
A3 input 1.01-1.14
|
||||
B input 0.54-0.98
|
||||
Cell OAI321xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!A2)*!A3)+(!B1*!B2))+!C
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.45-0.54
|
||||
A3 input 0.51-0.57
|
||||
B1 input 0.36-0.53
|
||||
B2 input 0.34-0.56
|
||||
C input 0.44-0.58
|
||||
Cell OAI322xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!A2)*!A3)+(!B1*!B2))+(!C1*!C2)
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.44-0.54
|
||||
A3 input 0.46-0.56
|
||||
B1 input 0.42-0.56
|
||||
B2 input 0.43-0.49
|
||||
C1 input 0.34-0.57
|
||||
C2 input 0.39-0.56
|
||||
Cell OAI32xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)*!A3)+(!B1*!B2)
|
||||
A1 input 0.36-0.53
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.45-0.51
|
||||
B1 input 0.33-0.45
|
||||
B2 input 0.29-0.47
|
||||
Cell OAI331xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!A2)*!A3)+((!B1*!B2)*!B3))+!C1
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.46-0.54
|
||||
A3 input 0.50-0.56
|
||||
B1 input 0.42-0.61
|
||||
B2 input 0.45-0.54
|
||||
B3 input 0.47-0.56
|
||||
C1 input 0.41-0.67
|
||||
Cell OAI332xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!A2)*!A3)+((!B1*!B2)*!B3))+(!C1*!C2)
|
||||
A1 input 0.42-0.61
|
||||
A2 input 0.46-0.54
|
||||
A3 input 0.50-0.56
|
||||
B1 input 0.42-0.61
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.38-0.65
|
||||
C2 input 0.43-0.61
|
||||
Cell OAI333xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=(((!A1*!A2)*!A3)+((!B1*!B2)*!B3))+((!C1*!C2)*!C3)
|
||||
A1 input 0.38-0.65
|
||||
A2 input 0.37-0.59
|
||||
A3 input 0.42-0.61
|
||||
B1 input 0.42-0.61
|
||||
B2 input 0.44-0.54
|
||||
B3 input 0.46-0.56
|
||||
C1 input 0.42-0.61
|
||||
C2 input 0.46-0.54
|
||||
C3 input 0.50-0.56
|
||||
Cell OAI33xp33_ASAP7_75t_R
|
||||
Library asap7sc7p5t_OA_RVT_FF_nldm_211120
|
||||
File ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
VDD power
|
||||
VSS ground
|
||||
Y output function=((!A1*!A2)*!A3)+((!B1*!B2)*!B3)
|
||||
A1 input 0.43-0.48
|
||||
A2 input 0.39-0.47
|
||||
A3 input 0.36-0.53
|
||||
B1 input 0.34-0.56
|
||||
B2 input 0.33-0.50
|
||||
B3 input 0.39-0.52
|
||||
Cell sg13g2_ebufn_2
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Z tristate enable=!TE_B function=A 4.51-7.42
|
||||
A input 2.58-2.66
|
||||
TE_B input 6.21-6.60
|
||||
Cell sg13g2_sdfbbp_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Q output function=IQ
|
||||
Q_N output function=IQN
|
||||
CLK input 2.97-3.06
|
||||
D input 1.95-2.01
|
||||
RESET_B input 1.74
|
||||
SCD input 1.96-2.00
|
||||
SCE input 3.18-3.92
|
||||
SET_B input 5.25
|
||||
IQ internal
|
||||
IQN internal
|
||||
Cell sg13g2_dlhq_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Q output function=IQ
|
||||
D input 2.26-2.31
|
||||
GATE input 1.69-2.58
|
||||
IQ internal
|
||||
IQN internal
|
||||
Cell sg13g2_mux2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
X output function=(!S*A0)+(S*A1)
|
||||
A0 input 0.38-3.63
|
||||
A1 input 0.52-3.70
|
||||
S input 5.00-5.09
|
||||
Warning: ../../test/liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
|
||||
Warning: ../../test/liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
# Test CCSN (current source) models and various timing model types.
|
||||
# Targets:
|
||||
# LibertyReader.cc: beginCcs/endCcs, receiver_capacitance groups,
|
||||
# timing_type combinations,
|
||||
# beginOutputCurrentRise/Fall, visitReceiverCapacitance,
|
||||
# polynomial model visitors, ccsn noise model visitors,
|
||||
# leakage_power groups, internal_power groups,
|
||||
# max_capacitance/max_transition on pins, min_pulse_width
|
||||
# TableModel.cc: different table axis variables, GateTableModel,
|
||||
# CheckTableModel, 3D tables, receiver model tables
|
||||
# TimingArc.cc: timing arc type queries (removal, recovery,
|
||||
# three_state_enable, rising_edge, min_pulse_width)
|
||||
# Liberty.cc: timing arc set queries, hasTimingArcs, timingArcSets
|
||||
source ../../test/helpers.tcl
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 CCSN library (CCS models with receiver_capacitance)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
|
||||
# Report cells from CCSN library to exercise CCS model paths
|
||||
set ccsn_cells [get_lib_cells */*]
|
||||
|
||||
foreach cell_obj $ccsn_cells {
|
||||
report_lib_cell [get_full_name $cell_obj]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ library (has setup/hold/recovery/removal arcs)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
||||
# Report sequential cells which have diverse timing_type values
|
||||
# DFF cells have setup, hold timing checks
|
||||
set lib_seq [sta::find_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
set seq_cells [$lib_seq find_liberty_cells_matching "DFF*" 0 0]
|
||||
|
||||
# Report specific cells to exercise different timing types
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx2_ASAP7_75t_R
|
||||
|
||||
# Scan DFF cells (scan_in, scan_enable timing arcs)
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R
|
||||
|
||||
# ICG cells (clock gating - exercises clock gate timing types)
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
|
||||
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx2_ASAP7_75t_R
|
||||
|
||||
# Async set/reset cells (recovery/removal timing types)
|
||||
set async_cells [$lib_seq find_liberty_cells_matching "*ASYNC*" 0 0]
|
||||
|
||||
# DFFR cells with reset (recovery/removal)
|
||||
set dffr_cells [$lib_seq find_liberty_cells_matching "DFFR*" 0 0]
|
||||
foreach cell_obj $dffr_cells {
|
||||
report_lib_cell [get_name $cell_obj]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ SS corner for different model values
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SIMPLE library (combinational cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set simple_lib [sta::find_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120]
|
||||
set simple_cells [$simple_lib find_liberty_cells_matching "*" 0 0]
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 AO library (AND-OR complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set ao_lib [sta::find_liberty asap7sc7p5t_AO_RVT_FF_nldm_211120]
|
||||
set ao_cells [$ao_lib find_liberty_cells_matching "AO*" 0 0]
|
||||
foreach c $ao_cells {
|
||||
report_lib_cell [get_name $c]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 OA library (OR-AND complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
|
||||
set oa_lib [sta::find_liberty asap7sc7p5t_OA_RVT_FF_nldm_211120]
|
||||
set oa_cells [$oa_lib find_liberty_cells_matching "OA*" 0 0]
|
||||
foreach c $oa_cells {
|
||||
report_lib_cell [get_name $c]
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF library
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
|
||||
############################################################
|
||||
# Read libraries from different process nodes
|
||||
# Exercises different liberty features/syntax in each library
|
||||
############################################################
|
||||
|
||||
# Read IHP SG13G2 library (has tristate, scan, different timing types)
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
||||
set ihp_lib [sta::find_liberty sg13g2_stdcell_typ_1p20V_25C]
|
||||
# Report tristate buffer cell (exercises three_state_enable paths)
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2
|
||||
|
||||
# Report scan flip-flop (exercises scan timing paths)
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1
|
||||
|
||||
# Report latch cell
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1
|
||||
|
||||
# MUX cell
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1
|
||||
|
||||
# Read IHP second PVT corner
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
|
||||
|
||||
############################################################
|
||||
# Read latch library to exercise latch-specific code
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_latch3.lib
|
||||
|
||||
############################################################
|
||||
# Read liberty with backslash-EOL continuation
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_backslash_eol.lib
|
||||
|
||||
############################################################
|
||||
# Read liberty with float-as-string values
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_float_as_str.lib
|
||||
|
||||
############################################################
|
||||
# Read liberty arcs one2one libraries
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_arcs_one2one_1.lib
|
||||
|
||||
read_liberty ../../test/liberty_arcs_one2one_2.lib
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro library (exercises macro/memory cells)
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ LVT/SLVT (different threshold voltages)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF different Vt flavors
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
|
||||
|
||||
############################################################
|
||||
# Write liberty for ASAP7 SEQ
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_ccsn_write.lib]
|
||||
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile
|
||||
|
||||
set outfile2 [make_result_file liberty_ccsn_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2
|
||||
|
|
@ -1,5 +1,3 @@
|
|||
PASS: read ASAP7 CCSN library
|
||||
PASS: CCSN lib cells total: 1
|
||||
Cell A2O1A1Ixp33_ASAP7_75t_L
|
||||
Library asap7sc7p5t_AO_LVT_FF_ccsn_211120
|
||||
File ../../test/asap7_ccsn.lib.gz
|
||||
|
|
@ -10,9 +8,6 @@ File ../../test/asap7_ccsn.lib.gz
|
|||
A2 input 0.53-0.63
|
||||
B input 0.47-0.66
|
||||
C input 0.36-0.63
|
||||
PASS: reported all CCSN cells
|
||||
PASS: read ASAP7 SEQ RVT FF
|
||||
PASS: ASAP7 DFF* cells: 9
|
||||
Cell DFFHQNx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
|
@ -23,7 +18,6 @@ File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
|||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
PASS: ASAP7 DFF cell report
|
||||
Cell DFFHQNx2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
|
@ -34,11 +28,8 @@ File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
|||
D input 0.55-0.62
|
||||
IQN internal
|
||||
IQNN internal
|
||||
PASS: ASAP7 DFF x2 cell report
|
||||
Warning: liberty_ccsn_ecsm.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R' not found.
|
||||
PASS: ASAP7 SDFF cell report
|
||||
Warning: liberty_ccsn_ecsm.tcl line 1, liberty cell 'asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R' not found.
|
||||
PASS: ASAP7 SDFF x2 cell report
|
||||
Cell ICGx1_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
|
@ -49,7 +40,6 @@ File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
|||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
PASS: ASAP7 ICG cell report
|
||||
Cell ICGx2_ASAP7_75t_R
|
||||
Library asap7sc7p5t_SEQ_RVT_FF_nldm_220123
|
||||
File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
|
|
@ -60,10 +50,6 @@ File ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
|||
CLK input 1.63-2.39
|
||||
ENA input 0.33-0.47
|
||||
SE input 0.39-0.47
|
||||
PASS: ASAP7 ICG x2 cell report
|
||||
PASS: ASAP7 ASYNC cells: 0
|
||||
PASS: ASAP7 DFFR cells reported
|
||||
PASS: read ASAP7 SEQ SS
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13178, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13211, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 13244, timing group from output port.
|
||||
|
|
@ -74,21 +60,12 @@ Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 1337
|
|||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14772, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14805, timing group from output port.
|
||||
Warning: ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz line 14838, timing group from output port.
|
||||
PASS: read ASAP7 SIMPLE
|
||||
PASS: ASAP7 SIMPLE cells: 56
|
||||
PASS: read ASAP7 AO
|
||||
PASS: ASAP7 AO* cells: 40
|
||||
PASS: read ASAP7 OA
|
||||
PASS: ASAP7 OA* cells: 32
|
||||
PASS: read ASAP7 INVBUF
|
||||
PASS: read IHP sg13g2
|
||||
Cell sg13g2_ebufn_2
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
Z tristate enable=!TE_B function=A 4.51-7.42
|
||||
A input 2.58-2.66
|
||||
TE_B input 6.21-6.60
|
||||
PASS: IHP tristate buffer report
|
||||
Cell sg13g2_sdfbbp_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
|
@ -102,7 +79,6 @@ File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
|||
SET_B input 5.25
|
||||
IQ internal
|
||||
IQN internal
|
||||
PASS: IHP scan DFF report
|
||||
Cell sg13g2_dlhq_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
|
@ -111,7 +87,6 @@ File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
|||
GATE input 1.69-2.58
|
||||
IQ internal
|
||||
IQN internal
|
||||
PASS: IHP latch report
|
||||
Cell sg13g2_mux2_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
|
@ -119,20 +94,5 @@ File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
|||
A0 input 0.38-3.63
|
||||
A1 input 0.52-3.70
|
||||
S input 5.00-5.09
|
||||
PASS: IHP mux report
|
||||
PASS: read IHP 1.5V
|
||||
PASS: read latch3 library
|
||||
PASS: read backslash_eol library
|
||||
PASS: read float_as_str library
|
||||
Warning: ../../test/liberty_arcs_one2one_1.lib line 48, timing port A and related port Y are different sizes.
|
||||
PASS: read arcs_one2one_1 library
|
||||
Warning: ../../test/liberty_arcs_one2one_2.lib line 48, timing port A and related port Y are different sizes.
|
||||
PASS: read arcs_one2one_2 library
|
||||
PASS: read gf180mcu SRAM library
|
||||
PASS: read ASAP7 SEQ LVT
|
||||
PASS: read ASAP7 SEQ SLVT
|
||||
PASS: read ASAP7 INVBUF LVT
|
||||
PASS: read ASAP7 INVBUF SLVT
|
||||
PASS: write_liberty ASAP7 SEQ
|
||||
PASS: write_liberty IHP
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -17,70 +17,58 @@ source ../../test/helpers.tcl
|
|||
# Read ASAP7 CCSN library (CCS models with receiver_capacitance)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7_ccsn.lib.gz
|
||||
puts "PASS: read ASAP7 CCSN library"
|
||||
|
||||
# Report cells from CCSN library to exercise CCS model paths
|
||||
set ccsn_cells [get_lib_cells */*]
|
||||
puts "PASS: CCSN lib cells total: [llength $ccsn_cells]"
|
||||
|
||||
foreach cell_obj $ccsn_cells {
|
||||
catch {
|
||||
report_lib_cell [get_full_name $cell_obj]
|
||||
}
|
||||
}
|
||||
puts "PASS: reported all CCSN cells"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ library (has setup/hold/recovery/removal arcs)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ RVT FF"
|
||||
|
||||
# Report sequential cells which have diverse timing_type values
|
||||
# DFF cells have setup, hold timing checks
|
||||
set lib_seq [sta::find_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123]
|
||||
catch {
|
||||
set seq_cells [$lib_seq find_liberty_cells_matching "DFF*" 0 0]
|
||||
puts "PASS: ASAP7 DFF* cells: [llength $seq_cells]"
|
||||
}
|
||||
|
||||
# Report specific cells to exercise different timing types
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx1_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 DFF cell report"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/DFFHQNx2_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 DFF x2 cell report"
|
||||
}
|
||||
|
||||
# Scan DFF cells (scan_in, scan_enable timing arcs)
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx1_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 SDFF cell report"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/SDFHQNx2_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 SDFF x2 cell report"
|
||||
}
|
||||
|
||||
# ICG cells (clock gating - exercises clock gate timing types)
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx1_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 ICG cell report"
|
||||
}
|
||||
|
||||
catch {
|
||||
report_lib_cell asap7sc7p5t_SEQ_RVT_FF_nldm_220123/ICGx2_ASAP7_75t_R
|
||||
puts "PASS: ASAP7 ICG x2 cell report"
|
||||
}
|
||||
|
||||
# Async set/reset cells (recovery/removal timing types)
|
||||
catch {
|
||||
set async_cells [$lib_seq find_liberty_cells_matching "*ASYNC*" 0 0]
|
||||
puts "PASS: ASAP7 ASYNC cells: [llength $async_cells]"
|
||||
}
|
||||
|
||||
# DFFR cells with reset (recovery/removal)
|
||||
|
|
@ -89,37 +77,31 @@ catch {
|
|||
foreach cell_obj $dffr_cells {
|
||||
report_lib_cell [get_object_name $cell_obj]
|
||||
}
|
||||
puts "PASS: ASAP7 DFFR cells reported"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ SS corner for different model values
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ SS"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SIMPLE library (combinational cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
|
||||
puts "PASS: read ASAP7 SIMPLE"
|
||||
|
||||
catch {
|
||||
set simple_lib [sta::find_liberty asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120]
|
||||
set simple_cells [$simple_lib find_liberty_cells_matching "*" 0 0]
|
||||
puts "PASS: ASAP7 SIMPLE cells: [llength $simple_cells]"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 AO library (AND-OR complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
|
||||
puts "PASS: read ASAP7 AO"
|
||||
|
||||
catch {
|
||||
set ao_lib [sta::find_liberty asap7sc7p5t_AO_RVT_FF_nldm_211120]
|
||||
set ao_cells [$ao_lib find_liberty_cells_matching "AO*" 0 0]
|
||||
puts "PASS: ASAP7 AO* cells: [llength $ao_cells]"
|
||||
foreach c $ao_cells {
|
||||
catch {report_lib_cell [get_object_name $c]}
|
||||
}
|
||||
|
|
@ -129,12 +111,10 @@ catch {
|
|||
# Read ASAP7 OA library (OR-AND complex cells)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
|
||||
puts "PASS: read ASAP7 OA"
|
||||
|
||||
catch {
|
||||
set oa_lib [sta::find_liberty asap7sc7p5t_OA_RVT_FF_nldm_211120]
|
||||
set oa_cells [$oa_lib find_liberty_cells_matching "OA*" 0 0]
|
||||
puts "PASS: ASAP7 OA* cells: [llength $oa_cells]"
|
||||
foreach c $oa_cells {
|
||||
catch {report_lib_cell [get_object_name $c]}
|
||||
}
|
||||
|
|
@ -144,7 +124,6 @@ catch {
|
|||
# Read ASAP7 INVBUF library
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF"
|
||||
|
||||
############################################################
|
||||
# Read libraries from different process nodes
|
||||
|
|
@ -153,91 +132,71 @@ puts "PASS: read ASAP7 INVBUF"
|
|||
|
||||
# Read IHP SG13G2 library (has tristate, scan, different timing types)
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP sg13g2"
|
||||
|
||||
catch {
|
||||
set ihp_lib [sta::find_liberty sg13g2_stdcell_typ_1p20V_25C]
|
||||
# Report tristate buffer cell (exercises three_state_enable paths)
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2}
|
||||
puts "PASS: IHP tristate buffer report"
|
||||
|
||||
# Report scan flip-flop (exercises scan timing paths)
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_sdfbbp_1}
|
||||
puts "PASS: IHP scan DFF report"
|
||||
|
||||
# Report latch cell
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dlhq_1}
|
||||
puts "PASS: IHP latch report"
|
||||
|
||||
# MUX cell
|
||||
catch {report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1}
|
||||
puts "PASS: IHP mux report"
|
||||
}
|
||||
|
||||
# Read IHP second PVT corner
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p50V_25C.lib
|
||||
puts "PASS: read IHP 1.5V"
|
||||
|
||||
############################################################
|
||||
# Read latch library to exercise latch-specific code
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_latch3.lib
|
||||
puts "PASS: read latch3 library"
|
||||
|
||||
############################################################
|
||||
# Read liberty with backslash-EOL continuation
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_backslash_eol.lib
|
||||
puts "PASS: read backslash_eol library"
|
||||
|
||||
############################################################
|
||||
# Read liberty with float-as-string values
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_float_as_str.lib
|
||||
puts "PASS: read float_as_str library"
|
||||
|
||||
############################################################
|
||||
# Read liberty arcs one2one libraries
|
||||
############################################################
|
||||
read_liberty ../../test/liberty_arcs_one2one_1.lib
|
||||
puts "PASS: read arcs_one2one_1 library"
|
||||
|
||||
read_liberty ../../test/liberty_arcs_one2one_2.lib
|
||||
puts "PASS: read arcs_one2one_2 library"
|
||||
|
||||
############################################################
|
||||
# Read SRAM macro library (exercises macro/memory cells)
|
||||
############################################################
|
||||
read_liberty ../../test/gf180mcu_sram.lib.gz
|
||||
puts "PASS: read gf180mcu SRAM library"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ LVT/SLVT (different threshold voltages)
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ LVT"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ SLVT"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 INVBUF different Vt flavors
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF LVT"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF SLVT"
|
||||
|
||||
############################################################
|
||||
# Write liberty for ASAP7 SEQ
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_ccsn_ecsm_write.lib]
|
||||
sta::write_liberty asap7sc7p5t_SEQ_RVT_FF_nldm_220123 $outfile
|
||||
puts "PASS: write_liberty ASAP7 SEQ"
|
||||
|
||||
set outfile2 [make_result_file liberty_ccsn_ecsm_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2
|
||||
puts "PASS: write_liberty IHP"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,3 @@
|
|||
PASS: read sky130hd
|
||||
PASS: read Nangate45
|
||||
PASS: read ASAP7 SEQ
|
||||
PASS: read IHP
|
||||
--- Nangate45 cell classification ---
|
||||
BUF_X1 is_buffer = 1
|
||||
BUF_X1 is_inverter = 0
|
||||
|
|
@ -14,7 +10,6 @@ DFF_X1 is_buffer = 0
|
|||
DFF_X1 is_inverter = 0
|
||||
DFF_X1 is_leaf = 1
|
||||
SDFF_X1 test_cell = NULL
|
||||
PASS: Nangate45 classification
|
||||
--- port function queries ---
|
||||
INV_X1/ZN func=!A dir=output
|
||||
BUF_X1/Z func=A dir=output
|
||||
|
|
@ -31,11 +26,8 @@ PASS: Nangate45 classification
|
|||
HA_X1/S func=A^B dir=output
|
||||
FA_X1/CO func=(A*B)+(CI*(A+B)) dir=output
|
||||
FA_X1/S func=CI^(A^B) dir=output
|
||||
PASS: port function queries
|
||||
--- bus port member iteration ---
|
||||
PASS: bus port member iteration
|
||||
--- port capacitance corner ---
|
||||
PASS: port capacitance corner
|
||||
--- timing arc sets ---
|
||||
INV_X1 arc_sets=1
|
||||
A -> ZN is_check=0
|
||||
|
|
@ -195,7 +187,6 @@ CLKGATETST_X1 arc_sets=9
|
|||
fall -> fall
|
||||
CK -> GCK is_check=0
|
||||
fall -> fall
|
||||
PASS: timing arc sets
|
||||
--- Sky130 cell queries ---
|
||||
sky130_fd_sc_hd__inv_1 is_buffer=0 is_inverter=1
|
||||
VGND pwr_gnd=1
|
||||
|
|
@ -267,10 +258,8 @@ sky130_fd_sc_hd__ebufn_1 is_buffer=0 is_inverter=0
|
|||
VNB pwr_gnd=1
|
||||
VPB pwr_gnd=1
|
||||
VPWR pwr_gnd=1
|
||||
PASS: Sky130 cell queries
|
||||
--- operating conditions ---
|
||||
Sky130 default OC process=1.0 voltage=1.7999999523162842 temp=25.0
|
||||
PASS: operating conditions
|
||||
--- IHP cell queries ---
|
||||
sg13g2_inv_1 is_buffer=0 is_inverter=1
|
||||
arc_sets=1
|
||||
|
|
@ -292,11 +281,7 @@ sg13g2_dfrbp_2 is_buffer=0 is_inverter=0
|
|||
arc_sets=10
|
||||
sg13g2_ebufn_2 is_buffer=0 is_inverter=0
|
||||
arc_sets=3
|
||||
PASS: IHP cell queries
|
||||
--- ensure voltage waveforms ---
|
||||
PASS: INV_X1 ensure_voltage_waveforms
|
||||
PASS: DFF_X1 ensure_voltage_waveforms
|
||||
PASS: ensure voltage waveforms
|
||||
--- liberty cell matching ---
|
||||
INV_* matches = 6
|
||||
DFF* matches = 8
|
||||
|
|
@ -304,5 +289,3 @@ DFF* matches = 8
|
|||
regex INV_X matches = 6
|
||||
INV_X1 port * matches = 4
|
||||
INV_X1 port A matches = 1
|
||||
PASS: liberty cell matching
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -20,16 +20,12 @@ source ../../test/helpers.tcl
|
|||
# Read libraries with pg_pin info (Sky130 has pg_pin groups)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read sky130hd"
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ"
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP"
|
||||
|
||||
############################################################
|
||||
# Cell classification queries on Nangate45
|
||||
|
|
@ -67,8 +63,6 @@ catch {
|
|||
puts "SDFF_X1 test_cell = $tc"
|
||||
}
|
||||
|
||||
puts "PASS: Nangate45 classification"
|
||||
|
||||
############################################################
|
||||
# Port function queries (exercises FuncExpr::to_string)
|
||||
############################################################
|
||||
|
|
@ -105,7 +99,6 @@ foreach {lib_name cell_name} {
|
|||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: port function queries"
|
||||
|
||||
############################################################
|
||||
# Bus port and member iteration
|
||||
|
|
@ -136,7 +129,6 @@ foreach cell_obj $asap7_cells {
|
|||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: bus port member iteration"
|
||||
|
||||
############################################################
|
||||
# Port capacitance with corner/min_max
|
||||
|
|
@ -161,7 +153,6 @@ foreach cell_name {INV_X1 INV_X4 INV_X16 BUF_X1 BUF_X8 NAND2_X1 DFF_X1} {
|
|||
}
|
||||
$port_iter finish
|
||||
}
|
||||
puts "PASS: port capacitance corner"
|
||||
|
||||
############################################################
|
||||
# Timing arc set queries
|
||||
|
|
@ -188,7 +179,6 @@ foreach cell_name {INV_X1 BUF_X1 DFF_X1 DFFR_X1 NAND2_X1 AOI21_X1 MUX2_X1 SDFF_X
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: timing arc sets"
|
||||
|
||||
############################################################
|
||||
# Sky130 cell queries (has pg_pin groups, different features)
|
||||
|
|
@ -220,7 +210,6 @@ foreach cell_name {
|
|||
$port_iter finish
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 cell queries"
|
||||
|
||||
############################################################
|
||||
# Operating conditions (exercises find_operating_conditions)
|
||||
|
|
@ -231,7 +220,6 @@ set default_oc [$sky_lib default_operating_conditions]
|
|||
if {$default_oc != "NULL"} {
|
||||
puts "Sky130 default OC process=[$default_oc process] voltage=[$default_oc voltage] temp=[$default_oc temperature]"
|
||||
}
|
||||
puts "PASS: operating conditions"
|
||||
|
||||
############################################################
|
||||
# IHP cell queries (different vendor, might have different features)
|
||||
|
|
@ -252,7 +240,6 @@ foreach cell_name {
|
|||
puts " arc_sets=[llength $arc_sets]"
|
||||
}
|
||||
}
|
||||
puts "PASS: IHP cell queries"
|
||||
|
||||
############################################################
|
||||
# Ensure voltage waveforms (exercises ensureVoltageWaveforms)
|
||||
|
|
@ -261,15 +248,12 @@ puts "--- ensure voltage waveforms ---"
|
|||
catch {
|
||||
set inv [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
$inv ensure_voltage_waveforms
|
||||
puts "PASS: INV_X1 ensure_voltage_waveforms"
|
||||
}
|
||||
|
||||
catch {
|
||||
set dff [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
$dff ensure_voltage_waveforms
|
||||
puts "PASS: DFF_X1 ensure_voltage_waveforms"
|
||||
}
|
||||
puts "PASS: ensure voltage waveforms"
|
||||
|
||||
############################################################
|
||||
# Liberty cell matching with regex patterns
|
||||
|
|
@ -296,6 +280,3 @@ puts "INV_X1 port * matches = [llength $port_matches]"
|
|||
|
||||
set port_matches [$inv find_liberty_ports_matching "A" 0 0]
|
||||
puts "INV_X1 port A matches = [llength $port_matches]"
|
||||
puts "PASS: liberty cell matching"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,24 +1,15 @@
|
|||
PASS: read Nangate45
|
||||
PASS: read ASAP7 SEQ
|
||||
PASS: read IHP
|
||||
PASS: INV_X1/A capacitance = 1.700230
|
||||
PASS: INV_X1/ZN capacitance = 0.000000
|
||||
PASS: DFF_X1/CK capacitance = 0.949653
|
||||
PASS: DFF_X1/D capacitance = 1.140290
|
||||
INV_X1/A cap = 1.700230
|
||||
INV_X2/A cap = 3.250891
|
||||
INV_X4/A cap = 6.258425
|
||||
INV_X8/A cap = 11.810652
|
||||
INV_X16/A cap = 25.228138
|
||||
INV_X32/A cap = 49.191467
|
||||
PASS: INV capacitance sweep
|
||||
BUF_X1/A cap = 0.974659
|
||||
BUF_X2/A cap = 1.779209
|
||||
BUF_X4/A cap = 3.401892
|
||||
BUF_X8/A cap = 6.585178
|
||||
BUF_X16/A cap = 12.410827
|
||||
BUF_X32/A cap = 26.703922
|
||||
PASS: BUF capacitance sweep
|
||||
INV_X1 area = 0.532000
|
||||
INV_X2 area = 0.798000
|
||||
INV_X4 area = 1.330000
|
||||
|
|
@ -49,30 +40,19 @@ FA_X1 area = 4.256000
|
|||
HA_X1 area = 2.660000
|
||||
TINV_X1 area = 1.064000
|
||||
CLKGATETST_X1 area = 3.990000
|
||||
PASS: cell area queries
|
||||
INV_X1 dont_use = 0
|
||||
BUF_X1 dont_use = 0
|
||||
DFF_X1 dont_use = 0
|
||||
ANTENNA_X1 dont_use = 1
|
||||
FILLCELL_X1 dont_use = 1
|
||||
PASS: dont_use queries
|
||||
PASS: leakage power queries
|
||||
Warning: liberty_cell_deep.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
PASS: design with constraints
|
||||
No paths found.
|
||||
PASS: max path report
|
||||
No paths found.
|
||||
PASS: min path report
|
||||
No paths found.
|
||||
PASS: in2->out2 path
|
||||
No paths found.
|
||||
PASS: rise_from path
|
||||
No paths found.
|
||||
PASS: fall_from path
|
||||
No paths found.
|
||||
PASS: rise_to path
|
||||
No paths found.
|
||||
PASS: fall_to path
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
clk1 2.05
|
||||
|
|
@ -80,7 +60,6 @@ clk2 0.08
|
|||
clk1 6.92
|
||||
clk2 9.88
|
||||
|
||||
PASS: report_check_types max/min delay
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
|
|
@ -93,24 +72,19 @@ Pin Limit Cap Slack
|
|||
------------------------------------------------------------
|
||||
nor1/ZN 26.70 1.14 25.56 (MET)
|
||||
|
||||
PASS: report_check_types max_slew/cap/fanout
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
PASS: report_check_types recovery/removal
|
||||
Required Actual
|
||||
Pin Width Width Slack
|
||||
------------------------------------------------------------
|
||||
reg1/CK (high) 0.05 5.00 4.95 (MET)
|
||||
|
||||
PASS: report_check_types min_pulse_width/min_period
|
||||
Group Slack
|
||||
--------------------------------------------
|
||||
No paths found.
|
||||
|
||||
PASS: report_check_types clock_gating
|
||||
PASS: report_check_types max_skew
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
|
|
@ -122,7 +96,6 @@ Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
|||
----------------------------------------------------------------
|
||||
Total 1.90e-06 7.80e-08 3.61e-07 2.33e-06 100.0%
|
||||
81.2% 3.3% 15.5%
|
||||
PASS: report_power
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
|
|
@ -135,8 +108,6 @@ PASS: report_power
|
|||
2.33e-08 5.90e-09 1.44e-08 4.35e-08 inv1
|
||||
1.46e-08 6.90e-09 1.97e-08 4.11e-08 nor1
|
||||
1.24e-08 6.90e-09 2.18e-08 4.11e-08 nand1
|
||||
PASS: report_power instances
|
||||
PASS: read Sky130
|
||||
Cell sky130_fd_sc_hd__ebufn_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -167,7 +138,6 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
A input 2.37-2.60
|
||||
TE_B input 6.26-7.48
|
||||
Z tristate enable=!TE_B function=A 5.20
|
||||
PASS: Sky130 tristate cells
|
||||
Cell sky130_fd_sc_hd__dlxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -192,7 +162,6 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
D input 1.70-1.89
|
||||
GATE_N input 1.66-1.82
|
||||
Q output function=IQ
|
||||
PASS: Sky130 latch cells
|
||||
Cell sky130_fd_sc_hd__sdfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -222,7 +191,6 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
Q_N output function=IQ_N
|
||||
SCD input 1.72-1.90
|
||||
SCE input 3.17-3.56
|
||||
PASS: Sky130 scan DFF cells
|
||||
Cell sky130_fd_sc_hd__dfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -276,7 +244,6 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
Q_N output function=IQ_N
|
||||
RESET_B input 1.53-1.67
|
||||
SET_B input 3.35-3.53
|
||||
PASS: Sky130 async set/reset DFF cells
|
||||
Cell sky130_fd_sc_hd__mux2_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -313,8 +280,5 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
S0 input 3.70-4.09
|
||||
S1 input 2.61-2.74
|
||||
X output function=((((A0*!S0)*!S1)+((A1*S0)*!S1))+((A2*!S0)*S1))+((A3*S0)*S1)
|
||||
PASS: Sky130 mux cells
|
||||
PASS: write_liberty
|
||||
Warning: /workspace/sta/OpenSTA/liberty/test/results/liberty_cell_deep_write.lib line 1, library NangateOpenCellLibrary already exists.
|
||||
INFO: roundtrip read had issue: Error: /workspace/sta/OpenSTA/liberty/test/results/liberty_cell_deep_write.lib, l
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -20,13 +20,10 @@ source ../../test/helpers.tcl
|
|||
# Read libraries
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ"
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP"
|
||||
|
||||
############################################################
|
||||
# Port capacitance queries
|
||||
|
|
@ -36,19 +33,15 @@ set inv_a [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
|
|||
set inv_zn [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
|
||||
|
||||
set cap_a [get_property $inv_a capacitance]
|
||||
puts "PASS: INV_X1/A capacitance = $cap_a"
|
||||
|
||||
set cap_zn [get_property $inv_zn capacitance]
|
||||
puts "PASS: INV_X1/ZN capacitance = $cap_zn"
|
||||
|
||||
# DFF capacitance queries
|
||||
set dff_ck [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
|
||||
set cap_ck [get_property $dff_ck capacitance]
|
||||
puts "PASS: DFF_X1/CK capacitance = $cap_ck"
|
||||
|
||||
set dff_d [get_lib_pin NangateOpenCellLibrary/DFF_X1/D]
|
||||
set cap_d [get_property $dff_d capacitance]
|
||||
puts "PASS: DFF_X1/D capacitance = $cap_d"
|
||||
|
||||
# Larger drive strengths have different capacitances
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
|
|
@ -58,7 +51,6 @@ foreach size {1 2 4 8 16 32} {
|
|||
puts "INV_X${size}/A cap = $cap"
|
||||
}
|
||||
}
|
||||
puts "PASS: INV capacitance sweep"
|
||||
|
||||
foreach size {1 2 4 8 16 32} {
|
||||
catch {
|
||||
|
|
@ -67,7 +59,6 @@ foreach size {1 2 4 8 16 32} {
|
|||
puts "BUF_X${size}/A cap = $cap"
|
||||
}
|
||||
}
|
||||
puts "PASS: BUF capacitance sweep"
|
||||
|
||||
############################################################
|
||||
# Cell area queries
|
||||
|
|
@ -85,7 +76,6 @@ foreach cell_name {INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
|
|||
puts "$cell_name area = $area"
|
||||
}
|
||||
}
|
||||
puts "PASS: cell area queries"
|
||||
|
||||
############################################################
|
||||
# Cell dont_use, is_macro, is_memory queries
|
||||
|
|
@ -97,7 +87,6 @@ foreach cell_name {INV_X1 BUF_X1 DFF_X1 ANTENNA_X1 FILLCELL_X1} {
|
|||
puts "$cell_name dont_use = $du"
|
||||
}
|
||||
}
|
||||
puts "PASS: dont_use queries"
|
||||
|
||||
############################################################
|
||||
# Leakage power queries
|
||||
|
|
@ -109,7 +98,6 @@ foreach cell_name {INV_X1 BUF_X1 DFF_X1 NAND2_X1 NOR2_X1 AOI21_X1} {
|
|||
puts "$cell_name leakage_power = $lp"
|
||||
}
|
||||
}
|
||||
puts "PASS: leakage power queries"
|
||||
|
||||
############################################################
|
||||
# Timing arc property queries
|
||||
|
|
@ -124,112 +112,86 @@ create_clock -name clk2 -period 20 [get_ports clk2]
|
|||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: design with constraints"
|
||||
|
||||
# Detailed timing reports exercise arc evaluation
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay max
|
||||
puts "PASS: max path report"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay min
|
||||
puts "PASS: min path report"
|
||||
|
||||
report_checks -from [get_ports in2] -to [get_ports out2]
|
||||
puts "PASS: in2->out2 path"
|
||||
|
||||
# Rise/fall reports exercise different arc transitions
|
||||
report_checks -rise_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: rise_from path"
|
||||
|
||||
report_checks -fall_from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: fall_from path"
|
||||
|
||||
report_checks -from [get_ports in1] -rise_to [get_ports out1]
|
||||
puts "PASS: rise_to path"
|
||||
|
||||
report_checks -from [get_ports in1] -fall_to [get_ports out1]
|
||||
puts "PASS: fall_to path"
|
||||
|
||||
############################################################
|
||||
# Report check types exercises different check arc types
|
||||
############################################################
|
||||
report_check_types -max_delay -min_delay
|
||||
puts "PASS: report_check_types max/min delay"
|
||||
|
||||
report_check_types -max_slew -max_capacitance -max_fanout
|
||||
puts "PASS: report_check_types max_slew/cap/fanout"
|
||||
|
||||
report_check_types -recovery -removal
|
||||
puts "PASS: report_check_types recovery/removal"
|
||||
|
||||
report_check_types -min_pulse_width -min_period
|
||||
puts "PASS: report_check_types min_pulse_width/min_period"
|
||||
|
||||
report_check_types -clock_gating_setup -clock_gating_hold
|
||||
puts "PASS: report_check_types clock_gating"
|
||||
|
||||
report_check_types -max_skew
|
||||
puts "PASS: report_check_types max_skew"
|
||||
|
||||
############################################################
|
||||
# Report power to exercise internal power model paths
|
||||
############################################################
|
||||
report_power
|
||||
puts "PASS: report_power"
|
||||
|
||||
catch {
|
||||
report_power -instances [get_cells *]
|
||||
puts "PASS: report_power instances"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Sky130 cells - different tristate and latch cells
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
# Tristate buffer
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_2}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_4}
|
||||
puts "PASS: Sky130 tristate cells"
|
||||
|
||||
# Latch cells
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1}
|
||||
puts "PASS: Sky130 latch cells"
|
||||
|
||||
# Scan flip-flops
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1}
|
||||
puts "PASS: Sky130 scan DFF cells"
|
||||
|
||||
# DFF with async set/clear (exercises recovery/removal)
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1}
|
||||
puts "PASS: Sky130 async set/reset DFF cells"
|
||||
|
||||
# Mux cells
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2i_1}
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1}
|
||||
puts "PASS: Sky130 mux cells"
|
||||
|
||||
############################################################
|
||||
# Write roundtrip to exercise all writer cell/arc/model paths
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_cell_deep_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
puts "PASS: write_liberty"
|
||||
|
||||
# Read back and verify roundtrip (may have minor syntax issues)
|
||||
catch {
|
||||
read_liberty $outfile
|
||||
puts "PASS: read roundtrip library"
|
||||
} msg
|
||||
if {[string match "Error*" $msg]} {
|
||||
puts "INFO: roundtrip read had issue: [string range $msg 0 80]"
|
||||
}
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
PASS: read Sky130 library
|
||||
PASS: found liberty library
|
||||
--- voltage_map / supply queries ---
|
||||
VPWR exists: 1
|
||||
VGND exists: 1
|
||||
|
|
@ -10,9 +8,7 @@ LOWLVPWR exists: 1
|
|||
VPWRIN exists: 1
|
||||
VSS exists: 1
|
||||
FAKE_SUPPLY exists: 0
|
||||
PASS: supply voltage queries
|
||||
--- clock gate cell queries ---
|
||||
PASS: dlclkp clock gate cells
|
||||
sky130_fd_sc_hd__sdlclkp_1 area=18.768000
|
||||
VGND dir=ground func=
|
||||
VNB dir=unknown func=
|
||||
|
|
@ -43,9 +39,7 @@ sky130_fd_sc_hd__sdlclkp_4 area=22.521601
|
|||
GCLK dir=output func=
|
||||
M0 dir=internal func=
|
||||
SCE dir=input func=
|
||||
PASS: sdlclkp clock gate cells with precontrol
|
||||
--- level shifter cell queries ---
|
||||
PASS: level shifter cell queries
|
||||
--- pg_pin queries ---
|
||||
sky130_fd_sc_hd__inv_1: pwr_pins=4 signal_pins=2
|
||||
sky130_fd_sc_hd__buf_1: pwr_pins=4 signal_pins=2
|
||||
|
|
@ -53,15 +47,11 @@ sky130_fd_sc_hd__nand2_1: pwr_pins=4 signal_pins=3
|
|||
sky130_fd_sc_hd__dfxtp_1: pwr_pins=4 signal_pins=5
|
||||
sky130_fd_sc_hd__dlclkp_1: pwr_pins=4 signal_pins=4
|
||||
sky130_fd_sc_hd__sdfxtp_1: pwr_pins=4 signal_pins=7
|
||||
PASS: pg_pin queries
|
||||
--- clock gate timing arcs ---
|
||||
dlclkp_1 arc_sets = 4
|
||||
PASS: clock gate timing arcs
|
||||
sdlclkp_1 arc_sets = 6
|
||||
PASS: sdlclkp timing arcs
|
||||
--- level shifter timing arcs ---
|
||||
lsbuf_lh_hl_isowell_tap_1 arcs = 1
|
||||
PASS: level shifter timing arcs
|
||||
--- cell classification ---
|
||||
sky130_fd_sc_hd__inv_1: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
sky130_fd_sc_hd__inv_2: is_buffer=0 is_inverter=1 is_leaf=1
|
||||
|
|
@ -73,13 +63,8 @@ sky130_fd_sc_hd__nand2_1: is_buffer=0 is_inverter=0 is_leaf=1
|
|||
sky130_fd_sc_hd__nor2_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__dfxtp_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
sky130_fd_sc_hd__dlclkp_1: is_buffer=0 is_inverter=0 is_leaf=1
|
||||
PASS: cell classification
|
||||
PASS: write_liberty sky130
|
||||
PASS: read IHP library
|
||||
IHP VDD exists: 0
|
||||
IHP sg13g2_inv_1: area=5.443200 buf=0 inv=1
|
||||
IHP sg13g2_buf_1: area=7.257600 buf=1 inv=0
|
||||
IHP sg13g2_nand2_1: area=7.257600 buf=0 inv=0
|
||||
IHP sg13g2_nor2_1: area=7.257600 buf=0 inv=0
|
||||
PASS: IHP cell queries
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -17,10 +17,8 @@ source ../../test/helpers.tcl
|
|||
# Read Sky130 library (has clock gate cells, level shifters, pg_pins)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130 library"
|
||||
|
||||
set lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
puts "PASS: found liberty library"
|
||||
|
||||
############################################################
|
||||
# Voltage map / supply voltage queries
|
||||
|
|
@ -56,8 +54,6 @@ puts "VSS exists: $vss_exists"
|
|||
set fake_exists [sta::liberty_supply_exists FAKE_SUPPLY]
|
||||
puts "FAKE_SUPPLY exists: $fake_exists"
|
||||
|
||||
puts "PASS: supply voltage queries"
|
||||
|
||||
############################################################
|
||||
# Clock gate cell queries (exercises clock_gating_integrated_cell)
|
||||
# dlclkp cells have latch_posedge type
|
||||
|
|
@ -78,7 +74,6 @@ foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: dlclkp clock gate cells"
|
||||
|
||||
# sdlclkp cells have latch_posedge_precontrol type
|
||||
foreach cell_name {sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__sdlclkp_2
|
||||
|
|
@ -101,7 +96,6 @@ foreach cell_name {sky130_fd_sc_hd__sdlclkp_1 sky130_fd_sc_hd__sdlclkp_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: sdlclkp clock gate cells with precontrol"
|
||||
|
||||
############################################################
|
||||
# Level shifter cell queries
|
||||
|
|
@ -137,7 +131,6 @@ foreach cell_name {sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: level shifter cell queries"
|
||||
|
||||
############################################################
|
||||
# PG pin queries on various cells
|
||||
|
|
@ -168,7 +161,6 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__buf_1
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: pg_pin queries"
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on clock gate cells
|
||||
|
|
@ -190,7 +182,6 @@ catch {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: clock gate timing arcs"
|
||||
|
||||
catch {
|
||||
set cell [get_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdlclkp_1]
|
||||
|
|
@ -203,7 +194,6 @@ catch {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: sdlclkp timing arcs"
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on level shifter cells
|
||||
|
|
@ -220,7 +210,6 @@ catch {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: level shifter timing arcs"
|
||||
|
||||
############################################################
|
||||
# Buffer/inverter classification on Sky130 cells
|
||||
|
|
@ -242,7 +231,6 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: cell classification"
|
||||
|
||||
############################################################
|
||||
# Write liberty for sky130 (exercises writer for pg_pin, level_shifter)
|
||||
|
|
@ -250,14 +238,12 @@ puts "PASS: cell classification"
|
|||
set outfile [make_result_file liberty_clkgate_lvlshift_write.lib]
|
||||
catch {
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
puts "PASS: write_liberty sky130"
|
||||
}
|
||||
|
||||
############################################################
|
||||
# Read IHP library for more voltage_map / pg_pin coverage
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP library"
|
||||
|
||||
# Check supply exists after IHP
|
||||
set ihp_vdd_exists [sta::liberty_supply_exists VDD]
|
||||
|
|
@ -275,6 +261,3 @@ foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1 sg13g2_nor2_1} {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: IHP cell queries"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,43 +0,0 @@
|
|||
PASS: make_equiv_cells
|
||||
PASS: find_equiv_cells INV_X1 (6 equivs)
|
||||
PASS: find_equiv_cells BUF_X1 (9 equivs)
|
||||
PASS: find_equiv_cells NAND2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells NOR2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells AND2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells OR2_X1 (3 equivs)
|
||||
PASS: find_equiv_cells DFF_X1 (2 equivs)
|
||||
PASS: find_equiv_cells DFFR_X1 (2 equivs)
|
||||
PASS: find_equiv_cells DFFS_X1 (2 equivs)
|
||||
PASS: find_equiv_cells AOI21_X1 (3 equivs)
|
||||
PASS: find_equiv_cells OAI21_X1 (3 equivs)
|
||||
PASS: find_equiv_cells MUX2_X1 (2 equivs)
|
||||
PASS: find_equiv_cells SDFF_X1 (2 equivs)
|
||||
PASS: equiv_cells INV_X1 INV_X2 = 1
|
||||
PASS: equiv_cells BUF_X1 BUF_X2 = 1
|
||||
PASS: equiv_cells INV_X1 BUF_X1 = 0
|
||||
PASS: equiv_cells NAND2_X1 NOR2_X1 = 0
|
||||
PASS: equiv_cells DFF_X1 DFF_X2 = 1
|
||||
PASS: equiv_cells DFF_X1 DFFR_X1 = 0
|
||||
PASS: equiv_cells NAND2_X1 NAND3_X1 = 0
|
||||
PASS: equiv_cells INV_X4 INV_X8 = 1
|
||||
PASS: equiv_cell_ports INV_X1 INV_X2 = 1
|
||||
PASS: equiv_cell_ports INV_X1 BUF_X1 = 0
|
||||
PASS: equiv_cell_ports NAND2_X1 NAND2_X2 = 1
|
||||
PASS: equiv_cell_ports NAND2_X1 NAND3_X1 = 0
|
||||
PASS: equiv_cell_timing_arcs INV_X1 INV_X2 = 1
|
||||
PASS: equiv_cell_timing_arcs BUF_X1 BUF_X2 = 1
|
||||
PASS: equiv_cell_timing_arcs INV_X1 BUF_X1 = 0
|
||||
PASS: find_library_buffers (9 buffers)
|
||||
PASS: find_liberty found
|
||||
PASS: liberty_library_iterator
|
||||
PASS: liberty_supply_exists VDD = 1
|
||||
PASS: liberty_supply_exists VSS = 1
|
||||
PASS: liberty_supply_exists NONEXISTENT = 0
|
||||
PASS: INV_X1/A direction = input
|
||||
PASS: INV_X1/ZN direction = output
|
||||
PASS: DFF_X1/CK direction = input
|
||||
PASS: DFF_X1/Q direction = output
|
||||
PASS: make_equiv_cells fast library
|
||||
PASS: find_equiv_cells fast INV_X1 (6 equivs)
|
||||
PASS: equiv_cells across libraries = 1
|
||||
ALL PASSED
|
||||
|
|
@ -8,66 +8,52 @@ read_liberty ../../test/nangate45/Nangate45_typ.lib
|
|||
# Make equivalent cells for the Nangate library
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $lib
|
||||
puts "PASS: make_equiv_cells"
|
||||
|
||||
# Find equiv cells for various cell types
|
||||
# INV_X1 should have equivalents (INV_X2, INV_X4, etc.)
|
||||
set inv_cell [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_equivs [sta::find_equiv_cells $inv_cell]
|
||||
puts "PASS: find_equiv_cells INV_X1 ([llength $inv_equivs] equivs)"
|
||||
|
||||
set buf_cell [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_equivs [sta::find_equiv_cells $buf_cell]
|
||||
puts "PASS: find_equiv_cells BUF_X1 ([llength $buf_equivs] equivs)"
|
||||
|
||||
set nand_cell [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand_equivs [sta::find_equiv_cells $nand_cell]
|
||||
puts "PASS: find_equiv_cells NAND2_X1 ([llength $nand_equivs] equivs)"
|
||||
|
||||
set nor_cell [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
set nor_equivs [sta::find_equiv_cells $nor_cell]
|
||||
puts "PASS: find_equiv_cells NOR2_X1 ([llength $nor_equivs] equivs)"
|
||||
|
||||
set and_cell [get_lib_cell NangateOpenCellLibrary/AND2_X1]
|
||||
set and_equivs [sta::find_equiv_cells $and_cell]
|
||||
puts "PASS: find_equiv_cells AND2_X1 ([llength $and_equivs] equivs)"
|
||||
|
||||
set or_cell [get_lib_cell NangateOpenCellLibrary/OR2_X1]
|
||||
set or_equivs [sta::find_equiv_cells $or_cell]
|
||||
puts "PASS: find_equiv_cells OR2_X1 ([llength $or_equivs] equivs)"
|
||||
|
||||
# DFF cells
|
||||
set dff_cell [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_equivs [sta::find_equiv_cells $dff_cell]
|
||||
puts "PASS: find_equiv_cells DFF_X1 ([llength $dff_equivs] equivs)"
|
||||
|
||||
set dffr_cell [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set dffr_equivs [sta::find_equiv_cells $dffr_cell]
|
||||
puts "PASS: find_equiv_cells DFFR_X1 ([llength $dffr_equivs] equivs)"
|
||||
|
||||
set dffs_cell [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set dffs_equivs [sta::find_equiv_cells $dffs_cell]
|
||||
puts "PASS: find_equiv_cells DFFS_X1 ([llength $dffs_equivs] equivs)"
|
||||
|
||||
# AOI cells
|
||||
set aoi_cell [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
set aoi_equivs [sta::find_equiv_cells $aoi_cell]
|
||||
puts "PASS: find_equiv_cells AOI21_X1 ([llength $aoi_equivs] equivs)"
|
||||
|
||||
# OAI cells
|
||||
set oai_cell [get_lib_cell NangateOpenCellLibrary/OAI21_X1]
|
||||
set oai_equivs [sta::find_equiv_cells $oai_cell]
|
||||
puts "PASS: find_equiv_cells OAI21_X1 ([llength $oai_equivs] equivs)"
|
||||
|
||||
# MUX cells
|
||||
set mux_cell [get_lib_cell NangateOpenCellLibrary/MUX2_X1]
|
||||
set mux_equivs [sta::find_equiv_cells $mux_cell]
|
||||
puts "PASS: find_equiv_cells MUX2_X1 ([llength $mux_equivs] equivs)"
|
||||
|
||||
# SDFF cells
|
||||
set sdff_cell [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_cell]
|
||||
puts "PASS: find_equiv_cells SDFF_X1 ([llength $sdff_equivs] equivs)"
|
||||
|
||||
############################################################
|
||||
# equiv_cells comparison
|
||||
|
|
@ -77,117 +63,92 @@ puts "PASS: find_equiv_cells SDFF_X1 ([llength $sdff_equivs] equivs)"
|
|||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_x2 [get_lib_cell NangateOpenCellLibrary/INV_X2]
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cells INV_X1 INV_X2 = $result"
|
||||
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_x2 [get_lib_cell NangateOpenCellLibrary/BUF_X2]
|
||||
set result [sta::equiv_cells $buf_x1 $buf_x2]
|
||||
puts "PASS: equiv_cells BUF_X1 BUF_X2 = $result"
|
||||
|
||||
# Different-function cells should NOT be equivalent
|
||||
set result [sta::equiv_cells $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cells INV_X1 BUF_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cells $nand_cell $nor_cell]
|
||||
puts "PASS: equiv_cells NAND2_X1 NOR2_X1 = $result"
|
||||
|
||||
# DFF equivalence
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
set dff_x2 [get_lib_cell NangateOpenCellLibrary/DFF_X2]
|
||||
set result [sta::equiv_cells $dff_x1 $dff_x2]
|
||||
puts "PASS: equiv_cells DFF_X1 DFF_X2 = $result"
|
||||
|
||||
# DFF vs DFFR (different function - has reset)
|
||||
set result [sta::equiv_cells $dff_x1 $dffr_cell]
|
||||
puts "PASS: equiv_cells DFF_X1 DFFR_X1 = $result"
|
||||
|
||||
# NAND2 vs NAND3 (different port count)
|
||||
set nand3_cell [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set result [sta::equiv_cells $nand_cell $nand3_cell]
|
||||
puts "PASS: equiv_cells NAND2_X1 NAND3_X1 = $result"
|
||||
|
||||
# Larger drive strengths
|
||||
set inv_x4 [get_lib_cell NangateOpenCellLibrary/INV_X4]
|
||||
set inv_x8 [get_lib_cell NangateOpenCellLibrary/INV_X8]
|
||||
set result [sta::equiv_cells $inv_x4 $inv_x8]
|
||||
puts "PASS: equiv_cells INV_X4 INV_X8 = $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_ports comparison
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cell_ports INV_X1 INV_X2 = $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cell_ports INV_X1 BUF_X1 = $result"
|
||||
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
set nand2_x2 [get_lib_cell NangateOpenCellLibrary/NAND2_X2]
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand2_x2]
|
||||
puts "PASS: equiv_cell_ports NAND2_X1 NAND2_X2 = $result"
|
||||
|
||||
# Different port count cells
|
||||
set nand3_x1 [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand3_x1]
|
||||
puts "PASS: equiv_cell_ports NAND2_X1 NAND3_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_timing_arcs comparison
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cell_timing_arcs INV_X1 INV_X2 = $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $buf_x1 $buf_x2]
|
||||
puts "PASS: equiv_cell_timing_arcs BUF_X1 BUF_X2 = $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cell_timing_arcs INV_X1 BUF_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# find_library_buffers
|
||||
############################################################
|
||||
|
||||
set buffers [sta::find_library_buffers $lib]
|
||||
puts "PASS: find_library_buffers ([llength $buffers] buffers)"
|
||||
|
||||
############################################################
|
||||
# Additional library queries
|
||||
############################################################
|
||||
|
||||
set found_lib [sta::find_liberty NangateOpenCellLibrary]
|
||||
puts "PASS: find_liberty found"
|
||||
|
||||
set lib_iter [sta::liberty_library_iterator]
|
||||
puts "PASS: liberty_library_iterator"
|
||||
|
||||
# liberty_supply_exists
|
||||
set result [sta::liberty_supply_exists VDD]
|
||||
puts "PASS: liberty_supply_exists VDD = $result"
|
||||
|
||||
set result [sta::liberty_supply_exists VSS]
|
||||
puts "PASS: liberty_supply_exists VSS = $result"
|
||||
|
||||
set result [sta::liberty_supply_exists NONEXISTENT]
|
||||
puts "PASS: liberty_supply_exists NONEXISTENT = $result"
|
||||
|
||||
# liberty_port_direction on various pins
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: INV_X1/A direction = $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: INV_X1/ZN direction = $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: DFF_X1/CK direction = $dir"
|
||||
|
||||
set pin [get_lib_pin NangateOpenCellLibrary/DFF_X1/Q]
|
||||
set dir [sta::liberty_port_direction $pin]
|
||||
puts "PASS: DFF_X1/Q direction = $dir"
|
||||
|
||||
############################################################
|
||||
# EquivCells across fast library
|
||||
|
|
@ -196,14 +157,9 @@ puts "PASS: DFF_X1/Q direction = $dir"
|
|||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
sta::make_equiv_cells $fast_lib
|
||||
puts "PASS: make_equiv_cells fast library"
|
||||
|
||||
set fast_inv [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set fast_inv_equivs [sta::find_equiv_cells $fast_inv]
|
||||
puts "PASS: find_equiv_cells fast INV_X1 ([llength $fast_inv_equivs] equivs)"
|
||||
|
||||
# Cross-library equiv check
|
||||
set result [sta::equiv_cells $inv_x1 $fast_inv]
|
||||
puts "PASS: equiv_cells across libraries = $result"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,3 @@
|
|||
PASS: read ASAP7 INVBUF RVT
|
||||
PASS: read ASAP7 INVBUF LVT
|
||||
PASS: read ASAP7 INVBUF SLVT
|
||||
PASS: make_equiv_cells ASAP7 RVT INVBUF
|
||||
INVx1_ASAP7_75t_R equiv count = 21
|
||||
INVx2_ASAP7_75t_R equiv count = 21
|
||||
INVx3_ASAP7_75t_R equiv count = 21
|
||||
|
|
@ -20,9 +16,6 @@ BUFx8_ASAP7_75t_R equiv count = 16
|
|||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx11_ASAP7_75t_R' not found.
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx13_ASAP7_75t_R' not found.
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx16_ASAP7_75t_R' not found.
|
||||
PASS: ASAP7 RVT INVBUF equiv cells
|
||||
PASS: ASAP7 RVT buffers = 16
|
||||
PASS: make_equiv_cells ASAP7 LVT INVBUF
|
||||
LVT INVx1_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx2_ASAP7_75t_L equiv count = 21
|
||||
LVT INVx4_ASAP7_75t_L equiv count = 21
|
||||
|
|
@ -31,33 +24,19 @@ Warning: liberty_equiv_cross_lib.tcl line 1, cell 'BUFx1_ASAP7_75t_L' not found.
|
|||
LVT BUFx2_ASAP7_75t_L equiv count = 16
|
||||
LVT BUFx4_ASAP7_75t_L equiv count = 16
|
||||
LVT BUFx8_ASAP7_75t_L equiv count = 16
|
||||
PASS: ASAP7 LVT INVBUF equiv cells
|
||||
PASS: ASAP7 LVT buffers = 16
|
||||
PASS: make_equiv_cells ASAP7 SLVT INVBUF
|
||||
PASS: ASAP7 SLVT buffers = 16
|
||||
--- cross-Vt equiv comparisons ---
|
||||
equiv RVT/LVT INVx1 = 1
|
||||
port_equiv RVT/LVT INVx1 = 1
|
||||
arc_equiv RVT/LVT INVx1 = 1
|
||||
PASS: cross-Vt comparisons
|
||||
PASS: read ASAP7 SEQ RVT + LVT
|
||||
PASS: make_equiv_cells SEQ RVT
|
||||
SEQ RVT DFFHQNx1 equiv count = 3
|
||||
equiv: DFFHQNx1_ASAP7_75t_R
|
||||
equiv: DFFHQNx2_ASAP7_75t_R
|
||||
equiv: DFFHQNx3_ASAP7_75t_R
|
||||
PASS: SEQ RVT DFF equiv
|
||||
SEQ RVT ICGx1 equiv count = 10
|
||||
PASS: SEQ RVT ICG equiv
|
||||
SEQ RVT DLLx1 equiv count = 3
|
||||
PASS: SEQ RVT latch equiv
|
||||
Warning: liberty_equiv_cross_lib.tcl line 1, cell 'SDFHQNx1_ASAP7_75t_R' not found.
|
||||
PASS: SEQ RVT SDFF equiv
|
||||
equiv SEQ RVT/LVT DFFHQNx1 = 1
|
||||
port_equiv SEQ RVT/LVT DFFHQNx1 = 1
|
||||
PASS: cross-lib SEQ comparisons
|
||||
PASS: read Sky130
|
||||
PASS: make_equiv_cells Sky130
|
||||
Sky130 inv_1 equiv count = 16
|
||||
equiv: sky130_fd_sc_hd__clkinvlp_2
|
||||
equiv: sky130_fd_sc_hd__inv_1
|
||||
|
|
@ -75,11 +54,7 @@ Sky130 inv_1 equiv count = 16
|
|||
equiv: sky130_fd_sc_hd__bufinv_16
|
||||
equiv: sky130_fd_sc_hd__inv_16
|
||||
equiv: sky130_fd_sc_hd__clkinv_16
|
||||
PASS: Sky130 inv equiv
|
||||
Sky130 dfxtp_1 equiv count = 3
|
||||
equiv: sky130_fd_sc_hd__dfxtp_1
|
||||
equiv: sky130_fd_sc_hd__dfxtp_2
|
||||
equiv: sky130_fd_sc_hd__dfxtp_4
|
||||
PASS: Sky130 DFF equiv
|
||||
PASS: Sky130 buffers = 35
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -15,20 +15,16 @@ source ../../test/helpers.tcl
|
|||
# Read multiple ASAP7 Vt flavors for cross-library equiv
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF RVT"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF LVT"
|
||||
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz
|
||||
puts "PASS: read ASAP7 INVBUF SLVT"
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for RVT library
|
||||
############################################################
|
||||
set rvt_lib [lindex [get_libs asap7sc7p5t_INVBUF_RVT_FF_nldm_211120] 0]
|
||||
sta::make_equiv_cells $rvt_lib
|
||||
puts "PASS: make_equiv_cells ASAP7 RVT INVBUF"
|
||||
|
||||
# Find equiv cells in ASAP7 RVT
|
||||
foreach cell_prefix {INVx BUFx} {
|
||||
|
|
@ -47,18 +43,15 @@ foreach cell_prefix {INVx BUFx} {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: ASAP7 RVT INVBUF equiv cells"
|
||||
|
||||
# Find library buffers
|
||||
set rvt_buffers [sta::find_library_buffers $rvt_lib]
|
||||
puts "PASS: ASAP7 RVT buffers = [llength $rvt_buffers]"
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for LVT library
|
||||
############################################################
|
||||
set lvt_lib [lindex [get_libs asap7sc7p5t_INVBUF_LVT_FF_nldm_211120] 0]
|
||||
sta::make_equiv_cells $lvt_lib
|
||||
puts "PASS: make_equiv_cells ASAP7 LVT INVBUF"
|
||||
|
||||
foreach cell_prefix {INVx BUFx} {
|
||||
foreach size {1 2 4 8} {
|
||||
|
|
@ -76,20 +69,16 @@ foreach cell_prefix {INVx BUFx} {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: ASAP7 LVT INVBUF equiv cells"
|
||||
|
||||
set lvt_buffers [sta::find_library_buffers $lvt_lib]
|
||||
puts "PASS: ASAP7 LVT buffers = [llength $lvt_buffers]"
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for SLVT library
|
||||
############################################################
|
||||
set slvt_lib [lindex [get_libs asap7sc7p5t_INVBUF_SLVT_FF_nldm_211120] 0]
|
||||
sta::make_equiv_cells $slvt_lib
|
||||
puts "PASS: make_equiv_cells ASAP7 SLVT INVBUF"
|
||||
|
||||
set slvt_buffers [sta::find_library_buffers $slvt_lib]
|
||||
puts "PASS: ASAP7 SLVT buffers = [llength $slvt_buffers]"
|
||||
|
||||
############################################################
|
||||
# Cross-Vt equiv_cells comparisons
|
||||
|
|
@ -107,18 +96,15 @@ catch {
|
|||
set result [sta::equiv_cell_timing_arcs $rvt_inv $lvt_inv]
|
||||
puts "arc_equiv RVT/LVT INVx1 = $result"
|
||||
}
|
||||
puts "PASS: cross-Vt comparisons"
|
||||
|
||||
############################################################
|
||||
# Read ASAP7 SEQ libraries for sequential equiv
|
||||
############################################################
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
|
||||
read_liberty ../../test/asap7/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib
|
||||
puts "PASS: read ASAP7 SEQ RVT + LVT"
|
||||
|
||||
set seq_rvt_lib [lindex [get_libs asap7sc7p5t_SEQ_RVT_FF_nldm_220123] 0]
|
||||
sta::make_equiv_cells $seq_rvt_lib
|
||||
puts "PASS: make_equiv_cells SEQ RVT"
|
||||
|
||||
# Find equiv cells for DFF cells
|
||||
catch {
|
||||
|
|
@ -133,7 +119,6 @@ catch {
|
|||
puts "SEQ RVT DFFHQNx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
puts "PASS: SEQ RVT DFF equiv"
|
||||
|
||||
# ICG equiv cells
|
||||
catch {
|
||||
|
|
@ -145,7 +130,6 @@ catch {
|
|||
puts "SEQ RVT ICGx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
puts "PASS: SEQ RVT ICG equiv"
|
||||
|
||||
# Latch equiv cells
|
||||
catch {
|
||||
|
|
@ -157,7 +141,6 @@ catch {
|
|||
puts "SEQ RVT DLLx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
puts "PASS: SEQ RVT latch equiv"
|
||||
|
||||
# SDFF equiv cells
|
||||
catch {
|
||||
|
|
@ -169,7 +152,6 @@ catch {
|
|||
puts "SEQ RVT SDFHQNx1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
puts "PASS: SEQ RVT SDFF equiv"
|
||||
|
||||
############################################################
|
||||
# Cross-library comparisons of DFF cells
|
||||
|
|
@ -182,17 +164,14 @@ catch {
|
|||
set result [sta::equiv_cell_ports $rvt_dff $lvt_dff]
|
||||
puts "port_equiv SEQ RVT/LVT DFFHQNx1 = $result"
|
||||
}
|
||||
puts "PASS: cross-lib SEQ comparisons"
|
||||
|
||||
############################################################
|
||||
# Read Sky130 and make equiv cells for a very different PDK
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
|
||||
sta::make_equiv_cells $sky_lib
|
||||
puts "PASS: make_equiv_cells Sky130"
|
||||
|
||||
# Find equiv cells for Sky130 inverters
|
||||
catch {
|
||||
|
|
@ -207,7 +186,6 @@ catch {
|
|||
puts "Sky130 inv_1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 inv equiv"
|
||||
|
||||
# Find equiv for Sky130 DFF
|
||||
catch {
|
||||
|
|
@ -222,9 +200,5 @@ catch {
|
|||
puts "Sky130 dfxtp_1 equiv count = 0"
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 DFF equiv"
|
||||
|
||||
set sky_buffers [sta::find_library_buffers $sky_lib]
|
||||
puts "PASS: Sky130 buffers = [llength $sky_buffers]"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
PASS: read Nangate45
|
||||
PASS: make_equiv_cells
|
||||
INV_X1 equiv count = 6
|
||||
equiv: INV_X1
|
||||
equiv: INV_X2
|
||||
|
|
@ -7,7 +5,6 @@ INV_X1 equiv count = 6
|
|||
equiv: INV_X8
|
||||
equiv: INV_X16
|
||||
equiv: INV_X32
|
||||
PASS: INV equiv cells
|
||||
BUF_X1 equiv count = 9
|
||||
equiv: BUF_X1
|
||||
equiv: CLKBUF_X1
|
||||
|
|
@ -18,71 +15,49 @@ BUF_X1 equiv count = 9
|
|||
equiv: BUF_X8
|
||||
equiv: BUF_X16
|
||||
equiv: BUF_X32
|
||||
PASS: BUF equiv cells
|
||||
NAND2_X1 equiv count = 3
|
||||
PASS: NAND2 equiv cells
|
||||
NOR2_X1 equiv count = 3
|
||||
PASS: NOR2 equiv cells
|
||||
AND2_X1 equiv count = 3
|
||||
PASS: AND2 equiv cells
|
||||
OR2_X1 equiv count = 3
|
||||
PASS: OR2 equiv cells
|
||||
XOR2_X1 equiv count = 2
|
||||
PASS: XOR2 equiv cells
|
||||
XNOR2_X1 equiv count = 2
|
||||
PASS: XNOR2 equiv cells
|
||||
NAND3_X1 equiv count = 3
|
||||
NOR3_X1 equiv count = 3
|
||||
AND3_X1 equiv count = 3
|
||||
OR3_X1 equiv count = 3
|
||||
PASS: 3-input gate equiv cells
|
||||
NAND4_X1 equiv count = 3
|
||||
NOR4_X1 equiv count = 3
|
||||
AND4_X1 equiv count = 3
|
||||
OR4_X1 equiv count = 3
|
||||
PASS: 4-input gate equiv cells
|
||||
AOI21_X1 equiv count = 3
|
||||
OAI21_X1 equiv count = 3
|
||||
AOI22_X1 equiv count = 3
|
||||
OAI22_X1 equiv count = 3
|
||||
AOI211_X1 equiv count = 2
|
||||
OAI211_X1 equiv count = 3
|
||||
PASS: AOI/OAI equiv cells
|
||||
MUX2_X1 equiv count = 2
|
||||
PASS: MUX equiv cells
|
||||
DFF_X1 equiv count = 2
|
||||
equiv: DFF_X1
|
||||
equiv: DFF_X2
|
||||
PASS: DFF equiv cells
|
||||
DFFR_X1 equiv count = 2
|
||||
PASS: DFFR equiv cells
|
||||
DFFS_X1 equiv count = 2
|
||||
PASS: DFFS equiv cells
|
||||
SDFF_X1 equiv count = 2
|
||||
PASS: SDFF equiv cells
|
||||
equiv INV BUF = 0
|
||||
equiv INV NAND = 0
|
||||
equiv NAND NOR = 0
|
||||
equiv INV DFF = 0
|
||||
PASS: cross-type comparisons
|
||||
port_equiv INV_X1 INV_X2 = 1
|
||||
port_equiv INV_X1 BUF_X1 = 0
|
||||
port_equiv NAND2_X1 NAND2_X2 = 1
|
||||
PASS: port equivalence
|
||||
arc_equiv INV_X1 INV_X2 = 1
|
||||
arc_equiv INV_X1 BUF_X1 = 0
|
||||
arc_equiv DFF_X1 DFF_X2 = 1
|
||||
arc_equiv DFF_X1 DFFR_X1 = 0
|
||||
PASS: timing arc equivalence
|
||||
PASS: read Nangate45_fast
|
||||
PASS: make_equiv_cells fast lib
|
||||
equiv typ_INV fast_INV = 1
|
||||
equiv typ_INV fast_BUF = 0
|
||||
port_equiv typ_INV fast_INV = 1
|
||||
arc_equiv typ_INV fast_INV = 1
|
||||
PASS: cross-library equivalence
|
||||
fast INV_X1 equiv count = 6
|
||||
PASS: fast lib equiv cells
|
||||
Library buffers count = 9
|
||||
buffer: BUF_X1
|
||||
buffer: BUF_X16
|
||||
|
|
@ -93,5 +68,3 @@ Library buffers count = 9
|
|||
buffer: CLKBUF_X1
|
||||
buffer: CLKBUF_X2
|
||||
buffer: CLKBUF_X3
|
||||
PASS: find_library_buffers
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -14,7 +14,6 @@ source ../../test/helpers.tcl
|
|||
# Read Nangate library
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
|
||||
|
|
@ -22,7 +21,6 @@ set lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
|||
# Make equiv cells
|
||||
############################################################
|
||||
sta::make_equiv_cells $lib
|
||||
puts "PASS: make_equiv_cells"
|
||||
|
||||
############################################################
|
||||
# Test equiv cells for all major gate families
|
||||
|
|
@ -35,7 +33,6 @@ puts "INV_X1 equiv count = [llength $equivs]"
|
|||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
puts "PASS: INV equiv cells"
|
||||
|
||||
# Buffers
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
|
|
@ -44,53 +41,39 @@ puts "BUF_X1 equiv count = [llength $equivs]"
|
|||
foreach eq $equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
puts "PASS: BUF equiv cells"
|
||||
|
||||
# 2-input gates
|
||||
foreach gate {NAND2 NOR2 AND2 OR2 XOR2 XNOR2} {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
puts "PASS: ${gate} equiv cells"
|
||||
}
|
||||
|
||||
# 3-input gates
|
||||
foreach gate {NAND3 NOR3 AND3 OR3} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
puts "PASS: 3-input gate equiv cells"
|
||||
|
||||
# 4-input gates
|
||||
foreach gate {NAND4 NOR4 AND4 OR4} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
puts "PASS: 4-input gate equiv cells"
|
||||
|
||||
# AOI/OAI gates
|
||||
foreach gate {AOI21 OAI21 AOI22 OAI22 AOI211 OAI211} {
|
||||
catch {
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
set cell [get_lib_cell NangateOpenCellLibrary/${gate}_X1]
|
||||
set equivs [sta::find_equiv_cells $cell]
|
||||
puts "${gate}_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
puts "PASS: AOI/OAI equiv cells"
|
||||
|
||||
# MUX cells
|
||||
catch {
|
||||
set mux_cell [get_lib_cell NangateOpenCellLibrary/MUX2_X1]
|
||||
set equivs [sta::find_equiv_cells $mux_cell]
|
||||
puts "MUX2_X1 equiv count = [llength $equivs]"
|
||||
}
|
||||
puts "PASS: MUX equiv cells"
|
||||
set mux_cell [get_lib_cell NangateOpenCellLibrary/MUX2_X1]
|
||||
set equivs [sta::find_equiv_cells $mux_cell]
|
||||
puts "MUX2_X1 equiv count = [llength $equivs]"
|
||||
|
||||
# DFF cells (sequential equivalence)
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
|
|
@ -99,25 +82,21 @@ puts "DFF_X1 equiv count = [llength $dff_equivs]"
|
|||
foreach eq $dff_equivs {
|
||||
puts " equiv: [$eq name]"
|
||||
}
|
||||
puts "PASS: DFF equiv cells"
|
||||
|
||||
# DFFR cells (reset flip-flop)
|
||||
set dffr_x1 [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set dffr_equivs [sta::find_equiv_cells $dffr_x1]
|
||||
puts "DFFR_X1 equiv count = [llength $dffr_equivs]"
|
||||
puts "PASS: DFFR equiv cells"
|
||||
|
||||
# DFFS cells (set flip-flop)
|
||||
set dffs_x1 [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set dffs_equivs [sta::find_equiv_cells $dffs_x1]
|
||||
puts "DFFS_X1 equiv count = [llength $dffs_equivs]"
|
||||
puts "PASS: DFFS equiv cells"
|
||||
|
||||
# SDFF cells (scan DFF)
|
||||
set sdff_x1 [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_x1]
|
||||
puts "SDFF_X1 equiv count = [llength $sdff_equivs]"
|
||||
puts "PASS: SDFF equiv cells"
|
||||
|
||||
############################################################
|
||||
# Cross-cell type equiv comparisons (should be false)
|
||||
|
|
@ -133,30 +112,25 @@ puts "equiv INV BUF = [sta::equiv_cells $inv_x1 $buf_x1]"
|
|||
puts "equiv INV NAND = [sta::equiv_cells $inv_x1 $nand2_x1]"
|
||||
puts "equiv NAND NOR = [sta::equiv_cells $nand2_x1 $nor2_x1]"
|
||||
puts "equiv INV DFF = [sta::equiv_cells $inv_x1 $dff_x1]"
|
||||
puts "PASS: cross-type comparisons"
|
||||
|
||||
# Port equivalence detailed
|
||||
puts "port_equiv INV_X1 INV_X2 = [sta::equiv_cell_ports $inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X2]]"
|
||||
puts "port_equiv INV_X1 BUF_X1 = [sta::equiv_cell_ports $inv_x1 $buf_x1]"
|
||||
puts "port_equiv NAND2_X1 NAND2_X2 = [sta::equiv_cell_ports $nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X2]]"
|
||||
puts "PASS: port equivalence"
|
||||
|
||||
# Timing arc equivalence
|
||||
puts "arc_equiv INV_X1 INV_X2 = [sta::equiv_cell_timing_arcs $inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X2]]"
|
||||
puts "arc_equiv INV_X1 BUF_X1 = [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]"
|
||||
puts "arc_equiv DFF_X1 DFF_X2 = [sta::equiv_cell_timing_arcs $dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X2]]"
|
||||
puts "arc_equiv DFF_X1 DFFR_X1 = [sta::equiv_cell_timing_arcs $dff_x1 $dffr_x1]"
|
||||
puts "PASS: timing arc equivalence"
|
||||
|
||||
############################################################
|
||||
# Multi-library equivalence (exercises mapEquivCells)
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
puts "PASS: read Nangate45_fast"
|
||||
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
sta::make_equiv_cells $fast_lib
|
||||
puts "PASS: make_equiv_cells fast lib"
|
||||
|
||||
# Cross-library comparisons
|
||||
set fast_inv [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
|
|
@ -166,12 +140,10 @@ puts "equiv typ_INV fast_INV = [sta::equiv_cells $inv_x1 $fast_inv]"
|
|||
puts "equiv typ_INV fast_BUF = [sta::equiv_cells $inv_x1 $fast_buf]"
|
||||
puts "port_equiv typ_INV fast_INV = [sta::equiv_cell_ports $inv_x1 $fast_inv]"
|
||||
puts "arc_equiv typ_INV fast_INV = [sta::equiv_cell_timing_arcs $inv_x1 $fast_inv]"
|
||||
puts "PASS: cross-library equivalence"
|
||||
|
||||
# Find equiv cells in the fast library
|
||||
set fast_equivs [sta::find_equiv_cells $fast_inv]
|
||||
puts "fast INV_X1 equiv count = [llength $fast_equivs]"
|
||||
puts "PASS: fast lib equiv cells"
|
||||
|
||||
############################################################
|
||||
# Find library buffers
|
||||
|
|
@ -182,6 +154,3 @@ puts "Library buffers count = [llength $buffers]"
|
|||
foreach buf $buffers {
|
||||
puts " buffer: [$buf name]"
|
||||
}
|
||||
puts "PASS: find_library_buffers"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
PASS: read Nangate45
|
||||
INV_X1 equiv=6
|
||||
INV_X2 equiv=6
|
||||
INV_X4 equiv=6
|
||||
|
|
@ -93,7 +92,6 @@ CLKGATETST_X1 equiv=4
|
|||
CLKGATETST_X2 equiv=4
|
||||
CLKGATETST_X4 equiv=4
|
||||
CLKGATETST_X8 equiv=4
|
||||
PASS: Nangate45 find_equiv_cells
|
||||
equiv INV_X1 INV_X2 = 1
|
||||
equiv BUF_X1 BUF_X2 = 1
|
||||
equiv NAND2_X1 NAND2_X2 = 1
|
||||
|
|
@ -120,9 +118,7 @@ arcs DFF_X1 DFF_X2 = 1
|
|||
arcs DFF DFFR = 0
|
||||
arcs NAND2_X1 NAND2_X2 = 1
|
||||
arcs NAND2 NOR2 = 1
|
||||
PASS: Nangate45 pairwise
|
||||
Nangate45 buffers = 9
|
||||
PASS: read Sky130
|
||||
SKY sky130_fd_sc_hd__inv_1 equiv=16
|
||||
SKY sky130_fd_sc_hd__inv_2 equiv=16
|
||||
SKY sky130_fd_sc_hd__inv_4 equiv=16
|
||||
|
|
@ -152,9 +148,7 @@ SKY sky130_fd_sc_hd__dfrtp_4 equiv=3
|
|||
SKY sky130_fd_sc_hd__clkbuf_1 equiv=30
|
||||
SKY sky130_fd_sc_hd__clkbuf_2 equiv=30
|
||||
SKY sky130_fd_sc_hd__clkbuf_4 equiv=30
|
||||
PASS: Sky130 find_equiv_cells
|
||||
Sky130 buffers = 35
|
||||
PASS: read IHP
|
||||
IHP sg13g2_inv_1 equiv=5
|
||||
IHP sg13g2_inv_2 equiv=5
|
||||
IHP sg13g2_inv_4 equiv=5
|
||||
|
|
@ -171,6 +165,4 @@ IHP sg13g2_and2_1 equiv=2
|
|||
IHP sg13g2_and2_2 equiv=2
|
||||
IHP sg13g2_or2_1 equiv=2
|
||||
IHP sg13g2_or2_2 equiv=2
|
||||
PASS: IHP find_equiv_cells
|
||||
IHP buffers = 8
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@ source ../../test/helpers.tcl
|
|||
# Test 1: Nangate45 pairwise
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
set ng_lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $ng_lib
|
||||
|
|
@ -61,7 +60,6 @@ foreach cell_name {INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: Nangate45 find_equiv_cells"
|
||||
|
||||
# Extensive pairwise comparisons
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
|
|
@ -116,7 +114,6 @@ puts "arcs DFF_X1 DFF_X2 = [sta::equiv_cell_timing_arcs $dff_x1 $dff_x2]"
|
|||
puts "arcs DFF DFFR = [sta::equiv_cell_timing_arcs $dff_x1 $dffr_x1]"
|
||||
puts "arcs NAND2_X1 NAND2_X2 = [sta::equiv_cell_timing_arcs $nand2_x1 $nand2_x2]"
|
||||
puts "arcs NAND2 NOR2 = [sta::equiv_cell_timing_arcs $nand2_x1 $nor2_x1]"
|
||||
puts "PASS: Nangate45 pairwise"
|
||||
|
||||
set ng_bufs [sta::find_library_buffers $ng_lib]
|
||||
puts "Nangate45 buffers = [llength $ng_bufs]"
|
||||
|
|
@ -125,7 +122,6 @@ puts "Nangate45 buffers = [llength $ng_bufs]"
|
|||
# Test 2: Sky130 families
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
set sky_lib [lindex [get_libs sky130_fd_sc_hd__tt_025C_1v80] 0]
|
||||
sta::make_equiv_cells $sky_lib
|
||||
|
|
@ -151,7 +147,6 @@ foreach cell_name {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: Sky130 find_equiv_cells"
|
||||
|
||||
set sky_bufs [sta::find_library_buffers $sky_lib]
|
||||
puts "Sky130 buffers = [llength $sky_bufs]"
|
||||
|
|
@ -160,7 +155,6 @@ puts "Sky130 buffers = [llength $sky_bufs]"
|
|||
# Test 3: IHP cell families
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP"
|
||||
|
||||
set ihp_lib [lindex [get_libs sg13g2_stdcell_typ_1p20V_25C] 0]
|
||||
sta::make_equiv_cells $ihp_lib
|
||||
|
|
@ -183,9 +177,6 @@ foreach cell_name {
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: IHP find_equiv_cells"
|
||||
|
||||
set ihp_bufs [sta::find_library_buffers $ihp_lib]
|
||||
puts "IHP buffers = [llength $ihp_bufs]"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,4 @@
|
|||
PASS: read Nangate45
|
||||
Warning: liberty_func_expr.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
PASS: design setup
|
||||
Cell XOR2_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -9,7 +7,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
A input 2.18-2.23
|
||||
B input 2.36-2.41
|
||||
Z output function=A^B
|
||||
PASS: report XOR2_X1
|
||||
Cell XOR2_X2
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -18,7 +15,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
A input 4.24-4.33
|
||||
B input 4.40-4.50
|
||||
Z output function=A^B
|
||||
PASS: report XOR2_X2
|
||||
Cell XNOR2_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -27,7 +23,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
A input 2.13-2.23
|
||||
B input 2.37-2.57
|
||||
ZN output function=!(A^B)
|
||||
PASS: report XNOR2_X1
|
||||
Cell XNOR2_X2
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -36,7 +31,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
A input 3.80-4.00
|
||||
B input 4.42-4.84
|
||||
ZN output function=!(A^B)
|
||||
PASS: report XNOR2_X2
|
||||
Cell AOI21_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -64,7 +58,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B1 input 5.61-6.40
|
||||
B2 input 5.64-6.71
|
||||
ZN output function=!(A+(B1*B2))
|
||||
PASS: report AOI21 variants
|
||||
Cell AOI22_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -95,7 +88,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B1 input 5.98-6.09
|
||||
B2 input 6.18-6.61
|
||||
ZN output function=!((A1*A2)+(B1*B2))
|
||||
PASS: report AOI22 variants
|
||||
Cell AOI211_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -126,7 +118,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
C1 input 1.39-1.63
|
||||
C2 input 1.44-1.75
|
||||
ZN output function=!!!(((C1*C2)+B)+A)
|
||||
PASS: report AOI211 variants
|
||||
Cell OAI21_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -154,7 +145,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B1 input 5.56-6.35
|
||||
B2 input 6.46-6.50
|
||||
ZN output function=!(A*(B1+B2))
|
||||
PASS: report OAI21 variants
|
||||
Cell OAI22_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -185,7 +175,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B1 input 5.51-6.52
|
||||
B2 input 6.23-6.48
|
||||
ZN output function=!((A1+A2)*(B1+B2))
|
||||
PASS: report OAI22 variants
|
||||
Cell OAI211_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -216,7 +205,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
C1 input 5.61-6.21
|
||||
C2 input 6.30-6.42
|
||||
ZN output function=!(((C1+C2)*A)*B)
|
||||
PASS: report OAI211 variants
|
||||
Cell OAI33_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -229,7 +217,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B2 input 1.47-1.61
|
||||
B3 input 1.55-1.58
|
||||
ZN output function=!(((A1+A2)+A3)*((B1+B2)+B3))
|
||||
PASS: report OAI33
|
||||
Cell MUX2_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -248,7 +235,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B input 1.48-1.74
|
||||
S input 2.52-2.62
|
||||
Z output function=(S*B)+(A*!S)
|
||||
PASS: report MUX2 variants
|
||||
Cell FA_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -259,7 +245,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
CI input 2.66-2.76
|
||||
CO output function=(A*B)+(CI*(A+B))
|
||||
S output function=CI^(A^B)
|
||||
PASS: report FA_X1 (full adder)
|
||||
Cell HA_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -269,7 +254,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
B input 3.34-3.45
|
||||
CO output function=A*B
|
||||
S output function=A^B
|
||||
PASS: report HA_X1 (half adder)
|
||||
Cell TINV_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -278,7 +262,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
EN input 1.64-1.75
|
||||
I input 1.38-1.44
|
||||
ZN tristate enable=!EN function=!I 0.80-0.80
|
||||
PASS: report TINV_X1 (tristate inv)
|
||||
Cell TBUF_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -295,14 +278,12 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
A input 3.11-3.33
|
||||
EN input 2.54-2.74
|
||||
Z tristate enable=!EN function=A 1.63-1.64
|
||||
PASS: report TBUF tristate buffer
|
||||
Cell ANTENNA_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
A input 0.02-0.02
|
||||
PASS: report ANTENNA_X1
|
||||
Cell FILLCELL_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -333,7 +314,6 @@ Library NangateOpenCellLibrary
|
|||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
VDD power
|
||||
VSS ground
|
||||
PASS: report FILLCELL variants
|
||||
Cell LOGIC0_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -346,7 +326,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
VDD power
|
||||
VSS ground
|
||||
Z output function=1
|
||||
PASS: report tie cells
|
||||
Cell CLKGATETST_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -387,7 +366,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
E input 0.86-0.90
|
||||
SE input 0.74-0.80
|
||||
GCK output
|
||||
PASS: report clock gate cells
|
||||
Cell SDFF_X1
|
||||
Library NangateOpenCellLibrary
|
||||
File ../../test/nangate45/Nangate45_typ.lib
|
||||
|
|
@ -500,9 +478,6 @@ File ../../test/nangate45/Nangate45_typ.lib
|
|||
CK input 0.84-0.94
|
||||
Q output function=IQ
|
||||
QN output function=IQN
|
||||
PASS: report scan DFF variants
|
||||
PASS: write_liberty (exercises FuncExpr::to_string)
|
||||
PASS: read IHP library
|
||||
Cell sg13g2_inv_1
|
||||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
|
|
@ -569,9 +544,6 @@ Cell sg13g2_tielo
|
|||
Library sg13g2_stdcell_typ_1p20V_25C
|
||||
File ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
L_LO output function=0
|
||||
PASS: IHP cell reports
|
||||
PASS: write_liberty IHP
|
||||
PASS: read Sky130
|
||||
Cell sky130_fd_sc_hd__a21o_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -792,10 +764,5 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
A input 1.73-1.88
|
||||
TE_B input 2.93-3.34
|
||||
Z tristate enable=!TE_B function=A 2.26
|
||||
PASS: Sky130 complex cell reports
|
||||
PASS: write_liberty Sky130
|
||||
No paths found.
|
||||
PASS: report_checks
|
||||
No paths found.
|
||||
PASS: report_checks min delay
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -10,7 +10,6 @@ source ../../test/helpers.tcl
|
|||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
# Link a design to enable timing queries
|
||||
read_verilog ../../sdc/test/sdc_test2.v
|
||||
|
|
@ -20,23 +19,18 @@ create_clock -name clk1 -period 10 [get_ports clk1]
|
|||
create_clock -name clk2 -period 20 [get_ports clk2]
|
||||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
puts "PASS: design setup"
|
||||
|
||||
############################################################
|
||||
# XOR/XNOR cells (FuncExpr op_xor)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XOR2_X1
|
||||
puts "PASS: report XOR2_X1"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XOR2_X2
|
||||
puts "PASS: report XOR2_X2"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XNOR2_X1
|
||||
puts "PASS: report XNOR2_X1"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/XNOR2_X2
|
||||
puts "PASS: report XNOR2_X2"
|
||||
|
||||
############################################################
|
||||
# AOI cells (complex AND-OR-INVERT functions)
|
||||
|
|
@ -46,19 +40,16 @@ puts "PASS: report XNOR2_X2"
|
|||
report_lib_cell NangateOpenCellLibrary/AOI21_X1
|
||||
report_lib_cell NangateOpenCellLibrary/AOI21_X2
|
||||
report_lib_cell NangateOpenCellLibrary/AOI21_X4
|
||||
puts "PASS: report AOI21 variants"
|
||||
|
||||
# AOI22: !(A1&A2 | B1&B2)
|
||||
report_lib_cell NangateOpenCellLibrary/AOI22_X1
|
||||
report_lib_cell NangateOpenCellLibrary/AOI22_X2
|
||||
report_lib_cell NangateOpenCellLibrary/AOI22_X4
|
||||
puts "PASS: report AOI22 variants"
|
||||
|
||||
# AOI211: !(A1&A2 | B | C)
|
||||
report_lib_cell NangateOpenCellLibrary/AOI211_X1
|
||||
report_lib_cell NangateOpenCellLibrary/AOI211_X2
|
||||
report_lib_cell NangateOpenCellLibrary/AOI211_X4
|
||||
puts "PASS: report AOI211 variants"
|
||||
|
||||
############################################################
|
||||
# OAI cells (complex OR-AND-INVERT functions)
|
||||
|
|
@ -68,23 +59,19 @@ puts "PASS: report AOI211 variants"
|
|||
report_lib_cell NangateOpenCellLibrary/OAI21_X1
|
||||
report_lib_cell NangateOpenCellLibrary/OAI21_X2
|
||||
report_lib_cell NangateOpenCellLibrary/OAI21_X4
|
||||
puts "PASS: report OAI21 variants"
|
||||
|
||||
# OAI22: !((A1|A2) & (B1|B2))
|
||||
report_lib_cell NangateOpenCellLibrary/OAI22_X1
|
||||
report_lib_cell NangateOpenCellLibrary/OAI22_X2
|
||||
report_lib_cell NangateOpenCellLibrary/OAI22_X4
|
||||
puts "PASS: report OAI22 variants"
|
||||
|
||||
# OAI211: !((A1|A2) & B & C)
|
||||
report_lib_cell NangateOpenCellLibrary/OAI211_X1
|
||||
report_lib_cell NangateOpenCellLibrary/OAI211_X2
|
||||
report_lib_cell NangateOpenCellLibrary/OAI211_X4
|
||||
puts "PASS: report OAI211 variants"
|
||||
|
||||
# OAI33: !((A1|A2|A3) & (B1|B2|B3))
|
||||
catch { report_lib_cell NangateOpenCellLibrary/OAI33_X1 }
|
||||
puts "PASS: report OAI33"
|
||||
report_lib_cell NangateOpenCellLibrary/OAI33_X1
|
||||
|
||||
############################################################
|
||||
# MUX cells (complex function: S?B:A)
|
||||
|
|
@ -92,35 +79,29 @@ puts "PASS: report OAI33"
|
|||
|
||||
report_lib_cell NangateOpenCellLibrary/MUX2_X1
|
||||
report_lib_cell NangateOpenCellLibrary/MUX2_X2
|
||||
puts "PASS: report MUX2 variants"
|
||||
|
||||
############################################################
|
||||
# Full/half adder (complex multi-output functions)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/FA_X1
|
||||
puts "PASS: report FA_X1 (full adder)"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/HA_X1
|
||||
puts "PASS: report HA_X1 (half adder)"
|
||||
|
||||
############################################################
|
||||
# Tristate cells (three_state enable)
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/TINV_X1
|
||||
puts "PASS: report TINV_X1 (tristate inv)"
|
||||
|
||||
catch { report_lib_cell NangateOpenCellLibrary/TBUF_X1 }
|
||||
catch { report_lib_cell NangateOpenCellLibrary/TBUF_X2 }
|
||||
puts "PASS: report TBUF tristate buffer"
|
||||
report_lib_cell NangateOpenCellLibrary/TBUF_X1
|
||||
report_lib_cell NangateOpenCellLibrary/TBUF_X2
|
||||
|
||||
############################################################
|
||||
# Special cells: antenna, filler, tie, clock gate
|
||||
############################################################
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/ANTENNA_X1
|
||||
puts "PASS: report ANTENNA_X1"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X1
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X2
|
||||
|
|
@ -128,17 +109,14 @@ report_lib_cell NangateOpenCellLibrary/FILLCELL_X4
|
|||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X8
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X16
|
||||
report_lib_cell NangateOpenCellLibrary/FILLCELL_X32
|
||||
puts "PASS: report FILLCELL variants"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/LOGIC0_X1
|
||||
report_lib_cell NangateOpenCellLibrary/LOGIC1_X1
|
||||
puts "PASS: report tie cells"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X1
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X2
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X4
|
||||
report_lib_cell NangateOpenCellLibrary/CLKGATETST_X8
|
||||
puts "PASS: report clock gate cells"
|
||||
|
||||
############################################################
|
||||
# Scan DFF cells (complex function with scan mux)
|
||||
|
|
@ -152,7 +130,6 @@ report_lib_cell NangateOpenCellLibrary/SDFFS_X1
|
|||
report_lib_cell NangateOpenCellLibrary/SDFFS_X2
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFRS_X1
|
||||
report_lib_cell NangateOpenCellLibrary/SDFFRS_X2
|
||||
puts "PASS: report scan DFF variants"
|
||||
|
||||
############################################################
|
||||
# Write liberty to exercise FuncExpr::to_string for all types
|
||||
|
|
@ -160,75 +137,64 @@ puts "PASS: report scan DFF variants"
|
|||
|
||||
set outfile1 [make_result_file liberty_func_expr_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile1
|
||||
puts "PASS: write_liberty (exercises FuncExpr::to_string)"
|
||||
|
||||
############################################################
|
||||
# Read IHP library (different function syntax/features)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP library"
|
||||
|
||||
# IHP has different cell naming and function formats
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_buf_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand2_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nor2_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xor2_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xnor2_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2 }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_antn }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_tiehi }
|
||||
catch { report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_tielo }
|
||||
puts "PASS: IHP cell reports"
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_inv_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_buf_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nand2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_nor2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xor2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_xnor2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_mux2_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_dfrbp_1
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_ebufn_2
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_antn
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_tiehi
|
||||
report_lib_cell sg13g2_stdcell_typ_1p20V_25C/sg13g2_tielo
|
||||
|
||||
set outfile2 [make_result_file liberty_func_expr_write_ihp.lib]
|
||||
sta::write_liberty sg13g2_stdcell_typ_1p20V_25C $outfile2
|
||||
puts "PASS: write_liberty IHP"
|
||||
|
||||
############################################################
|
||||
# Read Sky130 library (yet another function expression style)
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130"
|
||||
|
||||
# Sky130 has complex cells with different function expression styles
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a21o_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a21oi_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a22o_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a22oi_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a31o_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a32o_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o21a_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o21ai_0 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o22a_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__xor2_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__xnor2_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__fa_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ha_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__maj3_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1 }
|
||||
catch { report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1 }
|
||||
puts "PASS: Sky130 complex cell reports"
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a21o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a21oi_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a22o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a22oi_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a31o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__a32o_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o21a_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o21ai_0
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__o22a_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__xor2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__xnor2_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__fa_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ha_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__maj3_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1
|
||||
report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1
|
||||
|
||||
set outfile3 [make_result_file liberty_func_expr_write_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile3
|
||||
puts "PASS: write_liberty Sky130"
|
||||
|
||||
############################################################
|
||||
# Timing path reports through complex cells
|
||||
############################################################
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks"
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1] -path_delay min
|
||||
puts "PASS: report_checks min delay"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,9 +1,4 @@
|
|||
PASS: read Sky130 library
|
||||
--- leakage power queries ---
|
||||
PASS: combinational cell leakage
|
||||
PASS: sequential cell leakage
|
||||
PASS: tristate cell leakage
|
||||
PASS: clock gate cell leakage
|
||||
--- detailed cell reports ---
|
||||
Cell sky130_fd_sc_hd__inv_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
|
|
@ -14,7 +9,6 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
VPWR power
|
||||
A input 0.00-0.00
|
||||
Y output function=!A
|
||||
PASS: report inv_1
|
||||
Cell sky130_fd_sc_hd__nand2_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -25,7 +19,6 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
A input 0.00-0.00
|
||||
B input 0.00-0.00
|
||||
Y output function=!A+!B
|
||||
PASS: report nand2_1
|
||||
Cell sky130_fd_sc_hd__dfxtp_1
|
||||
Library sky130_fd_sc_hd__tt_025C_1v80
|
||||
File ../../test/sky130hd/sky130hd_tt.lib
|
||||
|
|
@ -38,11 +31,7 @@ File ../../test/sky130hd/sky130hd_tt.lib
|
|||
CLK input 0.00-0.00
|
||||
D input 0.00-0.00
|
||||
Q output function=IQ
|
||||
PASS: report dfxtp_1
|
||||
PASS: read Nangate45
|
||||
PASS: Nangate cell leakage
|
||||
Warning: liberty_leakage_power_deep.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
PASS: design setup
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
|
|
@ -54,7 +43,6 @@ Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
|||
----------------------------------------------------------------
|
||||
Total 1.88e-06 7.80e-08 3.61e-07 2.32e-06 100.0%
|
||||
81.1% 3.4% 15.5%
|
||||
PASS: report_power
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------------------------------------------
|
||||
|
|
@ -66,53 +54,39 @@ Pad 0.00000000e+00 0.00000000e+00 0.00000000e+00 0.00000000e+00
|
|||
--------------------------------------------------------------------------------
|
||||
Total 1.88477998e-06 7.79815039e-08 3.60756701e-07 2.32351817e-06 100.0%
|
||||
81.1% 3.4% 15.5%
|
||||
PASS: report_power -digits 8
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.69e-08 1.13e-08 2.14e-08 5.96e-08 buf1
|
||||
PASS: report_power buf1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
1.68e-08 5.90e-09 1.44e-08 3.71e-08 inv1
|
||||
PASS: report_power inv1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.56e-08 2.00e-08 2.51e-08 7.07e-08 and1
|
||||
PASS: report_power and1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
2.59e-08 2.01e-08 2.27e-08 6.87e-08 or1
|
||||
PASS: report_power or1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
1.24e-08 6.90e-09 2.18e-08 4.11e-08 nand1
|
||||
PASS: report_power nand1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
1.46e-08 6.90e-09 1.97e-08 4.11e-08 nor1
|
||||
PASS: report_power nor1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 6.90e-09 7.86e-08 6.73e-07 reg1
|
||||
PASS: report_power reg1
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.89e-07 0.00e+00 7.84e-08 6.67e-07 reg2
|
||||
PASS: report_power reg2
|
||||
Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
--------------------------------------------
|
||||
5.87e-07 0.00e+00 7.86e-08 6.65e-07 reg3
|
||||
PASS: report_power reg3
|
||||
PASS: read IHP
|
||||
PASS: IHP leakage queries
|
||||
PASS: write_liberty sky130 with power
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@ source ../../test/helpers.tcl
|
|||
# Read Sky130 library (has leakage_power groups with when conditions)
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read Sky130 library"
|
||||
|
||||
############################################################
|
||||
# Query leakage power on various cell types
|
||||
|
|
@ -44,7 +43,6 @@ foreach cell_name {sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: combinational cell leakage"
|
||||
|
||||
# Sequential cells (these have more leakage states)
|
||||
foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
|
||||
|
|
@ -61,7 +59,6 @@ foreach cell_name {sky130_fd_sc_hd__dfxtp_1 sky130_fd_sc_hd__dfxtp_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: sequential cell leakage"
|
||||
|
||||
# Tristate cells
|
||||
foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
|
||||
|
|
@ -74,7 +71,6 @@ foreach cell_name {sky130_fd_sc_hd__ebufn_1 sky130_fd_sc_hd__ebufn_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: tristate cell leakage"
|
||||
|
||||
# Clock gate cells
|
||||
foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
|
||||
|
|
@ -87,7 +83,6 @@ foreach cell_name {sky130_fd_sc_hd__dlclkp_1 sky130_fd_sc_hd__dlclkp_2
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: clock gate cell leakage"
|
||||
|
||||
############################################################
|
||||
# Report lib cells to exercise detailed leakage/power info
|
||||
|
|
@ -95,19 +90,15 @@ puts "PASS: clock gate cell leakage"
|
|||
puts "--- detailed cell reports ---"
|
||||
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__inv_1}
|
||||
puts "PASS: report inv_1"
|
||||
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__nand2_1}
|
||||
puts "PASS: report nand2_1"
|
||||
|
||||
catch {report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1}
|
||||
puts "PASS: report dfxtp_1"
|
||||
|
||||
############################################################
|
||||
# Read Nangate library for internal power with when conditions
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45"
|
||||
|
||||
# Query Nangate cell leakage
|
||||
foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
|
||||
|
|
@ -124,7 +115,6 @@ foreach cell_name {INV_X1 INV_X2 INV_X4 BUF_X1 BUF_X2 BUF_X4
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: Nangate cell leakage"
|
||||
|
||||
############################################################
|
||||
# Link design and run power analysis to exercise internal power
|
||||
|
|
@ -137,20 +127,16 @@ create_clock -name clk2 -period 20 [get_ports clk2]
|
|||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: design setup"
|
||||
|
||||
# Power reports exercise internal power evaluation
|
||||
report_power
|
||||
puts "PASS: report_power"
|
||||
|
||||
report_power -digits 8
|
||||
puts "PASS: report_power -digits 8"
|
||||
|
||||
# Per-instance power
|
||||
foreach inst_name {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3} {
|
||||
catch {
|
||||
report_power -instances [get_cells $inst_name]
|
||||
puts "PASS: report_power $inst_name"
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -158,7 +144,6 @@ foreach inst_name {buf1 inv1 and1 or1 nand1 nor1 reg1 reg2 reg3} {
|
|||
# Read IHP library for different power model format
|
||||
############################################################
|
||||
read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
|
||||
puts "PASS: read IHP"
|
||||
|
||||
foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
|
||||
sg13g2_nor2_1 sg13g2_and2_1 sg13g2_or2_1} {
|
||||
|
|
@ -171,7 +156,6 @@ foreach cell_name {sg13g2_inv_1 sg13g2_buf_1 sg13g2_nand2_1
|
|||
}
|
||||
}
|
||||
}
|
||||
puts "PASS: IHP leakage queries"
|
||||
|
||||
############################################################
|
||||
# Write liberty roundtrip for Sky130 (exercises power writer)
|
||||
|
|
@ -179,7 +163,4 @@ puts "PASS: IHP leakage queries"
|
|||
set outfile [make_result_file liberty_leakage_power_deep_write.lib]
|
||||
catch {
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile
|
||||
puts "PASS: write_liberty sky130 with power"
|
||||
}
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,10 +1,3 @@
|
|||
PASS: multi-corner liberty read
|
||||
PASS: fast library loaded
|
||||
PASS: slow library loaded
|
||||
PASS: fast INV_X1 found
|
||||
PASS: slow INV_X1 found
|
||||
PASS: link_design
|
||||
PASS: constraints set
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -32,7 +25,6 @@ Corner: fast
|
|||
6.95 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -corner fast
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -60,11 +52,9 @@ Corner: slow
|
|||
6.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -corner slow
|
||||
Clock Period Waveform
|
||||
----------------------------------------------------
|
||||
clk 10.00 0.00 5.00
|
||||
PASS: report_clock_properties
|
||||
Startpoint: in1 (input port clocked by clk)
|
||||
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -94,7 +84,6 @@ Corner: fast
|
|||
2.01 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -corner fast -path_delay min
|
||||
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
||||
Endpoint: out1 (output port clocked by clk)
|
||||
Path Group: clk
|
||||
|
|
@ -122,7 +111,6 @@ Corner: slow
|
|||
6.71 slack (MET)
|
||||
|
||||
|
||||
PASS: report_checks -corner slow -path_delay max
|
||||
Cell BUF_X1
|
||||
Library NangateOpenCellLibrary_fast
|
||||
File ../../test/nangate45/Nangate45_fast.lib
|
||||
|
|
@ -130,7 +118,6 @@ File ../../test/nangate45/Nangate45_fast.lib
|
|||
VSS ground
|
||||
A input 0.91-0.98
|
||||
Z output function=A
|
||||
PASS: report_lib_cell fast BUF_X1
|
||||
Cell BUF_X1
|
||||
Library NangateOpenCellLibrary_slow
|
||||
File ../../test/nangate45/Nangate45_slow.lib
|
||||
|
|
@ -138,7 +125,6 @@ File ../../test/nangate45/Nangate45_slow.lib
|
|||
VSS ground
|
||||
A input 0.84-0.93
|
||||
Z output function=A
|
||||
PASS: report_lib_cell slow BUF_X1
|
||||
Cell DFF_X1
|
||||
Library NangateOpenCellLibrary_fast
|
||||
File ../../test/nangate45/Nangate45_fast.lib
|
||||
|
|
@ -150,7 +136,6 @@ File ../../test/nangate45/Nangate45_fast.lib
|
|||
CK input 0.89-0.97
|
||||
Q output function=IQ
|
||||
QN output function=IQN
|
||||
PASS: report_lib_cell fast DFF_X1
|
||||
Cell DFF_X1
|
||||
Library NangateOpenCellLibrary_slow
|
||||
File ../../test/nangate45/Nangate45_slow.lib
|
||||
|
|
@ -162,7 +147,3 @@ File ../../test/nangate45/Nangate45_slow.lib
|
|||
CK input 0.82-0.91
|
||||
Q output function=IQ
|
||||
QN output function=IQN
|
||||
PASS: report_lib_cell slow DFF_X1
|
||||
PASS: fast BUF_X1 pins (2 pins)
|
||||
PASS: slow BUF_X1 pins (2 pins)
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@ define_corners fast slow
|
|||
|
||||
read_liberty -corner fast ../../test/nangate45/Nangate45_fast.lib
|
||||
read_liberty -corner slow ../../test/nangate45/Nangate45_slow.lib
|
||||
puts "PASS: multi-corner liberty read"
|
||||
|
||||
# Verify both corners loaded
|
||||
set fast_lib [get_libs NangateOpenCellLibrary_fast]
|
||||
|
|
@ -11,14 +10,12 @@ if { $fast_lib == "" } {
|
|||
puts "FAIL: fast library not found"
|
||||
exit 1
|
||||
}
|
||||
puts "PASS: fast library loaded"
|
||||
|
||||
set slow_lib [get_libs NangateOpenCellLibrary_slow]
|
||||
if { $slow_lib == "" } {
|
||||
puts "FAIL: slow library not found"
|
||||
exit 1
|
||||
}
|
||||
puts "PASS: slow library loaded"
|
||||
|
||||
# Query cells in each corner
|
||||
set fast_inv [get_lib_cells NangateOpenCellLibrary_fast/INV_X1]
|
||||
|
|
@ -26,62 +23,45 @@ if { $fast_inv == "" } {
|
|||
puts "FAIL: fast INV_X1 not found"
|
||||
exit 1
|
||||
}
|
||||
puts "PASS: fast INV_X1 found"
|
||||
|
||||
set slow_inv [get_lib_cells NangateOpenCellLibrary_slow/INV_X1]
|
||||
if { $slow_inv == "" } {
|
||||
puts "FAIL: slow INV_X1 not found"
|
||||
exit 1
|
||||
}
|
||||
puts "PASS: slow INV_X1 found"
|
||||
|
||||
# Read verilog and link
|
||||
read_verilog ../../sdc/test/sdc_test1.v
|
||||
link_design sdc_test1
|
||||
puts "PASS: link_design"
|
||||
|
||||
# Setup constraints
|
||||
create_clock -name clk -period 10 [get_ports clk]
|
||||
set_input_delay -clock clk 2.0 [get_ports in1]
|
||||
set_output_delay -clock clk 3.0 [get_ports out1]
|
||||
puts "PASS: constraints set"
|
||||
|
||||
# Report for each corner
|
||||
report_checks -corner fast
|
||||
puts "PASS: report_checks -corner fast"
|
||||
|
||||
report_checks -corner slow
|
||||
puts "PASS: report_checks -corner slow"
|
||||
|
||||
# Report clock properties
|
||||
report_clock_properties
|
||||
puts "PASS: report_clock_properties"
|
||||
|
||||
# Report with path details
|
||||
report_checks -corner fast -path_delay min
|
||||
puts "PASS: report_checks -corner fast -path_delay min"
|
||||
|
||||
report_checks -corner slow -path_delay max
|
||||
puts "PASS: report_checks -corner slow -path_delay max"
|
||||
|
||||
# Query lib cells from both corners
|
||||
report_lib_cell NangateOpenCellLibrary_fast/BUF_X1
|
||||
puts "PASS: report_lib_cell fast BUF_X1"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary_slow/BUF_X1
|
||||
puts "PASS: report_lib_cell slow BUF_X1"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary_fast/DFF_X1
|
||||
puts "PASS: report_lib_cell fast DFF_X1"
|
||||
|
||||
report_lib_cell NangateOpenCellLibrary_slow/DFF_X1
|
||||
puts "PASS: report_lib_cell slow DFF_X1"
|
||||
|
||||
# Get lib pins from both corners
|
||||
set fast_buf_pins [get_lib_pins NangateOpenCellLibrary_fast/BUF_X1/*]
|
||||
puts "PASS: fast BUF_X1 pins ([llength $fast_buf_pins] pins)"
|
||||
|
||||
set slow_buf_pins [get_lib_pins NangateOpenCellLibrary_slow/BUF_X1/*]
|
||||
puts "PASS: slow BUF_X1 pins ([llength $slow_buf_pins] pins)"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,54 +0,0 @@
|
|||
PASS: read Nangate45 typ
|
||||
PASS: read Nangate45 fast
|
||||
PASS: read Nangate45 slow
|
||||
PASS: make_equiv_cells typ
|
||||
PASS: find_equiv_cells INV_X1 typ (6 equivs)
|
||||
PASS: find_equiv_cells BUF_X1 typ (9 equivs)
|
||||
PASS: find_equiv_cells NAND2_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells NAND3_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells NAND4_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells NOR2_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells NOR3_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells NOR4_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells AND2_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells OR2_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells AOI21_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells OAI21_X1 typ (3 equivs)
|
||||
PASS: find_equiv_cells DFF_X1 typ (2 equivs)
|
||||
PASS: find_equiv_cells SDFF_X1 typ (2 equivs)
|
||||
PASS: find_equiv_cells CLKBUF_X1 typ (9 equivs)
|
||||
PASS: find_equiv_cells XOR2_X1 typ (2 equivs)
|
||||
PASS: equiv_cells typ/fast INV_X1 = 1
|
||||
PASS: equiv_cells typ/slow INV_X1 = 1
|
||||
PASS: equiv_cells fast/slow INV_X1 = 1
|
||||
PASS: equiv_cells typ/fast BUF_X1 = 1
|
||||
PASS: equiv_cells typ/fast NAND2_X1 = 1
|
||||
PASS: equiv_cells typ/fast DFF_X1 = 1
|
||||
PASS: equiv_cell_ports typ/fast INV_X1 = 1
|
||||
PASS: equiv_cell_ports typ/fast BUF_X1 = 1
|
||||
PASS: equiv_cell_ports INV_X1 vs BUF_X1 = 0
|
||||
PASS: equiv_cell_ports NAND2_X1 vs NAND3_X1 = 0
|
||||
PASS: equiv_cell_timing_arcs typ/fast INV_X1 = 1
|
||||
PASS: equiv_cell_timing_arcs typ/fast BUF_X1 = 1
|
||||
PASS: equiv_cell_timing_arcs INV_X1 vs BUF_X1 = 0
|
||||
PASS: find_library_buffers typ (9 buffers)
|
||||
PASS: find_library_buffers fast (9 buffers)
|
||||
PASS: find_library_buffers slow (9 buffers)
|
||||
PASS: equiv_cells INV_X1/X2 = 1
|
||||
PASS: equiv_cells INV_X1/X4 = 1
|
||||
PASS: equiv_cells INV_X1/X8 = 1
|
||||
PASS: equiv_cells INV_X1/X16 = 1
|
||||
PASS: equiv_cells INV_X1/X32 = 1
|
||||
PASS: equiv_cells NAND2/NOR2 = 0
|
||||
PASS: equiv_cells AND2/OR2 = 0
|
||||
PASS: equiv_cells AOI21/OAI21 = 0
|
||||
PASS: equiv_cells DFF/DFFR = 0
|
||||
PASS: equiv_cells DFF/DFFS = 0
|
||||
PASS: equiv_cells DFFR/DFFRS = 0
|
||||
PASS: read Nangate45 LVT
|
||||
PASS: make_equiv_cells lvt
|
||||
PASS: find_equiv_cells LVT INV_X1_L (6 equivs)
|
||||
PASS: find_library_buffers LVT (9 buffers)
|
||||
PASS: equiv_cells typ/lvt INV_X1 vs INV_X1_L = 1
|
||||
PASS: equiv_cell_ports typ/lvt INV_X1 vs INV_X1_L = 1
|
||||
ALL PASSED
|
||||
|
|
@ -10,13 +10,10 @@ source ../../test/helpers.tcl
|
|||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45 typ"
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
puts "PASS: read Nangate45 fast"
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_slow.lib
|
||||
puts "PASS: read Nangate45 slow"
|
||||
|
||||
############################################################
|
||||
# Make equiv cells for typ library
|
||||
|
|
@ -24,7 +21,6 @@ puts "PASS: read Nangate45 slow"
|
|||
|
||||
set typ_lib [lindex [get_libs NangateOpenCellLibrary] 0]
|
||||
sta::make_equiv_cells $typ_lib
|
||||
puts "PASS: make_equiv_cells typ"
|
||||
|
||||
############################################################
|
||||
# Find equiv cells in typ library (various cell families)
|
||||
|
|
@ -32,115 +28,67 @@ puts "PASS: make_equiv_cells typ"
|
|||
|
||||
# INV family
|
||||
set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
catch {
|
||||
set inv_equivs [sta::find_equiv_cells $inv_x1]
|
||||
puts "PASS: find_equiv_cells INV_X1 typ ([llength $inv_equivs] equivs)"
|
||||
}
|
||||
set inv_equivs [sta::find_equiv_cells $inv_x1]
|
||||
|
||||
# BUF family
|
||||
set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
catch {
|
||||
set buf_equivs [sta::find_equiv_cells $buf_x1]
|
||||
puts "PASS: find_equiv_cells BUF_X1 typ ([llength $buf_equivs] equivs)"
|
||||
}
|
||||
set buf_equivs [sta::find_equiv_cells $buf_x1]
|
||||
|
||||
# NAND2 family
|
||||
set nand2_x1 [get_lib_cell NangateOpenCellLibrary/NAND2_X1]
|
||||
catch {
|
||||
set nand2_equivs [sta::find_equiv_cells $nand2_x1]
|
||||
puts "PASS: find_equiv_cells NAND2_X1 typ ([llength $nand2_equivs] equivs)"
|
||||
}
|
||||
set nand2_equivs [sta::find_equiv_cells $nand2_x1]
|
||||
|
||||
# NAND3 family
|
||||
set nand3_x1 [get_lib_cell NangateOpenCellLibrary/NAND3_X1]
|
||||
catch {
|
||||
set nand3_equivs [sta::find_equiv_cells $nand3_x1]
|
||||
puts "PASS: find_equiv_cells NAND3_X1 typ ([llength $nand3_equivs] equivs)"
|
||||
}
|
||||
set nand3_equivs [sta::find_equiv_cells $nand3_x1]
|
||||
|
||||
# NAND4 family
|
||||
set nand4_x1 [get_lib_cell NangateOpenCellLibrary/NAND4_X1]
|
||||
catch {
|
||||
set nand4_equivs [sta::find_equiv_cells $nand4_x1]
|
||||
puts "PASS: find_equiv_cells NAND4_X1 typ ([llength $nand4_equivs] equivs)"
|
||||
}
|
||||
set nand4_equivs [sta::find_equiv_cells $nand4_x1]
|
||||
|
||||
# NOR2 family
|
||||
set nor2_x1 [get_lib_cell NangateOpenCellLibrary/NOR2_X1]
|
||||
catch {
|
||||
set nor2_equivs [sta::find_equiv_cells $nor2_x1]
|
||||
puts "PASS: find_equiv_cells NOR2_X1 typ ([llength $nor2_equivs] equivs)"
|
||||
}
|
||||
set nor2_equivs [sta::find_equiv_cells $nor2_x1]
|
||||
|
||||
# NOR3 family
|
||||
set nor3_x1 [get_lib_cell NangateOpenCellLibrary/NOR3_X1]
|
||||
catch {
|
||||
set nor3_equivs [sta::find_equiv_cells $nor3_x1]
|
||||
puts "PASS: find_equiv_cells NOR3_X1 typ ([llength $nor3_equivs] equivs)"
|
||||
}
|
||||
set nor3_equivs [sta::find_equiv_cells $nor3_x1]
|
||||
|
||||
# NOR4 family
|
||||
set nor4_x1 [get_lib_cell NangateOpenCellLibrary/NOR4_X1]
|
||||
catch {
|
||||
set nor4_equivs [sta::find_equiv_cells $nor4_x1]
|
||||
puts "PASS: find_equiv_cells NOR4_X1 typ ([llength $nor4_equivs] equivs)"
|
||||
}
|
||||
set nor4_equivs [sta::find_equiv_cells $nor4_x1]
|
||||
|
||||
# AND2 family
|
||||
set and2_x1 [get_lib_cell NangateOpenCellLibrary/AND2_X1]
|
||||
catch {
|
||||
set and2_equivs [sta::find_equiv_cells $and2_x1]
|
||||
puts "PASS: find_equiv_cells AND2_X1 typ ([llength $and2_equivs] equivs)"
|
||||
}
|
||||
set and2_equivs [sta::find_equiv_cells $and2_x1]
|
||||
|
||||
# OR2 family
|
||||
set or2_x1 [get_lib_cell NangateOpenCellLibrary/OR2_X1]
|
||||
catch {
|
||||
set or2_equivs [sta::find_equiv_cells $or2_x1]
|
||||
puts "PASS: find_equiv_cells OR2_X1 typ ([llength $or2_equivs] equivs)"
|
||||
}
|
||||
set or2_equivs [sta::find_equiv_cells $or2_x1]
|
||||
|
||||
# AOI21 family
|
||||
set aoi21_x1 [get_lib_cell NangateOpenCellLibrary/AOI21_X1]
|
||||
catch {
|
||||
set aoi21_equivs [sta::find_equiv_cells $aoi21_x1]
|
||||
puts "PASS: find_equiv_cells AOI21_X1 typ ([llength $aoi21_equivs] equivs)"
|
||||
}
|
||||
set aoi21_equivs [sta::find_equiv_cells $aoi21_x1]
|
||||
|
||||
# OAI21 family
|
||||
set oai21_x1 [get_lib_cell NangateOpenCellLibrary/OAI21_X1]
|
||||
catch {
|
||||
set oai21_equivs [sta::find_equiv_cells $oai21_x1]
|
||||
puts "PASS: find_equiv_cells OAI21_X1 typ ([llength $oai21_equivs] equivs)"
|
||||
}
|
||||
set oai21_equivs [sta::find_equiv_cells $oai21_x1]
|
||||
|
||||
# DFF family
|
||||
set dff_x1 [get_lib_cell NangateOpenCellLibrary/DFF_X1]
|
||||
catch {
|
||||
set dff_equivs [sta::find_equiv_cells $dff_x1]
|
||||
puts "PASS: find_equiv_cells DFF_X1 typ ([llength $dff_equivs] equivs)"
|
||||
}
|
||||
set dff_equivs [sta::find_equiv_cells $dff_x1]
|
||||
|
||||
# SDFF family
|
||||
set sdff_x1 [get_lib_cell NangateOpenCellLibrary/SDFF_X1]
|
||||
catch {
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_x1]
|
||||
puts "PASS: find_equiv_cells SDFF_X1 typ ([llength $sdff_equivs] equivs)"
|
||||
}
|
||||
set sdff_equivs [sta::find_equiv_cells $sdff_x1]
|
||||
|
||||
# CLKBUF family
|
||||
set clkbuf_x1 [get_lib_cell NangateOpenCellLibrary/CLKBUF_X1]
|
||||
catch {
|
||||
set clkbuf_equivs [sta::find_equiv_cells $clkbuf_x1]
|
||||
puts "PASS: find_equiv_cells CLKBUF_X1 typ ([llength $clkbuf_equivs] equivs)"
|
||||
}
|
||||
set clkbuf_equivs [sta::find_equiv_cells $clkbuf_x1]
|
||||
|
||||
# XOR2 family
|
||||
set xor2_x1 [get_lib_cell NangateOpenCellLibrary/XOR2_X1]
|
||||
catch {
|
||||
set xor2_equivs [sta::find_equiv_cells $xor2_x1]
|
||||
puts "PASS: find_equiv_cells XOR2_X1 typ ([llength $xor2_equivs] equivs)"
|
||||
}
|
||||
set xor2_equivs [sta::find_equiv_cells $xor2_x1]
|
||||
|
||||
############################################################
|
||||
# Cross-library equiv_cells comparisons
|
||||
|
|
@ -150,73 +98,57 @@ set fast_inv_x1 [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
|||
set slow_inv_x1 [get_lib_cell NangateOpenCellLibrary_slow/INV_X1]
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $fast_inv_x1]
|
||||
puts "PASS: equiv_cells typ/fast INV_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $slow_inv_x1]
|
||||
puts "PASS: equiv_cells typ/slow INV_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cells $fast_inv_x1 $slow_inv_x1]
|
||||
puts "PASS: equiv_cells fast/slow INV_X1 = $result"
|
||||
|
||||
# Cross-library BUF
|
||||
set fast_buf_x1 [get_lib_cell NangateOpenCellLibrary_fast/BUF_X1]
|
||||
set result [sta::equiv_cells $buf_x1 $fast_buf_x1]
|
||||
puts "PASS: equiv_cells typ/fast BUF_X1 = $result"
|
||||
|
||||
# Cross-library NAND2
|
||||
set fast_nand2_x1 [get_lib_cell NangateOpenCellLibrary_fast/NAND2_X1]
|
||||
set result [sta::equiv_cells $nand2_x1 $fast_nand2_x1]
|
||||
puts "PASS: equiv_cells typ/fast NAND2_X1 = $result"
|
||||
|
||||
# Cross-library DFF
|
||||
set fast_dff_x1 [get_lib_cell NangateOpenCellLibrary_fast/DFF_X1]
|
||||
set result [sta::equiv_cells $dff_x1 $fast_dff_x1]
|
||||
puts "PASS: equiv_cells typ/fast DFF_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_ports cross-library
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $fast_inv_x1]
|
||||
puts "PASS: equiv_cell_ports typ/fast INV_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $buf_x1 $fast_buf_x1]
|
||||
puts "PASS: equiv_cell_ports typ/fast BUF_X1 = $result"
|
||||
|
||||
# Different function should NOT match
|
||||
set result [sta::equiv_cell_ports $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cell_ports INV_X1 vs BUF_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $nand2_x1 $nand3_x1]
|
||||
puts "PASS: equiv_cell_ports NAND2_X1 vs NAND3_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# equiv_cell_timing_arcs cross-library
|
||||
############################################################
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $fast_inv_x1]
|
||||
puts "PASS: equiv_cell_timing_arcs typ/fast INV_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $buf_x1 $fast_buf_x1]
|
||||
puts "PASS: equiv_cell_timing_arcs typ/fast BUF_X1 = $result"
|
||||
|
||||
set result [sta::equiv_cell_timing_arcs $inv_x1 $buf_x1]
|
||||
puts "PASS: equiv_cell_timing_arcs INV_X1 vs BUF_X1 = $result"
|
||||
|
||||
############################################################
|
||||
# Find library buffers for each library
|
||||
############################################################
|
||||
|
||||
set typ_buffers [sta::find_library_buffers $typ_lib]
|
||||
puts "PASS: find_library_buffers typ ([llength $typ_buffers] buffers)"
|
||||
|
||||
set fast_lib [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
set fast_buffers [sta::find_library_buffers $fast_lib]
|
||||
puts "PASS: find_library_buffers fast ([llength $fast_buffers] buffers)"
|
||||
|
||||
set slow_lib [lindex [get_libs NangateOpenCellLibrary_slow] 0]
|
||||
set slow_buffers [sta::find_library_buffers $slow_lib]
|
||||
puts "PASS: find_library_buffers slow ([llength $slow_buffers] buffers)"
|
||||
|
||||
############################################################
|
||||
# Additional equiv cells in typ library - within family
|
||||
|
|
@ -230,67 +162,46 @@ set inv_x16 [get_lib_cell NangateOpenCellLibrary/INV_X16]
|
|||
set inv_x32 [get_lib_cell NangateOpenCellLibrary/INV_X32]
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x2]
|
||||
puts "PASS: equiv_cells INV_X1/X2 = $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x4]
|
||||
puts "PASS: equiv_cells INV_X1/X4 = $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x8]
|
||||
puts "PASS: equiv_cells INV_X1/X8 = $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x16]
|
||||
puts "PASS: equiv_cells INV_X1/X16 = $result"
|
||||
|
||||
set result [sta::equiv_cells $inv_x1 $inv_x32]
|
||||
puts "PASS: equiv_cells INV_X1/X32 = $result"
|
||||
|
||||
# Different family comparisons
|
||||
set result [sta::equiv_cells $nand2_x1 $nor2_x1]
|
||||
puts "PASS: equiv_cells NAND2/NOR2 = $result"
|
||||
|
||||
set result [sta::equiv_cells $and2_x1 $or2_x1]
|
||||
puts "PASS: equiv_cells AND2/OR2 = $result"
|
||||
|
||||
set result [sta::equiv_cells $aoi21_x1 $oai21_x1]
|
||||
puts "PASS: equiv_cells AOI21/OAI21 = $result"
|
||||
|
||||
set dffr_x1 [get_lib_cell NangateOpenCellLibrary/DFFR_X1]
|
||||
set result [sta::equiv_cells $dff_x1 $dffr_x1]
|
||||
puts "PASS: equiv_cells DFF/DFFR = $result"
|
||||
|
||||
set dffs_x1 [get_lib_cell NangateOpenCellLibrary/DFFS_X1]
|
||||
set result [sta::equiv_cells $dff_x1 $dffs_x1]
|
||||
puts "PASS: equiv_cells DFF/DFFS = $result"
|
||||
|
||||
set dffrs_x1 [get_lib_cell NangateOpenCellLibrary/DFFRS_X1]
|
||||
set result [sta::equiv_cells $dffr_x1 $dffrs_x1]
|
||||
puts "PASS: equiv_cells DFFR/DFFRS = $result"
|
||||
|
||||
############################################################
|
||||
# Read LVT library and make equiv cells
|
||||
############################################################
|
||||
|
||||
read_liberty ../../test/nangate45/Nangate45_lvt.lib
|
||||
puts "PASS: read Nangate45 LVT"
|
||||
|
||||
set lvt_lib [lindex [get_libs NangateOpenCellLibrary_lvt] 0]
|
||||
sta::make_equiv_cells $lvt_lib
|
||||
puts "PASS: make_equiv_cells lvt"
|
||||
|
||||
set lvt_inv_x1 [get_lib_cell NangateOpenCellLibrary_lvt/INV_X1_L]
|
||||
catch {
|
||||
set lvt_inv_equivs [sta::find_equiv_cells $lvt_inv_x1]
|
||||
puts "PASS: find_equiv_cells LVT INV_X1_L ([llength $lvt_inv_equivs] equivs)"
|
||||
}
|
||||
set lvt_inv_equivs [sta::find_equiv_cells $lvt_inv_x1]
|
||||
|
||||
set lvt_buffers [sta::find_library_buffers $lvt_lib]
|
||||
puts "PASS: find_library_buffers LVT ([llength $lvt_buffers] buffers)"
|
||||
|
||||
# Cross library with LVT (different cell naming so not equiv)
|
||||
set result [sta::equiv_cells $inv_x1 $lvt_inv_x1]
|
||||
puts "PASS: equiv_cells typ/lvt INV_X1 vs INV_X1_L = $result"
|
||||
|
||||
set result [sta::equiv_cell_ports $inv_x1 $lvt_inv_x1]
|
||||
puts "PASS: equiv_cell_ports typ/lvt INV_X1 vs INV_X1_L = $result"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
|
|
@ -1,57 +1,8 @@
|
|||
PASS: read Nangate45_typ
|
||||
PASS: find_operating_conditions typical found
|
||||
PASS: default_operating_conditions found
|
||||
Warning: liberty_opcond_scale.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
|
||||
PASS: basic design setup
|
||||
PASS: set_operating_conditions typical
|
||||
No paths found.
|
||||
PASS: report_checks with operating conditions
|
||||
PASS: find_liberty_cell INV_X1
|
||||
PASS: find_liberty_cell BUF_X1
|
||||
PASS: INV_X1 is_inverter = 1
|
||||
PASS: INV_X1 is_buffer = 0
|
||||
PASS: BUF_X1 is_buffer = 1
|
||||
PASS: BUF_X1 is_inverter = 0
|
||||
PASS: DFF_X1 is_leaf = 1
|
||||
PASS: liberty_library from cell: NangateOpenCellLibrary
|
||||
PASS: find_liberty_cells_matching INV* = 6
|
||||
PASS: find_liberty_cells_matching BUF* = 6
|
||||
PASS: find_liberty_cells_matching DFF* = 8
|
||||
PASS: find_liberty_cells_matching SDFF* = 8
|
||||
PASS: find_liberty_cells_matching * = 134
|
||||
PASS: find_liberty_ports_matching INV_X1/* = 4
|
||||
PASS: find_liberty_ports_matching DFF_X1/* = 8
|
||||
PASS: INV_X1 timing_arc_sets count = 1
|
||||
PASS: DFF_X1 timing_arc_sets count = 5
|
||||
PASS: CLKGATETST_X1 timing_arc_sets count = 9
|
||||
PASS: find_liberty_port INV_X1/A
|
||||
PASS: find_liberty_port INV_X1/ZN
|
||||
PASS: find_liberty_port DFF_X1/CK
|
||||
PASS: find_liberty_port DFF_X1/D
|
||||
PASS: find_liberty_port DFF_X1/Q
|
||||
PASS: liberty_port_iterator INV_X1 ports = 4
|
||||
PASS: liberty_port_iterator DFF_X1 ports = 8
|
||||
PASS: find_wireload 1K_hvratio_1_1
|
||||
INFO: wireload selection not found
|
||||
PASS: read sky130
|
||||
PASS: sky130 find_operating_conditions
|
||||
PASS: sky130 default_operating_conditions
|
||||
PASS: read Nangate45_fast
|
||||
PASS: read sky130 ff
|
||||
PASS: read sky130 ss
|
||||
No paths found.
|
||||
PASS: report_checks multi-library
|
||||
PASS: set_timing_derate
|
||||
No paths found.
|
||||
PASS: report_checks with derate
|
||||
PASS: write_liberty NangateOpenCellLibrary
|
||||
PASS: write_liberty sky130
|
||||
PASS: make_equiv_cells lib1
|
||||
PASS: make_equiv_cells lib2
|
||||
PASS: equiv_cells typ vs fast INV_X1 = 1
|
||||
PASS: equiv_cells typ vs fast BUF_X1 = 1
|
||||
PASS: equiv_cell_ports typ vs fast = 1
|
||||
PASS: equiv_cell_timing_arcs typ vs fast = 1
|
||||
max slew
|
||||
|
||||
Pin inv1/ZN ^
|
||||
|
|
@ -68,5 +19,3 @@ capacitance 1.16
|
|||
-----------------------
|
||||
Slack 25.55 (MET)
|
||||
|
||||
PASS: report_check_types verbose
|
||||
ALL PASSED
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@ source ../../test/helpers.tcl
|
|||
# Read Nangate45 library - has operating conditions
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_typ.lib
|
||||
puts "PASS: read Nangate45_typ"
|
||||
|
||||
set lib [sta::find_liberty NangateOpenCellLibrary]
|
||||
|
||||
|
|
@ -25,14 +24,12 @@ set lib [sta::find_liberty NangateOpenCellLibrary]
|
|||
############################################################
|
||||
set op_cond [$lib find_operating_conditions typical]
|
||||
if { $op_cond != "NULL" } {
|
||||
puts "PASS: find_operating_conditions typical found"
|
||||
} else {
|
||||
puts "INFO: no operating_conditions named typical"
|
||||
}
|
||||
|
||||
set def_op [$lib default_operating_conditions]
|
||||
if { $def_op != "NULL" } {
|
||||
puts "PASS: default_operating_conditions found"
|
||||
} else {
|
||||
puts "INFO: no default operating conditions"
|
||||
}
|
||||
|
|
@ -48,106 +45,78 @@ create_clock -name clk2 -period 20 [get_ports clk2]
|
|||
set_input_delay -clock clk1 2.0 [all_inputs]
|
||||
set_output_delay -clock clk1 3.0 [all_outputs]
|
||||
set_input_transition 0.1 [all_inputs]
|
||||
puts "PASS: basic design setup"
|
||||
|
||||
catch {
|
||||
set_operating_conditions typical
|
||||
puts "PASS: set_operating_conditions typical"
|
||||
} msg
|
||||
set_operating_conditions typical
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks with operating conditions"
|
||||
|
||||
############################################################
|
||||
# Library cell classification queries
|
||||
# Exercises: inverters(), buffers(), isBuffer(), isInverter()
|
||||
############################################################
|
||||
set inv_cell [sta::find_liberty_cell INV_X1]
|
||||
puts "PASS: find_liberty_cell INV_X1"
|
||||
|
||||
set buf_cell [sta::find_liberty_cell BUF_X1]
|
||||
puts "PASS: find_liberty_cell BUF_X1"
|
||||
|
||||
set inv_is_inv [$inv_cell is_inverter]
|
||||
puts "PASS: INV_X1 is_inverter = $inv_is_inv"
|
||||
|
||||
set inv_is_buf [$inv_cell is_buffer]
|
||||
puts "PASS: INV_X1 is_buffer = $inv_is_buf"
|
||||
|
||||
set buf_is_buf [$buf_cell is_buffer]
|
||||
puts "PASS: BUF_X1 is_buffer = $buf_is_buf"
|
||||
|
||||
set buf_is_inv [$buf_cell is_inverter]
|
||||
puts "PASS: BUF_X1 is_inverter = $buf_is_inv"
|
||||
|
||||
# Test is_leaf on various cells
|
||||
set dff_cell [sta::find_liberty_cell DFF_X1]
|
||||
set dff_leaf [$dff_cell is_leaf]
|
||||
puts "PASS: DFF_X1 is_leaf = $dff_leaf"
|
||||
|
||||
# Liberty library accessor on cell
|
||||
set cell_lib [$inv_cell liberty_library]
|
||||
puts "PASS: liberty_library from cell: [$cell_lib name]"
|
||||
|
||||
############################################################
|
||||
# Pattern matching on liberty cells
|
||||
# Exercises: findLibertyCellsMatching, findLibertyPortsMatching
|
||||
############################################################
|
||||
set inv_matches [$lib find_liberty_cells_matching "INV*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching INV* = [llength $inv_matches]"
|
||||
|
||||
set buf_matches [$lib find_liberty_cells_matching "BUF*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching BUF* = [llength $buf_matches]"
|
||||
|
||||
set dff_matches [$lib find_liberty_cells_matching "DFF*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching DFF* = [llength $dff_matches]"
|
||||
|
||||
set sdff_matches [$lib find_liberty_cells_matching "SDFF*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching SDFF* = [llength $sdff_matches]"
|
||||
|
||||
set all_matches [$lib find_liberty_cells_matching "*" 0 0]
|
||||
puts "PASS: find_liberty_cells_matching * = [llength $all_matches]"
|
||||
|
||||
# Port pattern matching
|
||||
set inv_port_matches [$inv_cell find_liberty_ports_matching "*" 0 0]
|
||||
puts "PASS: find_liberty_ports_matching INV_X1/* = [llength $inv_port_matches]"
|
||||
|
||||
set dff_port_matches [$dff_cell find_liberty_ports_matching "*" 0 0]
|
||||
puts "PASS: find_liberty_ports_matching DFF_X1/* = [llength $dff_port_matches]"
|
||||
|
||||
############################################################
|
||||
# Timing arc queries on cells
|
||||
# Exercises: timingArcSets, timingArcSetCount, hasTimingArcs
|
||||
############################################################
|
||||
set inv_arc_sets [$inv_cell timing_arc_sets]
|
||||
puts "PASS: INV_X1 timing_arc_sets count = [llength $inv_arc_sets]"
|
||||
|
||||
set dff_arc_sets [$dff_cell timing_arc_sets]
|
||||
puts "PASS: DFF_X1 timing_arc_sets count = [llength $dff_arc_sets]"
|
||||
|
||||
# Check timing arc set ports
|
||||
set clkgate_cell [sta::find_liberty_cell CLKGATETST_X1]
|
||||
set clkgate_arcs [$clkgate_cell timing_arc_sets]
|
||||
puts "PASS: CLKGATETST_X1 timing_arc_sets count = [llength $clkgate_arcs]"
|
||||
|
||||
############################################################
|
||||
# Find port on liberty cell
|
||||
# Exercises: findLibertyPort
|
||||
############################################################
|
||||
set inv_a [$inv_cell find_liberty_port A]
|
||||
puts "PASS: find_liberty_port INV_X1/A"
|
||||
|
||||
set inv_zn [$inv_cell find_liberty_port ZN]
|
||||
puts "PASS: find_liberty_port INV_X1/ZN"
|
||||
|
||||
set dff_ck [$dff_cell find_liberty_port CK]
|
||||
puts "PASS: find_liberty_port DFF_X1/CK"
|
||||
|
||||
set dff_d [$dff_cell find_liberty_port D]
|
||||
puts "PASS: find_liberty_port DFF_X1/D"
|
||||
|
||||
set dff_q [$dff_cell find_liberty_port Q]
|
||||
puts "PASS: find_liberty_port DFF_X1/Q"
|
||||
|
||||
############################################################
|
||||
# Liberty port iterator on cell
|
||||
|
|
@ -160,7 +129,6 @@ while { [$port_iter has_next] } {
|
|||
incr count
|
||||
}
|
||||
$port_iter finish
|
||||
puts "PASS: liberty_port_iterator INV_X1 ports = $count"
|
||||
|
||||
set port_iter2 [$dff_cell liberty_port_iterator]
|
||||
set count2 0
|
||||
|
|
@ -169,7 +137,6 @@ while { [$port_iter2 has_next] } {
|
|||
incr count2
|
||||
}
|
||||
$port_iter2 finish
|
||||
puts "PASS: liberty_port_iterator DFF_X1 ports = $count2"
|
||||
|
||||
############################################################
|
||||
# Wireload queries
|
||||
|
|
@ -177,14 +144,12 @@ puts "PASS: liberty_port_iterator DFF_X1 ports = $count2"
|
|||
############################################################
|
||||
set wl [$lib find_wireload "1K_hvratio_1_1"]
|
||||
if { $wl != "NULL" } {
|
||||
puts "PASS: find_wireload 1K_hvratio_1_1"
|
||||
} else {
|
||||
puts "INFO: wireload not found"
|
||||
}
|
||||
|
||||
set wls [$lib find_wireload_selection "WireloadSelection"]
|
||||
if { $wls != "NULL" } {
|
||||
puts "PASS: find_wireload_selection"
|
||||
} else {
|
||||
puts "INFO: wireload selection not found"
|
||||
}
|
||||
|
|
@ -193,20 +158,17 @@ if { $wls != "NULL" } {
|
|||
# Read Sky130 library - has different features
|
||||
############################################################
|
||||
read_liberty ../../test/sky130hd/sky130hd_tt.lib
|
||||
puts "PASS: read sky130"
|
||||
|
||||
set sky_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
|
||||
|
||||
set sky_op [$sky_lib find_operating_conditions "tt_025C_1v80"]
|
||||
if { $sky_op != "NULL" } {
|
||||
puts "PASS: sky130 find_operating_conditions"
|
||||
} else {
|
||||
puts "INFO: sky130 no named operating conditions"
|
||||
}
|
||||
|
||||
set sky_def_op [$sky_lib default_operating_conditions]
|
||||
if { $sky_def_op != "NULL" } {
|
||||
puts "PASS: sky130 default_operating_conditions"
|
||||
} else {
|
||||
puts "INFO: sky130 no default operating conditions"
|
||||
}
|
||||
|
|
@ -216,41 +178,31 @@ if { $sky_def_op != "NULL" } {
|
|||
# Exercises: makeCornerMap path, setCornerCell, scaleFactor
|
||||
############################################################
|
||||
read_liberty ../../test/nangate45/Nangate45_fast.lib
|
||||
puts "PASS: read Nangate45_fast"
|
||||
|
||||
# Read slow too - exercises more corner mapping paths
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib
|
||||
puts "PASS: read sky130 ff"
|
||||
|
||||
read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
|
||||
puts "PASS: read sky130 ss"
|
||||
|
||||
# Report checks exercises multi-library corner paths
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks multi-library"
|
||||
|
||||
############################################################
|
||||
# set_timing_derate - exercises OCV paths
|
||||
############################################################
|
||||
catch {
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
puts "PASS: set_timing_derate"
|
||||
}
|
||||
set_timing_derate -early 0.95
|
||||
set_timing_derate -late 1.05
|
||||
|
||||
report_checks -from [get_ports in1] -to [get_ports out1]
|
||||
puts "PASS: report_checks with derate"
|
||||
|
||||
############################################################
|
||||
# Write liberty for Nangate to exercise all writer paths
|
||||
############################################################
|
||||
set outfile [make_result_file liberty_opcond_scale_write.lib]
|
||||
sta::write_liberty NangateOpenCellLibrary $outfile
|
||||
puts "PASS: write_liberty NangateOpenCellLibrary"
|
||||
|
||||
set outfile2 [make_result_file liberty_opcond_scale_sky130.lib]
|
||||
sta::write_liberty sky130_fd_sc_hd__tt_025C_1v80 $outfile2
|
||||
puts "PASS: write_liberty sky130"
|
||||
|
||||
############################################################
|
||||
# EquivCells with multiple libraries
|
||||
|
|
@ -260,34 +212,25 @@ set lib1 [lindex [get_libs NangateOpenCellLibrary] 0]
|
|||
set lib2 [lindex [get_libs NangateOpenCellLibrary_fast] 0]
|
||||
|
||||
sta::make_equiv_cells $lib1
|
||||
puts "PASS: make_equiv_cells lib1"
|
||||
|
||||
sta::make_equiv_cells $lib2
|
||||
puts "PASS: make_equiv_cells lib2"
|
||||
|
||||
# Cross-library equiv
|
||||
set inv_typ [get_lib_cell NangateOpenCellLibrary/INV_X1]
|
||||
set inv_fast [get_lib_cell NangateOpenCellLibrary_fast/INV_X1]
|
||||
set result [sta::equiv_cells $inv_typ $inv_fast]
|
||||
puts "PASS: equiv_cells typ vs fast INV_X1 = $result"
|
||||
|
||||
set buf_typ [get_lib_cell NangateOpenCellLibrary/BUF_X1]
|
||||
set buf_fast [get_lib_cell NangateOpenCellLibrary_fast/BUF_X1]
|
||||
set result [sta::equiv_cells $buf_typ $buf_fast]
|
||||
puts "PASS: equiv_cells typ vs fast BUF_X1 = $result"
|
||||
|
||||
# equiv_cell_ports across libraries
|
||||
set result [sta::equiv_cell_ports $inv_typ $inv_fast]
|
||||
puts "PASS: equiv_cell_ports typ vs fast = $result"
|
||||
|
||||
# equiv_cell_timing_arcs across libraries
|
||||
set result [sta::equiv_cell_timing_arcs $inv_typ $inv_fast]
|
||||
puts "PASS: equiv_cell_timing_arcs typ vs fast = $result"
|
||||
|
||||
############################################################
|
||||
# Report check types for max_cap, max_slew, max_fanout
|
||||
############################################################
|
||||
report_check_types -max_slew -max_capacitance -max_fanout -verbose
|
||||
puts "PASS: report_check_types verbose"
|
||||
|
||||
puts "ALL PASSED"
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue