112 lines
3.7 KiB
Tcl
112 lines
3.7 KiB
Tcl
# Test advanced graph operations: multiple-instance design, edge traversal,
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# and graph info queries.
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# Targets uncovered Graph.cc functions: vertex operations, edge iterators,
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# constant propagation, level reporting, etc.
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Load a larger design for more graph coverage
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#---------------------------------------------------------------
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog graph_test1.v
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link_design graph_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports d]
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set_output_delay -clock clk 1.0 [get_ports q]
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set_input_transition 0.1 [get_ports d]
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#---------------------------------------------------------------
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# report_checks exercises graph traversal
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#---------------------------------------------------------------
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puts "--- report_checks baseline ---"
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report_checks
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puts "--- report_checks -path_delay min ---"
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report_checks -path_delay min
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puts "--- report_checks -path_delay max ---"
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report_checks -path_delay max
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puts "--- report_checks -from/-to ---"
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report_checks -from [get_ports d] -to [get_ports q]
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puts "--- report_checks -through ---"
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set rc [catch { report_checks -through [get_pins reg1/Q] } msg]
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if { $rc == 0 } {
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} else {
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puts "INFO: report_checks -through: $msg"
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}
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#---------------------------------------------------------------
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# Edge queries (Graph.cc edge functions)
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#---------------------------------------------------------------
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puts "--- get_timing_edges full combinations ---"
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set edges_all [get_timing_edges -of_objects [get_cells reg1]]
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puts "reg1 all edges: [llength $edges_all]"
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set edges_all2 [get_timing_edges -of_objects [get_cells reg2]]
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puts "reg2 all edges: [llength $edges_all2]"
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puts "--- report_edges for cells ---"
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report_edges -from [get_pins reg1/CK] -to [get_pins reg1/Q]
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report_edges -from [get_pins reg2/CK] -to [get_pins reg2/Q]
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report_edges -from [get_pins reg1/CK]
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report_edges -to [get_pins reg2/D]
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#---------------------------------------------------------------
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# set_disable_timing / report_disabled_edges exercises more paths
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#---------------------------------------------------------------
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puts "--- disable_timing on port pin ---"
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set_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
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report_disabled_edges
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report_checks
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unset_disable_timing -from CK -to Q [get_lib_cells NangateOpenCellLibrary/DFF_X1]
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report_disabled_edges
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puts "--- set_disable_timing instance and back ---"
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set_disable_timing [get_cells reg1]
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report_disabled_edges
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report_checks
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unset_disable_timing [get_cells reg1]
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report_disabled_edges
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report_checks
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#---------------------------------------------------------------
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# Slew reporting (exercises vertex slew access)
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#---------------------------------------------------------------
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puts "--- report_slews for various pins ---"
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report_slews [get_ports d]
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report_slews [get_ports q]
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report_slews [get_pins reg1/CK]
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report_slews [get_pins reg1/Q]
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report_slews [get_pins reg2/D]
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#---------------------------------------------------------------
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# Graph verification
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#---------------------------------------------------------------
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puts "--- report_check_types ---"
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report_check_types -max_delay -min_delay -verbose
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puts "--- report_checks with -format ---"
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report_checks -format full_clock
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puts "--- report_checks -unconstrained ---"
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report_checks -unconstrained
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#---------------------------------------------------------------
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# Additional graph traversals (exercises more vertex/edge paths)
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#---------------------------------------------------------------
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puts "--- report_checks -group_count 2 ---"
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report_checks -group_count 2
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puts "--- report_checks -endpoint_count 2 ---"
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report_checks -endpoint_count 2
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