955 lines
31 KiB
Plaintext
955 lines
31 KiB
Plaintext
--- Test 1: baseline edge count ---
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
buf1 edges: 1
|
|
buf2 edges: 1
|
|
inv1 edges: 1
|
|
and1 edges: 1
|
|
or1 edges: 1
|
|
nand1 edges: 1
|
|
nor1 edges: 1
|
|
--- Test 2: chain add/delete ---
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
chain_buf0 edges: 1
|
|
chain_buf1 edges: 1
|
|
chain_buf2 edges: 1
|
|
chain_buf3 edges: 1
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
--- Test 3: fan-out/fan-in ---
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
fo_drv edges: 1
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
--- Test 4: cell replacement cycle ---
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.13 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.13 ^ reg2/D (DFF_X1)
|
|
1.13 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
8.84 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
--- Test 5: register add/delete ---
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
--- Test 6: slew and edge reports ---
|
|
d1 ^ 0.10:0.10 v 0.10:0.10
|
|
d2 ^ 0.10:0.10 v 0.10:0.10
|
|
d3 ^ 0.10:0.10 v 0.10:0.10
|
|
clk ^ 0.10:0.10 v 0.10:0.10
|
|
buf1/A ^ 0.10:0.10 v 0.10:0.10
|
|
buf1/Z ^ 0.01:0.01 v 0.01:0.01
|
|
and1/A1 ^ 0.01:0.01 v 0.01:0.01
|
|
and1/ZN ^ 0.01:0.01 v 0.01:0.01
|
|
inv1/A ^ 0.10:0.10 v 0.10:0.10
|
|
inv1/ZN ^ 0.02:0.02 v 0.02:0.02
|
|
nand1/ZN ^ 0.01:0.01 v 0.01:0.01
|
|
nor1/ZN ^ 0.01:0.01 v 0.01:0.01
|
|
A -> Z combinational
|
|
^ -> ^ 0.03:0.03
|
|
v -> v 0.06:0.06
|
|
A1 -> ZN combinational
|
|
^ -> ^ 0.04:0.04
|
|
v -> v 0.03:0.03
|
|
A -> ZN combinational
|
|
^ -> v 0.01:0.01
|
|
v -> ^ 0.04:0.04
|
|
--- Test 7: through-pin queries ---
|
|
Startpoint: d1 (input port clocked by clk)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.03 1.09 v and1/ZN (AND2_X1)
|
|
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
|
0.00 1.11 ^ reg3/D (DFF_X1)
|
|
1.11 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg3/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.11 data arrival time
|
|
---------------------------------------------------------
|
|
8.86 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.04 1.09 v and1/ZN (AND2_X1)
|
|
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
|
0.00 1.11 ^ reg3/D (DFF_X1)
|
|
1.11 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg3/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.11 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d3 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d3 (in)
|
|
0.04 1.04 ^ inv1/ZN (INV_X1)
|
|
0.03 1.07 ^ or1/ZN (OR2_X1)
|
|
0.01 1.09 v nand1/ZN (NAND2_X1)
|
|
0.00 1.09 v reg2/D (DFF_X1)
|
|
1.09 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-1.09 data arrival time
|
|
---------------------------------------------------------
|
|
8.88 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.04 1.09 v and1/ZN (AND2_X1)
|
|
0.02 1.11 ^ nor1/ZN (NOR2_X1)
|
|
0.00 1.11 ^ reg3/D (DFF_X1)
|
|
1.11 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg3/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.11 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: d2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v d2 (in)
|
|
0.06 1.06 v buf2/Z (BUF_X1)
|
|
0.05 1.11 v or1/ZN (OR2_X1)
|
|
0.02 1.12 ^ nand1/ZN (NAND2_X1)
|
|
0.00 1.12 ^ reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.03 9.97 library setup time
|
|
9.97 data required time
|
|
---------------------------------------------------------
|
|
9.97 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
8.85 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: q1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ q1 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: q2 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.00 0.08 ^ q2 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: q3 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg3/CK (DFF_X1)
|
|
0.08 0.08 ^ reg3/Q (DFF_X1)
|
|
0.00 0.08 ^ q3 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg4 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: q4 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg4/CK (DFF_X1)
|
|
0.08 0.08 ^ reg4/Q (DFF_X1)
|
|
0.00 0.08 ^ q4 (out)
|
|
0.08 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
-1.00 9.00 output external delay
|
|
9.00 data required time
|
|
---------------------------------------------------------
|
|
9.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
8.92 slack (MET)
|
|
|
|
|