2012 lines
56 KiB
Plaintext
2012 lines
56 KiB
Plaintext
--- baseline timing ---
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: baseline report_checks
|
|
Startpoint: in4 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ in4 (in)
|
|
0.01 0.01 v nor1/ZN (NOR2_X1)
|
|
0.00 0.01 v reg2/D (DFF_X1)
|
|
0.01 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg2/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.01 data arrival time
|
|
---------------------------------------------------------
|
|
0.01 slack (MET)
|
|
|
|
|
|
PASS: baseline min path
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: baseline max path
|
|
--- multiple path queries ---
|
|
No paths found.
|
|
PASS: in1->out1
|
|
No paths found.
|
|
PASS: in1->out2
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: out3 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in1 (in)
|
|
0.06 0.06 v buf1/Z (BUF_X1)
|
|
0.01 0.07 ^ inv1/ZN (INV_X1)
|
|
0.02 0.09 ^ buf2/Z (BUF_X2)
|
|
0.03 0.12 ^ or1/ZN (OR2_X1)
|
|
0.02 0.13 ^ buf_out/Z (BUF_X1)
|
|
0.00 0.13 ^ out3 (out)
|
|
0.13 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
0.00 10.00 output external delay
|
|
10.00 data required time
|
|
---------------------------------------------------------
|
|
10.00 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
9.87 slack (MET)
|
|
|
|
|
|
PASS: in1->out3
|
|
No paths found.
|
|
PASS: in2->out1
|
|
No paths found.
|
|
PASS: in2->out2
|
|
No paths found.
|
|
PASS: in3->out1
|
|
No paths found.
|
|
PASS: in4->out2
|
|
No paths found.
|
|
PASS: sel->out1
|
|
--- through pin queries ---
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: through or1/ZN
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.01 0.15 ^ nand1/ZN (NAND2_X1)
|
|
0.00 0.15 ^ reg1/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.82 slack (MET)
|
|
|
|
|
|
PASS: through nand1/ZN
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: through nor1/ZN
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
9.81 slack (MET)
|
|
|
|
|
|
PASS: through and1/ZN
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in1 (in)
|
|
0.06 0.06 v buf1/Z (BUF_X1)
|
|
0.01 0.07 ^ inv1/ZN (INV_X1)
|
|
0.02 0.09 ^ buf2/Z (BUF_X2)
|
|
0.03 0.12 ^ or1/ZN (OR2_X1)
|
|
0.01 0.13 v nand1/ZN (NAND2_X1)
|
|
0.00 0.13 v reg1/D (DFF_X1)
|
|
0.13 data arrival time
|
|
|
|
10.00 10.00 clock clk (rise edge)
|
|
0.00 10.00 clock network delay (ideal)
|
|
0.00 10.00 clock reconvergence pessimism
|
|
10.00 ^ reg1/CK (DFF_X1)
|
|
-0.04 9.96 library setup time
|
|
9.96 data required time
|
|
---------------------------------------------------------
|
|
9.96 data required time
|
|
-0.13 data arrival time
|
|
---------------------------------------------------------
|
|
9.83 slack (MET)
|
|
|
|
|
|
PASS: through inv1/ZN
|
|
--- report_dcalc various gate types ---
|
|
Library: NangateOpenCellLibrary
|
|
Cell: BUF_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A ^ -> Z ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.70
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.03 0.03
|
|
0.13 | 0.03 0.04
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.70
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A v -> Z v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.55
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.05 0.05
|
|
0.13 | 0.06 0.07
|
|
Table value = 0.06
|
|
PVT scale factor = 1.00
|
|
Delay = 0.06
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.55
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc buf1 max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: BUF_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A ^ -> Z ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.70
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.03 0.03
|
|
0.13 | 0.03 0.04
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.70
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A v -> Z v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.55
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.05 0.05
|
|
0.13 | 0.06 0.07
|
|
Table value = 0.06
|
|
PVT scale factor = 1.00
|
|
Delay = 0.06
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.55
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc buf1 min:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: INV_X1
|
|
Arc sense: negative_unate
|
|
Arc type: combinational
|
|
A ^ -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.59
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.00 0.01
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Delay = 0.01
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.59
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.00 0.00
|
|
0.02 | 0.00 0.01
|
|
Table value = 0.00
|
|
PVT scale factor = 1.00
|
|
Slew = 0.00
|
|
Driver waveform slew = 0.00
|
|
|
|
.............................................
|
|
|
|
A v -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.78
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.02 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Delay = 0.01
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.78
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.00 0.01
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc inv1 max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: AND2_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A1 ^ -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 0.94
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.00 | 0.02 0.03
|
|
0.02 | 0.03 0.03
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 0.94
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A1 v -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 0.90
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.00 | 0.02 0.03
|
|
0.02 | 0.03 0.03
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 0.90
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.00 | 0.00 0.01
|
|
0.02 | 0.00 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc and1 A1->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: AND2_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A2 ^ -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 0.94
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.08 | 0.04 0.05
|
|
0.13 | 0.04 0.05
|
|
Table value = 0.04
|
|
PVT scale factor = 1.00
|
|
Delay = 0.04
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 0.94
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A2 v -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 0.90
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.08 | 0.06 0.06
|
|
0.13 | 0.07 0.07
|
|
Table value = 0.06
|
|
PVT scale factor = 1.00
|
|
Delay = 0.06
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 0.90
|
|
| 0.37 1.89
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc and1 A2->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: OR2_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A1 ^ -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 4.29
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.02 0.03
|
|
0.00 | 0.03 0.04
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 4.29
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.01 0.02
|
|
0.00 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A1 v -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 3.82
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.05 0.05
|
|
0.00 | 0.05 0.06
|
|
Table value = 0.05
|
|
PVT scale factor = 1.00
|
|
Delay = 0.05
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 3.82
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.01 0.02
|
|
0.00 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc or1 A1->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: OR2_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A2 ^ -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 4.29
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.03 0.04
|
|
0.02 | 0.03 0.04
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 4.29
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.01 0.02
|
|
0.02 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A2 v -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 3.82
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.05 0.06
|
|
0.02 | 0.06 0.07
|
|
Table value = 0.05
|
|
PVT scale factor = 1.00
|
|
Delay = 0.05
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 3.82
|
|
| 3.79 7.57
|
|
v --------------------
|
|
0.00 | 0.01 0.02
|
|
0.02 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc or1 A2->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: NAND2_X1
|
|
Arc sense: negative_unate
|
|
Arc type: combinational
|
|
A1 ^ -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.02 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Delay = 0.01
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.00 | 0.00 0.01
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A1 v -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.02 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Delay = 0.01
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.00 | 0.00 0.01
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc nand1 A1->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: NAND2_X1
|
|
Arc sense: negative_unate
|
|
Arc type: combinational
|
|
A2 ^ -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.08 | 0.01 0.02
|
|
0.13 | 0.01 0.02
|
|
Table value = 0.02
|
|
PVT scale factor = 1.00
|
|
Delay = 0.02
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.08 | 0.01 0.02
|
|
0.13 | 0.02 0.02
|
|
Table value = 0.02
|
|
PVT scale factor = 1.00
|
|
Slew = 0.02
|
|
Driver waveform slew = 0.02
|
|
|
|
.............................................
|
|
|
|
A2 v -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.08 | 0.03 0.04
|
|
0.13 | 0.04 0.05
|
|
Table value = 0.04
|
|
PVT scale factor = 1.00
|
|
Delay = 0.04
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.37 1.85
|
|
v --------------------
|
|
0.08 | 0.02 0.02
|
|
0.13 | 0.02 0.03
|
|
Table value = 0.02
|
|
PVT scale factor = 1.00
|
|
Slew = 0.02
|
|
Driver waveform slew = 0.02
|
|
|
|
.............................................
|
|
|
|
dcalc nand1 A2->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: NOR2_X1
|
|
Arc sense: negative_unate
|
|
Arc type: combinational
|
|
A1 ^ -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Delay = 0.01
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.00 | 0.00 0.00
|
|
0.02 | 0.01 0.01
|
|
Table value = 0.00
|
|
PVT scale factor = 1.00
|
|
Slew = 0.00
|
|
Driver waveform slew = 0.00
|
|
|
|
.............................................
|
|
|
|
A1 v -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.00 | 0.02 0.02
|
|
0.02 | 0.02 0.03
|
|
Table value = 0.02
|
|
PVT scale factor = 1.00
|
|
Delay = 0.02
|
|
|
|
------- input_net_transition = 0.01
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.00 | 0.01 0.02
|
|
0.02 | 0.01 0.02
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc nor1 A1->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: NOR2_X1
|
|
Arc sense: negative_unate
|
|
Arc type: combinational
|
|
A2 ^ -> ZN v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Delay = 0.01
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.06
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.08 | 0.02 0.02
|
|
0.13 | 0.02 0.03
|
|
Table value = 0.02
|
|
PVT scale factor = 1.00
|
|
Slew = 0.02
|
|
Driver waveform slew = 0.02
|
|
|
|
.............................................
|
|
|
|
A2 v -> ZN ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.08 | 0.04 0.05
|
|
0.13 | 0.05 0.06
|
|
Table value = 0.05
|
|
PVT scale factor = 1.00
|
|
Delay = 0.05
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.14
|
|
| 0.83 1.67
|
|
v --------------------
|
|
0.08 | 0.02 0.02
|
|
0.13 | 0.02 0.03
|
|
Table value = 0.02
|
|
PVT scale factor = 1.00
|
|
Slew = 0.02
|
|
Driver waveform slew = 0.02
|
|
|
|
.............................................
|
|
|
|
dcalc nor1 A2->ZN max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: DFF_X1
|
|
Arc sense: non_unate
|
|
Arc type: Reg Clk to Q
|
|
CK ^ -> Q ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.08 0.09
|
|
0.00 | 0.08 0.09
|
|
Table value = 0.08
|
|
PVT scale factor = 1.00
|
|
Delay = 0.08
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.00 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
CK ^ -> Q v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.08 0.08
|
|
0.00 | 0.08 0.08
|
|
Table value = 0.08
|
|
PVT scale factor = 1.00
|
|
Delay = 0.08
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.00 | 0.01 0.01
|
|
Table value = 0.00
|
|
PVT scale factor = 1.00
|
|
Slew = 0.00
|
|
Driver waveform slew = 0.00
|
|
|
|
.............................................
|
|
|
|
dcalc reg1 CK->Q max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: DFF_X1
|
|
Arc sense: non_unate
|
|
Arc type: Reg Clk to Q
|
|
CK ^ -> Q ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.08 0.09
|
|
0.00 | 0.08 0.09
|
|
Table value = 0.08
|
|
PVT scale factor = 1.00
|
|
Delay = 0.08
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.00 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
CK ^ -> Q v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.08 0.08
|
|
0.00 | 0.08 0.08
|
|
Table value = 0.08
|
|
PVT scale factor = 1.00
|
|
Delay = 0.08
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.00 | 0.01 0.01
|
|
Table value = 0.00
|
|
PVT scale factor = 1.00
|
|
Slew = 0.00
|
|
Driver waveform slew = 0.00
|
|
|
|
.............................................
|
|
|
|
dcalc reg1 CK->Q min:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: DFF_X1
|
|
Arc type: setup
|
|
CK ^ -> D ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- constrained_pin_transition = 0.02 (ideal clock)
|
|
| related_pin_transition = 0.00
|
|
| 0.00 0.04
|
|
v --------------------
|
|
0.00 | 0.03 0.02
|
|
0.04 | 0.04 0.03
|
|
Table value = 0.04
|
|
PVT scale factor = 1.00
|
|
Check = 0.04
|
|
|
|
.............................................
|
|
|
|
CK ^ -> D v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- constrained_pin_transition = 0.02 (ideal clock)
|
|
| related_pin_transition = 0.00
|
|
| 0.00 0.04
|
|
v --------------------
|
|
0.00 | 0.04 0.02
|
|
0.04 | 0.05 0.04
|
|
Table value = 0.04
|
|
PVT scale factor = 1.00
|
|
Check = 0.04
|
|
|
|
.............................................
|
|
|
|
dcalc reg1 setup max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: DFF_X1
|
|
Arc type: hold
|
|
CK ^ -> D ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- constrained_pin_transition = 0.01 (ideal clock)
|
|
| related_pin_transition = 0.00
|
|
| 0.00 0.04
|
|
v --------------------
|
|
0.00 | 0.00 0.02
|
|
0.04 | 0.02 0.03
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Check = 0.01
|
|
|
|
.............................................
|
|
|
|
CK ^ -> D v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- constrained_pin_transition = 0.01 (ideal clock)
|
|
| related_pin_transition = 0.00
|
|
| 0.00 0.04
|
|
v --------------------
|
|
0.00 | 0.00 0.01
|
|
0.04 | 0.00 0.01
|
|
Table value = 0.00
|
|
PVT scale factor = 1.00
|
|
Check = 0.00
|
|
|
|
.............................................
|
|
|
|
dcalc reg1 hold min:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: DFF_X1
|
|
Arc sense: non_unate
|
|
Arc type: Reg Clk to Q
|
|
CK ^ -> Q ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.08 0.09
|
|
0.00 | 0.08 0.09
|
|
Table value = 0.08
|
|
PVT scale factor = 1.00
|
|
Delay = 0.08
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.00 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
CK ^ -> Q v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.08 0.08
|
|
0.00 | 0.08 0.08
|
|
Table value = 0.08
|
|
PVT scale factor = 1.00
|
|
Delay = 0.08
|
|
|
|
------- input_net_transition = 0.00
|
|
| total_output_net_capacitance = 0.00
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.00 | 0.01 0.01
|
|
0.00 | 0.01 0.01
|
|
Table value = 0.00
|
|
PVT scale factor = 1.00
|
|
Slew = 0.00
|
|
Driver waveform slew = 0.00
|
|
|
|
.............................................
|
|
|
|
dcalc reg2 CK->Q max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: DFF_X1
|
|
Arc type: setup
|
|
CK ^ -> D ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- constrained_pin_transition = 0.02 (ideal clock)
|
|
| related_pin_transition = 0.00
|
|
| 0.00 0.04
|
|
v --------------------
|
|
0.00 | 0.03 0.02
|
|
0.04 | 0.04 0.03
|
|
Table value = 0.04
|
|
PVT scale factor = 1.00
|
|
Check = 0.04
|
|
|
|
.............................................
|
|
|
|
CK ^ -> D v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- constrained_pin_transition = 0.02 (ideal clock)
|
|
| related_pin_transition = 0.00
|
|
| 0.00 0.04
|
|
v --------------------
|
|
0.00 | 0.04 0.02
|
|
0.04 | 0.05 0.04
|
|
Table value = 0.04
|
|
PVT scale factor = 1.00
|
|
Check = 0.04
|
|
|
|
.............................................
|
|
|
|
dcalc reg2 setup max:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: BUF_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A ^ -> Z ^
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.70
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.03 0.03
|
|
0.13 | 0.03 0.04
|
|
Table value = 0.03
|
|
PVT scale factor = 1.00
|
|
Delay = 0.03
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.70
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
A v -> Z v
|
|
P = 1.00 V = 1.10 T = 25.00
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.55
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.05 0.05
|
|
0.13 | 0.06 0.07
|
|
Table value = 0.06
|
|
PVT scale factor = 1.00
|
|
Delay = 0.06
|
|
|
|
------- input_net_transition = 0.10
|
|
| total_output_net_capacitance = 1.55
|
|
| 0.37 1.90
|
|
v --------------------
|
|
0.08 | 0.01 0.01
|
|
0.13 | 0.01 0.01
|
|
Table value = 0.01
|
|
PVT scale factor = 1.00
|
|
Slew = 0.01
|
|
Driver waveform slew = 0.01
|
|
|
|
.............................................
|
|
|
|
dcalc buf1 2 digits:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: BUF_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A ^ -> Z ^
|
|
P = 1.000000 V = 1.100000 T = 25.000000
|
|
------- input_net_transition = 0.100000
|
|
| total_output_net_capacitance = 1.700230
|
|
| 0.365616 1.895430
|
|
v --------------------
|
|
0.078060 | 0.028670 0.033868
|
|
0.130081 | 0.029278 0.035163
|
|
Table value = 0.033714
|
|
PVT scale factor = 1.000000
|
|
Delay = 0.033714
|
|
|
|
------- input_net_transition = 0.100000
|
|
| total_output_net_capacitance = 1.700230
|
|
| 0.365616 1.895430
|
|
v --------------------
|
|
0.078060 | 0.007270 0.009820
|
|
0.130081 | 0.008965 0.011835
|
|
Table value = 0.010328
|
|
PVT scale factor = 1.000000
|
|
Slew = 0.010328
|
|
Driver waveform slew = 0.010328
|
|
|
|
.............................................
|
|
|
|
A v -> Z v
|
|
P = 1.000000 V = 1.100000 T = 25.000000
|
|
------- input_net_transition = 0.100000
|
|
| total_output_net_capacitance = 1.549360
|
|
| 0.365616 1.895430
|
|
v --------------------
|
|
0.078060 | 0.049716 0.053860
|
|
0.130081 | 0.061787 0.066352
|
|
Table value = 0.058151
|
|
PVT scale factor = 1.000000
|
|
Delay = 0.058151
|
|
|
|
------- input_net_transition = 0.100000
|
|
| total_output_net_capacitance = 1.549360
|
|
| 0.365616 1.895430
|
|
v --------------------
|
|
0.078060 | 0.007435 0.008884
|
|
0.130081 | 0.009300 0.010811
|
|
Table value = 0.009363
|
|
PVT scale factor = 1.000000
|
|
Slew = 0.009363
|
|
Driver waveform slew = 0.009363
|
|
|
|
.............................................
|
|
|
|
dcalc buf1 6 digits:
|
|
Library: NangateOpenCellLibrary
|
|
Cell: BUF_X1
|
|
Arc sense: positive_unate
|
|
Arc type: combinational
|
|
A ^ -> Z ^
|
|
P = 1.0000000000 V = 1.1000000238 T = 25.0000000000
|
|
------- input_net_transition = 0.0999999940
|
|
| total_output_net_capacitance = 1.7002300024
|
|
| 0.3656159937 1.8954299688
|
|
v --------------------
|
|
0.0780595988 | 0.0286695007 0.0338681005
|
|
0.1300809979 | 0.0292776022 0.0351628996
|
|
Table value = 0.0337139107
|
|
PVT scale factor = 1.0000000000
|
|
Delay = 0.0337139107
|
|
|
|
------- input_net_transition = 0.0999999940
|
|
| total_output_net_capacitance = 1.7002300024
|
|
| 0.3656159937 1.8954299688
|
|
v --------------------
|
|
0.0780595988 | 0.0072701499 0.0098204901
|
|
0.1300809979 | 0.0089652101 0.0118354997
|
|
Table value = 0.0103277005
|
|
PVT scale factor = 1.0000000000
|
|
Slew = 0.0103277005
|
|
Driver waveform slew = 0.0103277005
|
|
|
|
.............................................
|
|
|
|
A v -> Z v
|
|
P = 1.0000000000 V = 1.1000000238 T = 25.0000000000
|
|
------- input_net_transition = 0.0999999940
|
|
| total_output_net_capacitance = 1.5493600368
|
|
| 0.3656159937 1.8954299688
|
|
v --------------------
|
|
0.0780595988 | 0.0497157983 0.0538601018
|
|
0.1300809979 | 0.0617868006 0.0663516000
|
|
Table value = 0.0581508502
|
|
PVT scale factor = 1.0000000000
|
|
Delay = 0.0581508502
|
|
|
|
------- input_net_transition = 0.0999999940
|
|
| total_output_net_capacitance = 1.5493600368
|
|
| 0.3656159937 1.8954299688
|
|
v --------------------
|
|
0.0780595988 | 0.0074347798 0.0088842297
|
|
0.1300809979 | 0.0093002804 0.0108105997
|
|
Table value = 0.0093629928
|
|
PVT scale factor = 1.0000000000
|
|
Slew = 0.0093629928
|
|
Driver waveform slew = 0.0093629928
|
|
|
|
.............................................
|
|
|
|
dcalc buf1 10 digits:
|
|
--- incremental delay calculation ---
|
|
No paths found.
|
|
PASS: incremental after set_load 0.001 on out1
|
|
No paths found.
|
|
PASS: incremental after set_load 0.01 on out1
|
|
No paths found.
|
|
PASS: incremental after set_load 0.1 on out1
|
|
No paths found.
|
|
PASS: incremental after set_load 0.05 on out2
|
|
No paths found.
|
|
PASS: incremental after slew 0.01 on in1
|
|
No paths found.
|
|
PASS: incremental after slew 1.0 on in1
|
|
Startpoint: in2 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 v input external delay
|
|
0.00 0.00 v in2 (in)
|
|
0.05 0.05 v buf3/Z (BUF_X4)
|
|
0.03 0.08 v and1/ZN (AND2_X1)
|
|
0.05 0.13 v or1/ZN (OR2_X1)
|
|
0.02 0.15 ^ nor1/ZN (NOR2_X1)
|
|
0.00 0.15 ^ reg2/D (DFF_X1)
|
|
0.15 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
5.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 4.96 library setup time
|
|
4.96 data required time
|
|
---------------------------------------------------------
|
|
4.96 data required time
|
|
-0.15 data arrival time
|
|
---------------------------------------------------------
|
|
4.81 slack (MET)
|
|
|
|
|
|
PASS: incremental after clock period change to 5
|
|
No paths found.
|
|
PASS: incremental after input_delay 1.0
|
|
No paths found.
|
|
PASS: incremental after output_delay 2.0
|
|
--- calculator switching ---
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 ^ input external delay
|
|
0.00 1.00 ^ in1 (in)
|
|
1.00 2.00 ^ buf1/Z (BUF_X1)
|
|
1.00 3.00 v inv1/ZN (INV_X1)
|
|
1.00 4.00 v buf2/Z (BUF_X2)
|
|
1.00 5.00 v or1/ZN (OR2_X1)
|
|
1.00 6.00 ^ nand1/ZN (NAND2_X1)
|
|
0.00 6.00 ^ reg1/D (DFF_X1)
|
|
6.00 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
5.00 ^ reg1/CK (DFF_X1)
|
|
-1.00 4.00 library setup time
|
|
4.00 data required time
|
|
---------------------------------------------------------
|
|
4.00 data required time
|
|
-6.00 data arrival time
|
|
---------------------------------------------------------
|
|
-2.00 slack (VIOLATED)
|
|
|
|
|
|
PASS: unit on large design
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: lumped_cap on large design
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: dmp_ceff_elmore on large design
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: dmp_ceff_two_pole on large design
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: ccs_ceff on large design
|
|
--- report_checks formatting ---
|
|
Warning: dcalc_graph_delay.tcl line 1, unknown field nets.
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Fanout Cap Slew Delay Time Description
|
|
-----------------------------------------------------------------------------
|
|
0.00 0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
1 0.00 0.01 0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.01 0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
0.00 5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
-----------------------------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
-----------------------------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_checks with all fields
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_checks full_clock
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_checks full_clock_expanded
|
|
Warning: dcalc_graph_delay.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 v reg1/Q (DFF_X1)
|
|
0.00 0.08 v out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.01 1.07 ^ inv1/ZN (INV_X1)
|
|
0.02 1.09 ^ buf2/Z (BUF_X2)
|
|
0.03 1.12 ^ or1/ZN (OR2_X1)
|
|
0.01 1.13 v nand1/ZN (NAND2_X1)
|
|
0.00 1.13 v reg1/D (DFF_X1)
|
|
1.13 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
5.00 ^ reg1/CK (DFF_X1)
|
|
-0.04 4.96 library setup time
|
|
4.96 data required time
|
|
---------------------------------------------------------
|
|
4.96 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
3.83 slack (MET)
|
|
|
|
|
|
PASS: report_checks endpoint_count 3
|
|
Warning: dcalc_graph_delay.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.01 1.07 ^ inv1/ZN (INV_X1)
|
|
0.02 1.09 ^ buf2/Z (BUF_X2)
|
|
0.03 1.12 ^ or1/ZN (OR2_X1)
|
|
0.01 1.13 v nand1/ZN (NAND2_X1)
|
|
0.00 1.13 v reg1/D (DFF_X1)
|
|
1.13 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
5.00 ^ reg1/CK (DFF_X1)
|
|
-0.04 4.96 library setup time
|
|
4.96 data required time
|
|
---------------------------------------------------------
|
|
4.96 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
3.83 slack (MET)
|
|
|
|
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.01 1.07 ^ inv1/ZN (INV_X1)
|
|
0.02 1.09 ^ buf2/Z (BUF_X2)
|
|
0.03 1.12 ^ or1/ZN (OR2_X1)
|
|
0.01 1.12 v nor1/ZN (NOR2_X1)
|
|
0.00 1.12 v reg2/D (DFF_X1)
|
|
1.12 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
5.00 ^ reg2/CK (DFF_X1)
|
|
-0.04 4.96 library setup time
|
|
4.96 data required time
|
|
---------------------------------------------------------
|
|
4.96 data required time
|
|
-1.12 data arrival time
|
|
---------------------------------------------------------
|
|
3.83 slack (MET)
|
|
|
|
|
|
Startpoint: in1 (input port clocked by clk)
|
|
Endpoint: out3 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
1.00 1.00 v input external delay
|
|
0.00 1.00 v in1 (in)
|
|
0.06 1.06 v buf1/Z (BUF_X1)
|
|
0.01 1.07 ^ inv1/ZN (INV_X1)
|
|
0.02 1.09 ^ buf2/Z (BUF_X2)
|
|
0.03 1.12 ^ or1/ZN (OR2_X1)
|
|
0.02 1.13 ^ buf_out/Z (BUF_X1)
|
|
0.00 1.13 ^ out3 (out)
|
|
1.13 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
0.00 5.00 output external delay
|
|
5.00 data required time
|
|
---------------------------------------------------------
|
|
5.00 data required time
|
|
-1.13 data arrival time
|
|
---------------------------------------------------------
|
|
3.87 slack (MET)
|
|
|
|
|
|
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out2 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg2/CK (DFF_X1)
|
|
0.08 0.08 ^ reg2/Q (DFF_X1)
|
|
0.00 0.08 ^ out2 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
0.00 5.00 output external delay
|
|
5.00 data required time
|
|
---------------------------------------------------------
|
|
5.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
4.92 slack (MET)
|
|
|
|
|
|
PASS: report_checks group_count 5
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_checks unconstrained
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_checks sort_by_slack
|
|
--- report_check_types ---
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_check_types max
|
|
Startpoint: in4 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ in4 (in)
|
|
0.01 0.01 v nor1/ZN (NOR2_X1)
|
|
0.00 0.01 v reg2/D (DFF_X1)
|
|
0.01 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg2/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.01 data arrival time
|
|
---------------------------------------------------------
|
|
0.01 slack (MET)
|
|
|
|
|
|
PASS: report_check_types min
|
|
Startpoint: in4 (input port clocked by clk)
|
|
Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
|
|
Path Group: clk
|
|
Path Type: min
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ input external delay
|
|
0.00 0.00 ^ in4 (in)
|
|
0.01 0.01 v nor1/ZN (NOR2_X1)
|
|
0.00 0.01 v reg2/D (DFF_X1)
|
|
0.01 data arrival time
|
|
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 clock reconvergence pessimism
|
|
0.00 ^ reg2/CK (DFF_X1)
|
|
0.00 0.00 library hold time
|
|
0.00 data required time
|
|
---------------------------------------------------------
|
|
0.00 data required time
|
|
-0.01 data arrival time
|
|
---------------------------------------------------------
|
|
0.01 slack (MET)
|
|
|
|
|
|
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
|
|
Endpoint: out1 (output port clocked by clk)
|
|
Path Group: clk
|
|
Path Type: max
|
|
|
|
Delay Time Description
|
|
---------------------------------------------------------
|
|
0.00 0.00 clock clk (rise edge)
|
|
0.00 0.00 clock network delay (ideal)
|
|
0.00 0.00 ^ reg1/CK (DFF_X1)
|
|
0.08 0.08 ^ reg1/Q (DFF_X1)
|
|
0.00 0.08 ^ out1 (out)
|
|
0.08 data arrival time
|
|
|
|
5.00 5.00 clock clk (rise edge)
|
|
0.00 5.00 clock network delay (ideal)
|
|
0.00 5.00 clock reconvergence pessimism
|
|
-2.00 3.00 output external delay
|
|
3.00 data required time
|
|
---------------------------------------------------------
|
|
3.00 data required time
|
|
-0.08 data arrival time
|
|
---------------------------------------------------------
|
|
2.92 slack (MET)
|
|
|
|
|
|
PASS: report_check_types max+min
|
|
ALL PASSED
|