554 lines
16 KiB
Plaintext
554 lines
16 KiB
Plaintext
--- setIncrementalDelayTolerance ---
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PASS: incremental delay tolerance 0.01
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PASS: incremental delay tolerance 0.0
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PASS: incremental delay tolerance 0.1
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--- report_net for various nets ---
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Net n1
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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inv1/A input (INV_X1) 1.55-1.70
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Net n2
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Pin capacitance: 1.59-1.78
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Wire capacitance: 0.00
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Total capacitance: 1.59-1.78
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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buf2/A input (BUF_X2) 1.59-1.78
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Net n3
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Pin capacitance: 0.79-0.95
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Wire capacitance: 0.00
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Total capacitance: 0.79-0.95
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf2/Z output (BUF_X2)
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Load pins
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or1/A1 input (OR2_X1) 0.79-0.95
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Net n4
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf3/Z output (BUF_X4)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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Net n5
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Pin capacitance: 0.90-0.94
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Wire capacitance: 0.00
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Total capacitance: 0.90-0.94
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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or1/A2 input (OR2_X1) 0.90-0.94
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Net n6
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Pin capacitance: 3.82-4.29
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Wire capacitance: 0.00
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Total capacitance: 3.82-4.29
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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buf_out/A input (BUF_X1) 0.88-0.97
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nand1/A1 input (NAND2_X1) 1.53-1.60
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nor1/A1 input (NOR2_X1) 1.41-1.71
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Net n7
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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nand1/ZN output (NAND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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Net n8
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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nor1/ZN output (NOR2_X1)
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Load pins
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reg2/D input (DFF_X1) 1.06-1.14
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PASS: report_net all nets
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--- report_net with loads ---
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Net n6
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Pin capacitance: 3.82-4.29
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Wire capacitance: 0.00
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Total capacitance: 3.82-4.29
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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buf_out/A input (BUF_X1) 0.88-0.97
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nand1/A1 input (NAND2_X1) 1.53-1.60
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nor1/A1 input (NOR2_X1) 1.41-1.71
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Net n7
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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nand1/ZN output (NAND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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Net n8
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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nor1/ZN output (NOR2_X1)
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Load pins
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reg2/D input (DFF_X1) 1.06-1.14
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PASS: report_net with loads
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--- report_net with digits ---
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Net n1
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Pin capacitance: 1.549360-1.700230
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Wire capacitance: 0.000000
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Total capacitance: 1.549360-1.700230
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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inv1/A input (INV_X1) 1.549360-1.700230
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Net n6
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Pin capacitance: 3.82-4.29
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Wire capacitance: 0.00
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Total capacitance: 3.82-4.29
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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buf_out/A input (BUF_X1) 0.88-0.97
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nand1/A1 input (NAND2_X1) 1.53-1.60
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nor1/A1 input (NOR2_X1) 1.41-1.71
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PASS: report_net digits
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--- incremental with wire caps ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: wire cap n1
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: wire cap n6
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--- rapid constraint changes ---
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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PASS: rapid constraint changes
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--- input transition incremental ---
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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PASS: input transition incremental
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--- clock period incremental ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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5.00 5.00 clock clk (rise edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 clock reconvergence pessimism
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5.00 ^ reg2/CK (DFF_X1)
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-0.04 4.96 library setup time
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4.96 data required time
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---------------------------------------------------------
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4.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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4.81 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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20.00 20.00 clock clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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20.00 ^ reg2/CK (DFF_X1)
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-0.04 19.96 library setup time
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19.96 data required time
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---------------------------------------------------------
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19.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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19.81 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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2.00 2.00 clock clk (rise edge)
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0.00 2.00 clock network delay (ideal)
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0.00 2.00 clock reconvergence pessimism
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2.00 ^ reg2/CK (DFF_X1)
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-0.04 1.96 library setup time
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1.96 data required time
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---------------------------------------------------------
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1.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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1.81 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: clock period incremental
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--- delay calc after constraint changes ---
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No paths found.
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No paths found.
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No paths found.
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PASS: constraint change incremental
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--- driving cell changes ---
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No paths found.
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No paths found.
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No paths found.
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PASS: driving cell changes
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--- write and read SDF ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
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Not
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Delay type Total Annotated Annotated
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----------------------------------------------------------------
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cell arcs 17 17 0
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internal net arcs 10 10 0
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net arcs from primary inputs 7 7 0
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net arcs to primary outputs 3 3 0
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----------------------------------------------------------------
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37 37 0
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Annotated Arcs
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primary input net clk -> reg1/CK
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primary input net clk -> reg2/CK
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primary input net in1 -> buf1/A
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primary input net in2 -> buf3/A
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primary input net in3 -> and1/A2
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primary input net in4 -> nor1/A2
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primary input net sel -> nand1/A2
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delay and1/A1 -> and1/ZN
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delay and1/A2 -> and1/ZN
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internal net and1/ZN -> or1/A2
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delay buf1/A -> buf1/Z
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internal net buf1/Z -> inv1/A
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delay buf2/A -> buf2/Z
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internal net buf2/Z -> or1/A1
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delay buf3/A -> buf3/Z
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internal net buf3/Z -> and1/A1
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delay buf_out/A -> buf_out/Z
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primary output net buf_out/Z -> out3
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delay inv1/A -> inv1/ZN
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internal net inv1/ZN -> buf2/A
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delay nand1/A1 -> nand1/ZN
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delay nand1/A2 -> nand1/ZN
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internal net nand1/ZN -> reg1/D
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delay nor1/A1 -> nor1/ZN
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delay nor1/A2 -> nor1/ZN
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internal net nor1/ZN -> reg2/D
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delay or1/A1 -> or1/ZN
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delay or1/A2 -> or1/ZN
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internal net or1/ZN -> nand1/A1
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internal net or1/ZN -> nor1/A1
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internal net or1/ZN -> buf_out/A
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delay reg1/CK -> reg1/QN
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delay reg1/CK -> reg1/Q
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primary output net reg1/Q -> out1
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delay reg2/CK -> reg2/QN
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delay reg2/CK -> reg2/Q
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primary output net reg2/Q -> out2
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Warning: dcalc_annotated_incremental.tcl line 1, -list_annotated is deprecated. Use -report_annotated.
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Not
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Check type Total Annotated Annotated
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----------------------------------------------------------------
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cell setup arcs 2 2 0
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cell hold arcs 2 2 0
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----------------------------------------------------------------
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4 4 0
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Annotated Arcs
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setup reg1/CK -> reg1/D
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hold reg1/CK -> reg1/D
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setup reg2/CK -> reg2/D
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hold reg2/CK -> reg2/D
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PASS: write/read SDF
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--- remove annotations ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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PASS: remove annotations
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--- calculator switch incremental ---
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No paths found.
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No paths found.
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No paths found.
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No paths found.
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PASS: calculator switch incremental
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ALL PASSED
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