OpenRAM/compiler/base
mrg f6c5f48b4c Default channel route is true 2020-10-28 10:31:05 -07:00
..
channel_route.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
contact.py Remove static method call 2020-10-27 09:26:40 -07:00
custom_cell_properties.py Add ptx cell properties 2020-10-28 09:54:15 -07:00
custom_layer_properties.py Default channel route is true 2020-10-28 10:31:05 -07:00
delay_data.py Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
design.py Multiport constants can't be static 2020-10-27 09:28:21 -07:00
errors.py Add exception errors file 2020-04-08 16:55:45 -07:00
geometry.py Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
graph_util.py Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
hierarchy_design.py Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
hierarchy_layout.py Convert design class data to static 2020-10-27 09:23:11 -07:00
hierarchy_spice.py Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
lef.py Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
pin_layout.py Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
utils.py Search all shapes for boundary rather than specify structure 2020-10-08 14:04:19 -07:00
vector.py Merge branch 'tech_migration' into dev 2020-01-25 12:03:56 -08:00
verilog.py Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
wire.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
wire_path.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
wire_spice_model.py Move classes to individual file. 2019-07-16 15:18:04 -07:00