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base
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Remove temp names in DRC/LVS. Extract unique doesn't actually extract.
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2019-02-24 07:26:21 -08:00 |
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bitcells
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Copy 1rw/1r cell to 1w/1r.
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2019-02-24 09:54:45 -08:00 |
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characterizer
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Revert bus bits back into pins
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2019-02-22 16:22:27 -08:00 |
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datasheet
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fixed area not being found
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2019-02-14 07:01:35 -08:00 |
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drc
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Moving wide metal spacing to routing grid level
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2018-10-15 09:59:16 -07:00 |
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example_configs
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Add example 1w/1r
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2019-02-24 09:57:34 -08:00 |
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gdsMill
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Remove non-rectangular error and just skip them.
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2019-01-30 10:25:01 -08:00 |
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modules
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Changed test values to fix tests.
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2019-02-06 15:27:29 -08:00 |
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pgates
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Fixed some delay model bugs.
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2019-02-05 21:15:12 -08:00 |
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router
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Check membership of keys without using keys() list
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2019-01-30 13:02:34 -08:00 |
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tests
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Copy 1rw/1r cell to 1w/1r.
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2019-02-24 09:54:45 -08:00 |
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verify
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Remove temp names in DRC/LVS. Extract unique doesn't actually extract.
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2019-02-24 07:26:21 -08:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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Add missing / in output path for log
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2019-02-21 10:23:30 -08:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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git_id
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track git_id
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2018-12-05 16:13:52 -08:00 |
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globals.py
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Merge remote-tracking branch 'origin/dev' into factory
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2019-01-18 09:52:18 -08:00 |
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openram.py
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complete log file generation
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2019-01-13 14:34:46 -08:00 |
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options.py
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Fixed merge conflicts
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2019-01-28 22:33:08 -08:00 |
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profile_stats.py
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Add profile scripts
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2018-12-07 08:56:40 -08:00 |
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run_profile.sh
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Move inspect into if statement for runtime
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2019-01-30 08:42:25 -08:00 |
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sram.py
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html datasheet no longer dependeds on sram
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2019-01-16 14:52:01 -08:00 |
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sram_1bank.py
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_base.py
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Change pbuf/pinv to pdriver in control logic.
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2019-01-23 12:03:52 -08:00 |
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sram_config.py
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Added word per row to sram config with a default arguement to fix test.
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2019-01-30 11:43:47 -08:00 |
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sram_factory.py
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Added some comments to the spice files.
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2019-01-25 15:00:00 -08:00 |
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view_profile.py
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Convert source and target lists to sets for faster contains check.
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2019-01-30 11:15:47 -08:00 |
4577d380f9