Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract.		2019-02-24 07:26:21 -08:00
..
contact.py	Convert all contacts to use the sram_factory	2019-01-16 16:56:06 -08:00
design.py	First draft of sram_factory code	2019-01-16 16:15:38 -08:00
geometry.py	Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.	2018-11-16 11:48:41 -08:00
hierarchy_design.py	Remove temp names in DRC/LVS. Extract unique doesn't actually extract.	2019-02-24 07:26:21 -08:00
hierarchy_layout.py	Change path to wire_path for Anaconda package conflict	2019-01-25 15:07:56 -08:00
hierarchy_spice.py	Add size commments to spize. Change pdriver stage effort.	2019-01-23 17:27:15 -08:00
lef.py	Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.	2019-01-11 14:15:16 -08:00
pin_layout.py	Fix instersection bug. Improve primary and secondary pin algo.	2018-12-04 16:53:04 -08:00
route.py	Convert all contacts to use the sram_factory	2019-01-16 16:56:06 -08:00
utils.py	Allow multiple must-connect pins with the same label.	2018-11-07 13:05:13 -08:00
vector.py	Fix Future Warning for real	2018-10-10 15:58:16 -07:00
verilog.py	Remove tabs	2019-01-11 14:16:57 -08:00
wire.py	Change path to wire_path for Anaconda package conflict	2019-01-25 15:07:56 -08:00
wire_path.py	Change path to wire_path for Anaconda package conflict	2019-01-25 15:07:56 -08:00