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2954f13294a77cb154a971276c4cbac133c05673
OpenRAM/compiler/tests
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mrg 87493e1e30 Disable pex tests.
2020-12-11 11:47:10 -08:00
..
configs
Change default nominal corners to false and enable in test config.
2019-11-29 12:08:53 -08:00
golden
Add PDK layer names to tech file
2020-11-09 09:10:43 -08:00
00_code_format_check_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
01_library_test.py
Simplify to a single DRC/LVS library test.
2020-11-10 16:45:00 -08:00
03_contact_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_path_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_1finger_nmos_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_1finger_pmos_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_3finger_nmos_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_3finger_pmos_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_4finger_nmos_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_4finger_pmos_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_ptx_no_contacts_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
03_wire_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
04_and2_dec_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_and3_dec_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_and4_dec_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
04_column_mux_1rw_1r_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
04_column_mux_pbitcell_test.py
Rename single_level_column_mux to just column_mux
2020-10-05 08:56:51 -07:00
04_column_mux_test.py
Rename single_level_column_mux to just column_mux
2020-10-05 08:56:51 -07:00
04_dff_buf_test.py
Use cell_properties to override cell names
2020-11-03 07:06:01 -08:00
04_dummy_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pand2_test.py
Add pand4 and pnand4
2020-10-02 14:54:12 -07:00
04_pand3_test.py
Add pand4 and pnand4
2020-10-02 14:54:12 -07:00
04_pand4_test.py
Add pand4 and pnand4
2020-10-02 14:54:12 -07:00
04_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pbuf_dec_8x_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pbuf_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pdriver_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinv_1x_beta_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinv_1x_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinv_2x_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinv_10x_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinv_100x_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinv_dec_1x_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pinvbuf_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pnand2_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pnand3_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pnand4_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
04_pnor2_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_precharge_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_precharge_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_precharge_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_pwrite_driver_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
04_replica_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
04_wordline_driver_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
05_bitcell_array_1rw_1r_test.py
Remove extra debug statement
2020-12-08 11:59:14 -08:00
05_bitcell_array_test.py
Adjust openram options.
2020-11-05 13:12:26 -08:00
05_dummy_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
05_pbitcell_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_decoder_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_decoder_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_decoder_test.py
Disable 4x16 decoder test for now
2020-11-06 13:50:04 -08:00
06_hierarchical_predecode2x4_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_predecode2x4_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_predecode2x4_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_predecode3x8_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_predecode3x8_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_predecode3x8_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
06_hierarchical_predecode4x16_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
07_column_mux_array_1rw_1r_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
07_column_mux_array_pbitcell_test.py
Rename single_level_column_mux to just column_mux
2020-10-05 08:56:51 -07:00
07_column_mux_array_test.py
Rename single_level_column_mux to just column_mux
2020-10-05 08:56:51 -07:00
08_precharge_array_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
08_precharge_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
08_wordline_buffer_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
08_wordline_driver_array_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
08_wordline_driver_array_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
08_wordline_driver_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
09_sense_amp_array_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
09_sense_amp_array_spare_cols_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
09_sense_amp_array_test_pbitcell.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
09_sense_amp_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
10_write_driver_array_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
10_write_driver_array_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
10_write_driver_array_spare_cols_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
10_write_driver_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
10_write_driver_array_wmask_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
10_write_driver_array_wmask_spare_cols_test.py
Updated spare col tests
2020-06-08 16:38:18 +00:00
10_write_driver_array_wmask_test.py
split pbitcell tests
2020-04-17 12:26:18 -07:00
10_write_mask_and_array_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
10_write_mask_and_array_pbitcell_test.py
Add option to remove wells. Save area in pgates with redundant wells.
2020-05-13 14:46:42 -07:00
10_write_mask_and_array_test.py
split pbitcell tests
2020-04-17 12:26:18 -07:00
11_dff_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
11_dff_buf_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
12_tri_gate_array_test.py
Skip tri gate array test
2020-11-04 06:57:51 -08:00
13_delay_chain_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
14_replica_bitcell_array_1rw_1r_test.py
Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.
2020-11-20 16:56:07 -08:00
14_replica_bitcell_array_test.py
Change test 14 to odd sizes for use in sky130.
2020-12-08 10:32:23 -08:00
14_replica_column_1rw_1r_test.py
Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.
2020-11-20 16:56:07 -08:00
14_replica_column_test.py
Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions.
2020-11-20 16:56:07 -08:00
14_replica_pbitcell_array_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
15_global_bitcell_array_1rw_1r_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
15_global_bitcell_array_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
15_local_bitcell_array_1rw_1r_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
15_local_bitcell_array_test.py
Updates to local and global arrays to make bitline and wordlines consistent.
2020-09-09 11:54:46 -07:00
16_control_logic_multiport_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
16_control_logic_r_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
16_control_logic_rw_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
16_control_logic_w_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
18_port_address_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
18_port_address_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
18_port_data_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
18_port_data_spare_cols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
18_port_data_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
18_port_data_wmask_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
18_port_data_wmask_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
19_bank_select_pbitcell_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
19_bank_select_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
19_multi_bank_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
19_pmulti_bank_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
19_psingle_bank_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
19_single_bank_1rw_1r_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
19_single_bank_1w_1r_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
19_single_bank_global_bitline.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
19_single_bank_spare_cols_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
19_single_bank_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
19_single_bank_wmask_1rw_1r_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
19_single_bank_wmask_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
20_psram_1bank_2mux_1rw_1w_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_psram_1bank_2mux_1rw_1w_wmask_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
20_psram_1bank_2mux_1w_1r_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_psram_1bank_2mux_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_psram_1bank_4mux_1rw_1r_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_1rw_1r_test.py
Remove extra debug statement
2020-12-08 11:59:14 -08:00
20_sram_1bank_2mux_1w_1r_spare_cols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_1w_1r_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_global_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_wmask_spare_cols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_2mux_wmask_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_4mux_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_8mux_1rw_1r_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_8mux_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_32b_1024_wmask_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_nomux_1rw_1r_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_nomux_spare_cols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_nomux_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_nomux_wmask_sparecols_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_1bank_nomux_wmask_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
20_sram_2bank_test.py
Fix bitcell and pbitcell with different cell names
2020-11-03 11:30:40 -08:00
21_hspice_delay_test.py
Changed named on delay chain sizing variable. Automatic sizing default is False.
2020-11-17 14:29:01 -08:00
21_hspice_setuphold_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
21_model_delay_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
21_ngspice_delay_extra_rows_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
21_ngspice_delay_global_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
21_ngspice_delay_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
21_ngspice_setuphold_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
22_psram_1bank_2mux_func_test.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
22_psram_1bank_4mux_func_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
22_psram_1bank_8mux_func_test.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
22_psram_1bank_nomux_func_test.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
22_sram_1bank_2mux_func_test.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
22_sram_1bank_2mux_global_func_test.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
22_sram_1bank_2mux_sparecols_func_test.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
22_sram_1bank_4mux_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
22_sram_1bank_8mux_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
22_sram_1bank_nomux_1rw_1r_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
22_sram_1bank_nomux_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
22_sram_1bank_nomux_sparecols_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
22_sram_1bank_wmask_1rw_1r_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
22_sram_wmask_func_test.py
Fix errors in new run_sim calls and corners
2020-11-09 13:59:46 -08:00
23_lib_sram_model_corners_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
23_lib_sram_model_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
23_lib_sram_prune_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
23_lib_sram_test.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
24_lef_sram_test.py
Skip LEF test as correct output keeps changing.
2020-11-09 11:14:55 -08:00
25_verilog_sram_test.py
Add PDK layer names to tech file
2020-11-09 09:10:43 -08:00
26_hspice_pex_pinv_test.py
Disable pex tests.
2020-12-11 11:47:10 -08:00
26_ngspice_pex_pinv_test.py
Disable pex tests.
2020-12-11 11:47:10 -08:00
26_sram_pex_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
30_openram_back_end_test.py
Change custom cells to use set_ports setter
2020-11-14 07:15:27 -08:00
30_openram_front_end_test.py
Change custom cells to use set_ports setter
2020-11-14 07:15:27 -08:00
50_riscv_func_test.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
50_riscv_phys_test.py
Skip test 50 which is too slow
2020-11-16 08:59:25 -08:00
regress.py
PEP8 fixes in regress.py
2020-10-05 15:56:12 -07:00
skip_tests_sky130.txt
Names in skiptests changed. Reduce grid router verbosity.
2020-10-23 09:22:59 -07:00
sram_1rw_1r_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
sram_1rw_wmask_tb.v
Convert capital names to lower case for consistency
2019-08-21 13:45:34 -07:00
testutils.py
Make DRC/LVS scripts use relative paths
2020-12-11 10:06:00 -08:00