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Olof Kindgren
1d657abebc
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script
from compiler.base.verilog import verilog
v = verilog()
v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8
v.verilog_write("mymodule.v")
Signed-off-by: Olof Kindgren <[email protected]>