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OpenRAM/compiler/base
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Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 		2021-04-15 22:33:57 +02:00
..
channel_route.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
contact.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
custom_cell_properties.py Set default port map 2020-11-24 13:27:11 -08:00
custom_layer_properties.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
delay_data.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
design.py Can redefine number of ports in custom_cell_properties 2020-11-21 08:05:49 -08:00
errors.py Add exception errors file 2020-04-08 16:55:45 -07:00
geometry.py Fix lpp erase bug in removing router annotations 2021-01-06 09:39:01 -08:00
graph_util.py Added debug measurements along main delay paths in SRAM. WIP. 2020-11-17 12:43:17 -08:00
hierarchy_design.py Update temp file to be relative 2020-12-14 14:18:18 -08:00
hierarchy_layout.py Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
hierarchy_spice.py Many edits. 2020-11-22 08:24:47 -08:00
lef.py Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
pin_layout.py Use default zoom for text 2020-12-14 14:18:00 -08:00
power_data.py Move classes to individual file. 2019-07-16 15:18:04 -07:00
route.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
utils.py Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
vector.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
verilog.py Add VERBOSE parameter to generated verilog model 2021-04-15 22:33:57 +02:00
wire.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
wire_path.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
wire_spice_model.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00