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OpenRAM
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2842 Commits

Author SHA1 Message Date
Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:33:57 +02:00
mrg 608e4b81f1 Merge remote-tracking branch 'private/dev' 2021-01-15 16:11:23 -08:00
mrg 3048c61c20 Merge branch 'supply_router' into dev 2021-01-15 14:28:08 -08:00
mrg e8239c5e77 Remove debug print statement 2021-01-15 14:27:54 -08:00
mrg 69fe050bad Refactor and cleanup router grids. 2021-01-15 13:25:57 -08:00
mrg 683f4214b2 Differentiate pin and other blockages for easier to understand blockage processing. 2021-01-14 15:58:37 -08:00
mrg e3a888e0f7 Only unblock blockages not grids 2021-01-13 13:57:49 -08:00
mrg 88f2198524 Always use min area power/IO pins 2021-01-13 13:56:46 -08:00
mrg 3ef56a29ea Bug fix 2021-01-13 13:56:22 -08:00
mrg 1b31afd773 Use partial grids for enclosure with note 2021-01-13 13:01:55 -08:00
mrg bc9ab086e5 Clean up imports 2021-01-13 13:01:33 -08:00
mrg 78966824db Second iteration try unblocking partial blocked grids. 2021-01-13 12:37:29 -08:00
mrg 4991693f1a Clean up min area 2021-01-13 12:32:17 -08:00
mrg 01d312d65c Refactor add power pins 2021-01-13 10:57:12 -08:00
mrg 408ea15228 Ordering bug fixed in Magic. 2021-01-12 16:20:26 -08:00
mrg 6f5b7c0264 Flatten bug fixed in Magic so don't flatten routes. 2021-01-12 16:20:03 -08:00
mrg 3d7bed0641 Fix typo in comment 2021-01-12 11:22:11 -08:00
mrg 2101d89646 Merge branch 'dev' into supply_router 2021-01-11 13:52:59 -08:00
mrg 1c6d4eedd1 Add new empty debug function. 2021-01-11 13:52:41 -08:00
mrg 7506ba81be Refactor how blocked_grids work. Must still calculate blockages based on enclosed pins. 2021-01-11 11:12:45 -08:00
mrg 504f9aa892 Space tx in pinv_dec for power routing. 2021-01-08 11:34:58 -08:00
mrg f428ff4bfd v1.1.14 2021-01-07 10:33:21 -08:00
mrg c0df3ff1da Merge remote-tracking branch 'private/dev' 2021-01-07 10:20:17 -08:00
mrg 0faa14c0e3 Sort escape pins by distance to perimeter to reduce blockages. 2021-01-07 10:12:02 -08:00
mrg 66ff1fe990 Only unblock source/target instead of all components for cleaner routes 2021-01-06 15:14:56 -08:00
mrg 7eb1e2f2d1 Keep previous pin shapes which were used in router pin connections. 2021-01-06 11:31:16 -08:00
mrg 9a6ca328f6 Temporarily disable flatten and readonly in magic DRC 2021-01-06 09:42:56 -08:00
mrg be79789097 Return empty string instead of None when no grid type 2021-01-06 09:41:13 -08:00
mrg 72dc1c58da Initialize queue only in init_queue function 2021-01-06 09:40:49 -08:00
mrg ec6f0f1873 Escape route to any side 2021-01-06 09:40:32 -08:00
mrg b22d2a76a7 Make clear source/target option instead of general setter (bug to remove source/target fixed) 2021-01-06 09:39:50 -08:00
mrg d61fcb3be3 Fix lpp erase bug in removing router annotations 2021-01-06 09:39:01 -08:00
mrg 4fc0357282 Small readability edit to dff_buf 2021-01-04 13:16:23 -08:00
mrg 82178bcf89 Change info from exit to escape 2021-01-04 11:52:02 -08:00
mrg 81220068f7 v1.1.13 2020-12-23 11:59:54 -08:00
mrg 80c0bccd70 Merge remote-tracking branch 'private/dev' into dev 2020-12-23 11:59:38 -08:00
mrg c89e156bfe Separate add pins and route pins so pins can block supply router. 2020-12-23 10:49:47 -08:00
mrg 96c75d7c4b Remove outdated unit tests for router 2020-12-23 07:42:36 -08:00
mrg 35c1f2d8a5 Delete temp files 2020-12-23 07:41:04 -08:00
mrg 9ef4cf14c5 Check for drc/lvs aux scripts in test 30 2020-12-23 07:25:24 -08:00
mrg e59333a232 Change options to use route perimeter pins and supply as tree by default. 2020-12-23 07:25:07 -08:00
mrg 1885794016 Only write drc/lvs scripts if drc/lvs is enabled 2020-12-23 07:16:43 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg 98250cf115 Copy pins as rects before removing them. 2020-12-21 13:47:05 -08:00
mrg fc91c0da23 Only warn if characterizing. 2020-12-21 12:44:37 -08:00
mrg 6101195b51 Function to remove layout pins. 2020-12-21 12:44:04 -08:00