mrg 6062565973 Add col/row cap modules

2020-12-08 10:34:24 -08:00

..

bitcell_1port.py

Many edits.

2020-11-22 08:24:47 -08:00

bitcell_2port.py

Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

bitcell_base.py

Many edits.

2020-11-22 08:24:47 -08:00

col_cap_bitcell_1port.py

Add col/row cap modules

2020-12-08 10:34:24 -08:00

col_cap_bitcell_2port.py

Small bug fixes related to new name mapping.

2020-11-16 13:42:42 -08:00

dummy_bitcell_1port.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

dummy_bitcell_2port.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

dummy_pbitcell.py

Refactor dynamic cell name to utilize base class

2020-11-03 13:18:46 -08:00

pbitcell.py

Fix original pin name bug in bitcell too.

2020-11-19 15:12:02 -08:00

replica_bitcell_1port.py

Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.

2020-11-17 15:05:07 -08:00

replica_bitcell_2port.py

Fix original pin name bug in bitcell too.

2020-11-19 15:12:02 -08:00

replica_pbitcell.py

Fix bitcell and pbitcell with different cell names

2020-11-03 11:30:40 -08:00

row_cap_bitcell_1port.py

Add col/row cap modules

2020-12-08 10:34:24 -08:00

row_cap_bitcell_2port.py

Small bug fixes related to new name mapping.

2020-11-16 13:42:42 -08:00