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bank.py
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Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port
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2018-08-18 16:51:21 -07:00 |
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bank_select.py
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bank_sel_bar only used for clk now
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2018-08-13 15:14:52 -07:00 |
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bitcell.py
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altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions
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2018-08-05 19:43:59 -07:00 |
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bitcell_array.py
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Remove carriage returns form python files
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2018-08-07 09:44:01 -07:00 |
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control_logic.py
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Changing control logic names to match naming scheme for multi-port. din[0] to din0[0], s_en to s_en0, addr[0] to addr0[0], etc. Sram level should pass unit tests for single port but will not currently pass for multi-port
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2018-08-18 16:51:21 -07:00 |
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delay_chain.py
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Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections.
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2018-07-19 10:51:20 -07:00 |
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dff.py
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Add dff_buf for buffered flop arrays.
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2018-03-04 16:13:10 -08:00 |
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dff_array.py
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Connect data and column DFF clocks in 1 bank.
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2018-08-14 10:09:41 -07:00 |
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dff_buf.py
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Limit sizes for dff_buf too. Add comments about restriction.
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2018-07-27 08:17:50 -07:00 |
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dff_buf_array.py
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Fix routing clk connections of dff arrays
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2018-07-18 11:38:58 -07:00 |
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dff_inv.py
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Limit sizes for dff_buf too. Add comments about restriction.
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2018-07-27 08:17:50 -07:00 |
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dff_inv_array.py
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Fix routing clk connections of dff arrays
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2018-07-18 11:38:58 -07:00 |
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hierarchical_decoder.py
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Use lower case names except for leaf cells and top level
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2018-07-18 15:10:57 -07:00 |
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hierarchical_predecode.py
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Fix spacing between adjacent decoders
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2018-07-17 15:01:16 -07:00 |
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hierarchical_predecode2x4.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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hierarchical_predecode3x8.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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ms_flop.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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ms_flop_array.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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precharge_array.py
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Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines.
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2018-08-18 15:27:07 -07:00 |
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replica_bitcell.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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replica_bitline.py
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Connect data and column DFF clocks in 1 bank.
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2018-08-14 10:09:41 -07:00 |
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sense_amp.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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sense_amp_array.py
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Fix sense amp spacing after modifying index to be increment by one.
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2018-06-29 15:30:17 -07:00 |
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single_level_column_mux_array.py
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Consolidate metal pitch rules to new design class
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2018-07-09 15:42:46 -07:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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wordline_driver.py
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Modified pinvbuf to have a stage effort of 4 for driving the
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2018-07-26 11:28:48 -07:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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