Jesse Cirimelli-Low 06805d1e70 file browser does not show files in root directory; removed test file

2018-11-28 17:18:59 -08:00

..

base

Merge branch 'dev' into datasheet_gen

2018-11-20 11:23:42 -08:00

bitcells

Merge branch 'dev' into multiport_layout

2018-11-08 18:00:28 -08:00

characterizer

added another VLSI logo and fixed control port numbering

2018-11-11 07:22:13 -08:00

datasheet

file browser does not show files in root directory; removed test file

2018-11-28 17:18:59 -08:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

modules

Move via away from cell edges

2018-11-19 15:42:22 -08:00

pgates

Editted pbuf.py to pass regression.

2018-11-20 14:39:11 -08:00

router

Use grid furthest from blockages when blocked pin. Enclose multiple connectors.

2018-11-19 17:32:55 -08:00

tests

Merge branch 'dev' into datasheet_gen

2018-11-27 13:54:21 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Add magic/netgen to example config

2018-11-07 13:54:00 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py

2018-11-15 10:45:33 -08:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

options.py

Add new option to enable inline checks at each level of hierarchy. Default is off.

2018-11-13 16:51:19 -08:00

sram_1bank.py

Use array ur instead of bank ur to pace row addr dff

2018-11-19 08:41:26 -08:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

sram_base.py

Don't always add all 3 types of contorl. Add write and read only port lists.

2018-11-16 15:03:12 -08:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

added area to datasheet

2018-11-08 21:30:17 -08:00