Matt Guthaus a47509de26 Move via away from cell edges

2018-11-19 15:42:22 -08:00

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bank_select.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

bank.py

Use array ur instead of bank ur to pace row addr dff

2018-11-19 08:41:26 -08:00

bitcell_array.py

Uniquify bitcell array

2018-11-16 12:52:22 -08:00

control_logic.py

Two m1 pitches at top of control logic

2018-11-18 09:30:27 -08:00

delay_chain.py

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dff_array.py

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dff_buf_array.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_buf.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_inv_array.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff_inv.py

Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.

2018-11-16 11:48:41 -08:00

dff.py

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hierarchical_decoder.py

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hierarchical_predecode2x4.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

hierarchical_predecode3x8.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

hierarchical_predecode.py

Move via away from cell edges

2018-11-19 15:42:22 -08:00

multibank.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

precharge_array.py

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replica_bitline.py

Uniquify bitcell array

2018-11-16 12:52:22 -08:00

sense_amp_array.py

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sense_amp.py

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single_level_column_mux_array.py

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tri_gate_array.py

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tri_gate.py

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wordline_driver.py

Initial two port bank in SCMOS

2018-11-13 16:05:22 -08:00

write_driver_array.py

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write_driver.py

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