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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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06805d1e7005f5d32d26e7f1b8f0bfc14eb4c2ea
OpenRAM/compiler/bitcells
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Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
..
bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
bitcell.py
Simplify bl and br name lists.
2018-11-08 15:48:49 -08:00
pbitcell.py
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
replica_bitcell_1rw_1r.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_bitcell.py
Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.
2018-11-07 11:31:44 -08:00
replica_pbitcell.py
Move replica bitcells to new bitcells subdir
2018-10-24 09:06:29 -07:00
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