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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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06805d1e7005f5d32d26e7f1b8f0bfc14eb4c2ea
OpenRAM/compiler/verify
T
History
Matt Guthaus 831e454b34 Remove redundant DRC run in magic.
2018-11-05 13:30:42 -08:00
..
__init__.py
Add none option for verify wrapper with warning messages.
2018-09-11 10:17:24 -07:00
assura.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
calibre.py
Supply router working, perhaps not efficiently though.
2018-10-05 15:57:34 -07:00
magic.py
Remove redundant DRC run in magic.
2018-11-05 13:30:42 -08:00
none.py
Add none option for verify wrapper with warning messages.
2018-09-11 10:17:24 -07:00
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