Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the ...

clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.

2018-07-26 11:28:48 -07:00

..

bank_select.py

Consolidate metal pitch rules to new design class

2018-07-09 15:42:46 -07:00

bank.py

Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch.

2018-07-25 15:50:49 -07:00

bitcell_array.py

Revert change. Add gnd pin to right on bitline load.

2018-07-19 13:26:12 -07:00

bitcell.py

changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit

2018-05-22 14:16:51 -07:00

control_logic.py

Modified pinvbuf to have a stage effort of 4 for driving the

2018-07-26 11:28:48 -07:00

delay_chain.py

Fix s_en stages to be even per Kevin's bug report. Assert minimum fanout to ensure vdd/gnd connections.

2018-07-19 10:51:20 -07:00

dff_array.py

Move dff_array pins to center of rail

2018-07-25 15:08:04 -07:00

dff_buf_array.py

Fix routing clk connections of dff arrays

2018-07-18 11:38:58 -07:00

dff_buf.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

dff_inv_array.py

Fix routing clk connections of dff arrays

2018-07-18 11:38:58 -07:00

dff_inv.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

dff.py

Add dff_buf for buffered flop arrays.

2018-03-04 16:13:10 -08:00

hierarchical_decoder.py

Use lower case names except for leaf cells and top level

2018-07-18 15:10:57 -07:00

hierarchical_predecode2x4.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode3x8.py

First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.

2018-02-26 16:32:28 -08:00

hierarchical_predecode.py

Fix spacing between adjacent decoders

2018-07-17 15:01:16 -07:00

ms_flop_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

ms_flop.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

precharge_array.py

Route precharge_array vdd in M3

2018-04-04 13:49:55 -07:00

replica_bitcell.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00

replica_bitline.py

Rotate via in center for freepdk

2018-07-19 14:01:48 -07:00

sense_amp_array.py

Fix sense amp spacing after modifying index to be increment by one.

2018-06-29 15:30:17 -07:00

sense_amp.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

single_level_column_mux_array.py

Consolidate metal pitch rules to new design class

2018-07-09 15:42:46 -07:00

tri_gate_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

tri_gate.py

Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.

2018-03-01 23:34:15 -08:00

wordline_driver.py

Modified pinvbuf to have a stage effort of 4 for driving the

2018-07-26 11:28:48 -07:00

write_driver_array.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

write_driver.py

Organize top-level files into subdirs.

2018-02-09 10:25:24 -08:00