Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the ...

clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.

2018-07-26 11:28:48 -07:00

..

base

Remove print statement

2018-07-25 15:51:48 -07:00

characterizer

Modified pinvbuf to have a stage effort of 4 for driving the

2018-07-26 11:28:48 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Modified pinvbuf to have a stage effort of 4 for driving the

2018-07-26 11:28:48 -07:00

pgates

Modified pinvbuf to have a stage effort of 4 for driving the

2018-07-26 11:28:48 -07:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

Pass the sram design to lib instead of the sram wrapper

2018-07-18 11:51:42 -07:00

verify

Add temporary options to LVS to allow name merging

2018-07-18 15:10:29 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Fix num words in example.

2018-02-23 12:17:43 -08:00

example_config_scn3me_subm.py

Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.

2018-02-12 11:22:47 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Only print LVS/DRC stats when it is enabled

2018-07-25 13:44:34 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Improve openram output. Fix save output function name.

2018-07-12 10:35:38 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

Change DIN to DOUT in characterizer. Spacing dff flops down by m2 not m1 pitch.

2018-07-25 15:50:49 -07:00

sram_2bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_4bank.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram_base.py

Add LVS correspondence points to each bank type

2018-07-18 14:29:04 -07:00

sram.py

Add verilog_write to sram wrapper for verilog unit test

2018-07-19 10:05:30 -07:00