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OpenRAM
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280 Commits

Author SHA1 Message Date
Matt Guthaus ffcf58100e Clean up column mux by moving pins to own function. Adjust spacing between column mux and bitcell to prevent DRCs. Fix up find lowest/highest functions when no objects or instances in a module. 2018-02-02 15:17:21 -08:00
Matt Guthaus 9d043b904e Remove unnecessary design reset 2018-02-02 14:26:53 -08:00
Matt Guthaus 27dbb95c19 Fix name of column mux. 2018-02-02 14:26:39 -08:00
Matt Guthaus 9d7dc4c552 Reset even if not purging temp files. 2018-02-02 14:26:09 -08:00
Matt Guthaus 2a8199c3ca Force re-extract of cells in DRC/LVS. 2018-02-02 14:21:31 -08:00
Matt Guthaus fb90b8f5fe Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder. 2018-02-02 14:08:56 -08:00
Matt Guthaus 3be59fb762 Change DRC output for magic to drc.summary just like calibre output. 2018-02-02 14:07:15 -08:00
Matt Guthaus 63392c8d71 Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
Matt Guthaus 072c8e3174 Change LVS report file to same name as Calibre 2018-02-02 12:47:42 -08:00
Matt Guthaus ea5eda91fc Connect all gnd rails of RBL. 2018-02-02 12:27:24 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 8ef1e0af2c Replace LEF files with new changes. 2018-02-01 05:43:37 -08:00
Matt Guthaus 64546ad3dd Change wen to en in spice lib files. Check lvs report insted of stdout with netgen. 2018-02-01 05:38:48 -08:00
Matt Guthaus 512448f9e8 Fix pin names to lower case. Fix write driver DRC errors and LVS error. 2018-01-31 17:37:16 -08:00
Matt Guthaus 9fea4a1a2d Do not require hspice during tests. Check if a valid simulator is found, however. 2018-01-31 16:21:43 -08:00
Matt Guthaus 590f6e01d1 Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message. 2018-01-31 15:38:02 -08:00
Matt Guthaus acf3fe8376 Add well around column muxes. 2018-01-31 14:31:50 -08:00
mguthaus 4273a3717d Clean up messages. 2018-01-31 11:54:20 -08:00
mguthaus 4aee700331 Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class. 2018-01-31 11:48:41 -08:00
Matt Guthaus 1175f515c8 Add descriptive exceptions along with cleanup in unit test checking. 2018-01-31 10:35:51 -08:00
Matt Guthaus 58da8af619 Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array. 2018-01-31 10:04:28 -08:00
Matt Guthaus 012c3923be Create empty setup.tcl file as workaround for resetting netgen LVS options until Tim fix's bug. 2018-01-31 08:28:53 -08:00
Matt Guthaus 264d55b16c Remove temp files 2018-01-30 08:05:50 -08:00
Matt Guthaus 8fcb551953 Only perform DRC not LVS on transistors 2018-01-30 08:03:54 -08:00
Matt Guthaus 1d9274621a Only remove files when cleaning temp dir 2018-01-30 07:58:31 -08:00
Matt Guthaus 0b6eddef43 Force write the specific cell during DRC. 2018-01-29 17:00:20 -08:00
Matt Guthaus 56770f558f Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds. 2018-01-29 16:59:29 -08:00
Matt Guthaus 313e06d2af Fix pwell contact in column mux to have layers for Magic. 2018-01-29 15:53:22 -08:00
Matt Guthaus 6080b59058 Fix nand input ordering to correct netgen LVS error of wordline driver. 2018-01-29 15:36:37 -08:00
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00
Matt Guthaus 3c5ecb963d Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:15 -08:00
Matt Guthaus 586d80623e Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:00 -08:00
Matt Guthaus 31c192c2e9 Fix precharge nwell contact spacing DRC violatin. 2018-01-26 13:53:45 -08:00
Matt Guthaus e46a4fb115 Use any spice for the functional tests. 2018-01-26 13:53:11 -08:00
Matt Guthaus 028146f3c2 Add output explaining error for not finding simulator in unit tests. 2018-01-26 13:23:11 -08:00
Matt Guthaus 369aa85cd2 Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
Matt Guthaus 50107636a0 Fail test early if spice simulator is not found. 2018-01-26 12:47:32 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 1b2df3a5a1 Properly ignore ad as, pd, ps property errors 2018-01-22 17:50:53 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus 84ec7a5be0 Convert unit tests to use new options as well. 2018-01-19 17:23:38 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 72b0617e81 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-01-19 16:19:12 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00