SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.

compiler/tests/01_library_drc_test.py

@@ -26,7 +26,7 @@ class library_drc_test(unittest.TestCase):
                 drc_errors += 1
                 debug.error("Missing GDS file: {}".format(gds_name))
             drc_errors += verify.run_drc(name, gds_name)
-            self.assertEqual(drc_errors, 0)
+
         # fails if there are any DRC errors on any cells
         self.assertEqual(drc_errors, 0)
         globals.end_openram()

compiler/tests/02_library_lvs_test.py

@@ -28,7 +28,7 @@ class library_lvs_test(unittest.TestCase):
                 lvs_errors += 1
                 debug.error("Missing SPICE file {}".format(gds_name))
             lvs_errors += verify.run_lvs(f, gds_name, sp_name)
-
+            self.assertEqual(lvs_errors, 0)
         # fail if the error count is not zero
         self.assertEqual(lvs_errors, 0)
         globals.end_openram()

compiler/verify/magic.py

@@ -116,10 +116,10 @@ def write_netgen_script(cell_name, sp_name):
     #f.write("lvs {0}.spice {{{1} {0}}}\n".format(cell_name, sp_name))
     f.write("log file lvs.results\n")
     f.write("log start\n")    
+    f.write("permute default\n")
     f.write("compare hierarchical {0}{1}.spice {{{2} {1}}}\n".format(OPTS.openram_temp,
                                                                      cell_name,
                                                                      sp_name))
-    f.write("permute\n")
     f.write("run converge\n")
     f.write("log end\n")    
     f.write("quit\n")