12 Commits

Author	SHA1	Message	Date
samuelkcrow	fede082b80	cs instead of cs_buf now that everything else is working	2022-07-21 19:35:01 -07:00
samuelkcrow	30b9c2fc25	remove glitch inverters from placement functions, move glitch1 to pen row	2022-07-21 19:35:01 -07:00
samuelkcrow	606260dd68	use odd number inverter chains from delay chain for delay instead of external inverters	2022-07-21 19:35:01 -07:00
samuelkcrow	b9b57ab6b3	double length of delay chain as well	2022-07-21 19:35:01 -07:00
samuelkcrow	06254fae72	forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops	2022-07-21 19:35:01 -07:00
samuelkcrow	7d4b718344	add most functions needed for delay control logic, fix multi-delay pin order issue	2022-07-21 19:35:01 -07:00
samuelkcrow	45239ca2a9	use cs_buf for sense amp on r ports instead of cs	2022-07-21 19:35:01 -07:00
samuelkcrow	c4138c9f9b	typo in cs buf netlist function	2022-07-21 19:35:01 -07:00
samuelkcrow	11ea82e782	check delay chain pinout list, add cs_buf to control logic	2022-07-21 19:35:01 -07:00
samuelkcrow	78013d32b7	hard-code multi-delay stages	2022-07-21 19:35:01 -07:00
samuelkcrow	62a65f8053	all remaining spice for delay control	2022-07-21 19:35:01 -07:00
samuelkcrow	66502fc5dc	new control logic module with no more rbl logic, added glitches so far	2022-07-21 19:35:01 -07:00