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OpenRAM
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4,879 Commits 4 Branches 63 Tags 78 MiB
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105 Commits

Author SHA1 Message Date
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
Sam Crow d65ccfcc95 fix column mux without rbl start_bit to 0 2023-07-05 13:17:46 -07:00
Sam Crow 744ba0e892 fix precharge bit offsets in no rbl case 2023-04-25 09:24:18 -07:00
Sam Crow ae6d271602 add support for no rbl to port data 2023-04-05 15:33:45 -07:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg cf03454ecf Don't add wdriver_sel_n pins which aren't used. 2022-06-10 09:18:40 -07:00
mrg 0c3ee643ab Remove add_mod and add module whenever calling add_inst. 2021-11-22 11:33:27 -08:00
Jesse Cirimelli-Low 5792256db1 route spare col 2021-10-05 15:28:20 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Jesse Cirimelli-Low 0008df0204 catch where strap size is zero 2021-06-18 15:24:24 -07:00
Jesse Cirimelli-Low 8ceece2af6 check for valid dimensions instead of recalcuating 2021-06-18 14:21:02 -07:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
Jesse Cirimelli-Low d0e9de1f13 fix port data spare col 2021-05-04 00:41:20 -07:00
Jesse Cirimelli-Low 93b264bc4c allow spare col number override 2021-05-03 21:59:05 -07:00
Jesse Cirimelli-Low 4377619bf6 fixed port_data typo 2021-05-03 14:39:51 -07:00
Jesse Cirimelli-Low 3a3da9e0d7 56 drc errors on col mux 1port 2021-05-02 21:49:09 -07:00
Jesse Cirimelli-Low 4ea0fcd068 support multi cell wide precharge cells 2021-04-23 22:49:29 -07:00
Jesse Cirimelli-Low e976c4043b Merge branch 'dev' into laptop_checkpoint 2021-04-14 15:58:06 -07:00
Jesse Cirimelli-Low 2f1d7b879f make bank compatable with sky130 2021-04-14 15:09:25 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 611a4155b9 Add initial custom layer properties. 2020-10-27 15:11:04 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg 8cd1cba818 Fix missing via in wmask driver 2020-07-01 14:44:18 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg e14deff3d1 Fixed offset in port_data 2020-06-04 16:03:39 -07:00
Joey Kunzler 6430aad857 Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg f1b7b91b1a Use non-channel route for s8 port_data 2020-06-02 11:43:57 -07:00
mrg a1c7474f80 Revert to channel route of bitlines 2020-06-02 10:08:53 -07:00
mrg 496a24389c Remove prints 2020-05-29 16:57:47 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00