Matt Guthaus
ed28b4983b
Clean up and generalize layer rules.
...
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
2019-12-17 11:03:36 -08:00
Matt Guthaus
e143a6033f
Use layer stacks from tech file in design class and throughout
2019-12-13 14:13:41 -08:00
Hunter Nichols
3c44ce2df6
Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer.
2019-08-08 02:33:51 -07:00
Matt Guthaus
6e044b776f
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
Matt Guthaus
a234b0af88
Fix space before comment
2019-06-14 08:43:41 -07:00
mrg
fc12ea24e9
Add boundary to every module and pgate for visual debug.
2019-06-03 15:27:37 -07:00
Matt Guthaus
0f03553689
Update copyright to correct years.
2019-05-06 06:50:15 -07:00
Matt Guthaus
3f9a987e51
Update copyright. Add header to all OpenRAM files.
2019-04-26 12:33:53 -07:00
Matt Guthaus
be20408fb2
Rewrite add_contact to use layer directions.
2019-04-15 18:00:36 -07:00
Hunter Nichols
25c034f85d
Added more accurate bitline delay capacitance estimations
2019-04-09 01:56:32 -07:00
Hunter Nichols
cc5b347f42
Added analyical model test which compares measured delay to model delay.
2019-04-03 16:26:20 -07:00
Hunter Nichols
f6eefc1728
Added updated analytical characterization with combined models
2019-04-02 01:09:31 -07:00
Hunter Nichols
80a325fe32
Added corner information for analytical power estimation.
2019-03-04 19:27:53 -08:00
Hunter Nichols
0e96648211
Added linear corner factors in analytical delay model.
2019-03-04 00:42:18 -08:00
Matt Guthaus
0c3baa5172
Added some comments to the spice files.
2019-01-25 15:00:00 -08:00
Matt Guthaus
a418431a42
First draft of sram_factory code
2019-01-16 16:15:38 -08:00
Matt Guthaus
3d2abc0873
Change default col mux size to 2. Add some comments.
2018-11-07 15:43:08 -08:00
Hunter Nichols
3bb8aa7e55
Fixed import errors with mux analytical delay model.
2018-10-26 17:37:25 -07:00
Hunter Nichols
016604f846
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
Matt Guthaus
ce8c2d983d
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
Matt Guthaus
e22e658090
Converted all submodules to use _bit notation instead of [bit]
2018-10-11 09:53:08 -07:00
Michael Timothy Grimes
27427d4192
Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.
2018-09-09 22:06:29 -07:00
Matt Guthaus
e17c69be3e
Clean up new code for add_modules, add_pins and netlist/layouts.
2018-08-28 10:24:09 -07:00
Matt Guthaus
6401cbf2a6
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
Matt Guthaus
0daad338e4
All modules have split netlist/layout.
2018-08-27 11:13:34 -07:00
Matt Guthaus
94db2052dd
Consolidate metal pitch rules to new design class
2018-07-09 15:42:46 -07:00
Matt Guthaus
f34c4eb7dc
Convert entire OpenRAM to use python3. Works with Python 3.6.
...
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
2018-05-14 16:15:45 -07:00
Matt Guthaus
a6c2e77bcf
Move precharge and column mux cells to pgate directory.
...
Move gnd to M3 in column mux.
Create column mux cell unit test.
2018-04-06 17:15:14 -07:00
Matt Guthaus
bab92fcf38
Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.
2018-03-23 08:13:20 -07:00
Matt Guthaus
7100d6f904
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00