luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
4,847 Commits 5 Branches 63 Tags
e35f060d32ca625c317ceab3267b98e4c7ed0e8f
Commit Graph
643 Commits
Author SHA1 Message Date
SWalker 6bd437cfa8 Fixed bug that made metal-metal vias think they were well contacts 2023-11-07 14:27:11 -08:00
SWalker 5c22e382b5 add parameter to make routing horizonal vdd rails easier 2023-10-31 23:24:21 -07:00
SWalker a544abebf7 fixed contact area issue 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Hadir Khan 7ce11eba52 added pwell as a non-routing layer 2023-10-31 23:24:21 -07:00
Sam Crow 6e3e964c12 cleanup net_spice docstrings 2023-07-19 12:45:41 -07:00
Sam Crow f41537b508 Merge branch 'char' into STA-refactor 2023-07-19 12:35:22 -07:00
Sam Crow 2ced895b32 add BIAS pin type back to valid types 2023-07-19 12:15:47 -07:00
Sam Crow c67fdd8bd8 fix insts typo 2023-07-19 12:15:21 -07:00
Bugra Onal d53353b5be Merge branch 'dev' into char 2023-07-19 12:06:34 -07:00
Sam Crow 2b9e70d318 remove line ending whitespace from comment 2023-07-19 10:51:19 -07:00
Sam Crow bfabe64f33 fix pin/net dictionary deepcopy-ing 2023-07-18 16:14:38 -07:00
Sam Crow 5907cbb3e2 remove pins overwrite from contact class 2023-07-18 16:12:42 -07:00
Sam Crow aa71785bd5 fix circular import with pin and net 2023-07-18 11:28:30 -07:00
Sam Crow 478c76c1ca get connections from spice objects in instances 2023-07-18 10:50:50 -07:00
Sam Crow 8a441bc68b Merge branch 'dev' into STA-refactor 2023-07-17 16:35:31 -07:00
Sam Crow 45b88889e4 use pin and net objects in connect_inst 2023-07-17 16:04:56 -07:00
Sam Crow d0339a90e6 change spice_nets and spice_pins to dicts 2023-07-17 15:36:57 -07:00
Sam Crow e15feb2361 change nets list to dictionary 2023-07-17 15:36:22 -07:00
Sam Crow 7581df2255 change pins to OrderedDict 2023-07-17 15:22:35 -07:00
Sam Crow c8c43f75d9 add spice nets and a way to connect them to pins 2023-07-14 16:18:10 -07:00
Sam Crow 146efc5070 implement pin_spice object 2023-07-13 16:45:05 -07:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Bugra Onal dae275c508 Merge branch 'dev' into char 2023-04-12 12:00:31 -07:00
Jacob Walker fef9902c45 rom base passing tests with top level routing 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
Bugra Onal 613146520e Merge branch 'library' into char 2023-02-23 15:11:39 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
Bugra Onal c8a06a1317 Properly trim wrapped instances 2023-02-17 14:27:15 -08:00
Bugra Onal 9002a8ac70 Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Bugra Onal a7cbf254be Merge branch 'dev' into char 2023-01-19 12:18:38 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
mrg 7ddb1a39dc Line wrap output spice subckt and instance lines at 80 characters. 2022-12-12 13:58:30 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan 2e7206343e Remove unnecessary imports 2022-11-27 13:11:10 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Bugra Onal 2b79646b8f Merge branch 'dev' into char 2022-10-04 09:09:52 -07:00
Bugra Onal 05ab45f39b Added graph store and read functionality 2022-08-30 09:15:35 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
mrg 28128157c0 Initial work on separate delay and func simulation 2022-08-10 12:06:14 -07:00