Sam Crow 2b9e70d318 remove line ending whitespace from comment

2023-07-19 10:51:19 -07:00

..

__init__.py

Verilog ROM model created for testing

2023-06-12 15:35:54 -07:00

channel_route.py

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contact.py

remove pins overwrite from contact class

2023-07-18 16:12:42 -07:00

delay_data.py

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design.py

change pins to OrderedDict

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errors.py

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geometry.py

remove line ending whitespace from comment

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hierarchy_design.py

get connections from spice objects in instances

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hierarchy_layout.py

fix pin/net dictionary deepcopy-ing

2023-07-18 16:14:38 -07:00

hierarchy_spice.py

fix pin/net dictionary deepcopy-ing

2023-07-18 16:14:38 -07:00

lef.py

implement pin_spice object

2023-07-13 16:45:05 -07:00

logical_effort.py

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pin_layout.py

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power_data.py

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rom_verilog.py

Fixed formatting on all files

2023-06-14 12:28:36 -07:00

route.py

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timing_graph.py

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utils.py

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vector3d.py

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vector.py

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verilog.py

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wire_path.py

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wire_spice_model.py

add fixme note for unit conversion

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wire.py

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