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__init__.py
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Verilog ROM model created for testing
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2023-06-12 15:35:54 -07:00 |
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channel_route.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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contact.py
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Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.
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2023-10-31 23:24:21 -07:00 |
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delay_data.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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design.py
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Merge branch 'char' into STA-refactor
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2023-07-19 12:35:22 -07:00 |
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errors.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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geometry.py
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remove line ending whitespace from comment
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2023-07-19 10:51:19 -07:00 |
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hierarchy_design.py
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get connections from spice objects in instances
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2023-07-18 10:50:50 -07:00 |
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hierarchy_layout.py
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Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.
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2023-10-31 23:24:21 -07:00 |
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hierarchy_spice.py
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cleanup net_spice docstrings
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2023-07-19 12:45:41 -07:00 |
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lef.py
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implement pin_spice object
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2023-07-13 16:45:05 -07:00 |
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logical_effort.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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pin_layout.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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power_data.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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rom_verilog.py
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Fixed formatting on all files
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2023-06-14 12:28:36 -07:00 |
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route.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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timing_graph.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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utils.py
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2023-01-28 22:56:27 -08:00 |
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vector.py
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2023-01-28 22:56:27 -08:00 |
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vector3d.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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verilog.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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wire.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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wire_path.py
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Update copyright year
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2023-01-28 22:56:27 -08:00 |
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wire_spice_model.py
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add fixme note for unit conversion
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2023-06-28 14:05:42 -07:00 |
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