 mrg
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c12720a93f
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Extend pin correct length in new array.
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2020-09-14 12:53:59 -07:00 |
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mrg
|
e95ab66916
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Update to space according to the bitcell array.
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2020-09-14 12:05:45 -07:00 |
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mrg
|
4482c63d6f
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Fix sense amp offset index error
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2020-09-11 17:12:29 -07:00 |
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mrg
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8909ad7165
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Update modules to use variable bit offsets.
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
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2020-09-11 15:36:22 -07:00 |
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mrg
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c58741c44f
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Updates to global array.
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
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2020-09-10 16:44:54 -07:00 |
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mrg
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9c762634a5
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Change default options for replica_bitcell_array
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2020-09-10 15:11:48 -07:00 |
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mrg
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71d86f88b0
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Merge branch 'dev' into wlbuffer
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2020-09-10 13:05:14 -07:00 |
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mrg
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f2313d0c73
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Use default names for replica_column too
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2020-09-10 12:04:46 -07:00 |
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mrg
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3c0707e5d1
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Consistents of bl x port then br x port
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2020-09-09 13:38:13 -07:00 |
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mrg
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3062aba214
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Fix update to exclude bits with RBLs
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2020-09-09 13:03:05 -07:00 |
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mrg
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138cbfac15
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Flatten dummy pbitcell too
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2020-09-09 12:58:22 -07:00 |
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mrg
|
12fd60e8c3
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Fix pbitcell array test
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2020-09-09 12:02:09 -07:00 |
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mrg
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7bb21fb73f
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Updates to local and global arrays to make bitline and wordlines consistent.
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2020-09-09 11:54:46 -07:00 |
|
 Hunter Nichols
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af22e438f1
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Added option to output an extended configuration file that includes defaults.
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2020-09-08 18:40:39 -07:00 |
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mrg
|
8e91ec1770
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Add check_pins function
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2020-09-08 13:31:50 -07:00 |
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mrg
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1269bf6e16
|
Global bitcell working
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2020-09-04 13:06:58 -07:00 |
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|
Hunter Nichols
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8bcbf005bf
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Merge branch 'dev' into characterizer_bug_fixes
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2020-09-04 02:25:01 -07:00 |
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Hunter Nichols
|
500327d59b
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Fixed import in simulation and fixed names in functional
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2020-09-04 02:24:18 -07:00 |
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mrg
|
1534295326
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Ground dummy lines in replica bitcell array
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2020-09-03 14:04:20 -07:00 |
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mrg
|
f6f6242d68
|
Ground dummy lines in replica bitcell array
|
2020-09-03 10:45:28 -07:00 |
|
|
Hunter Nichols
|
d027632bdc
|
Moved majority of code duplicated between delay and functional to simulation
|
2020-09-02 14:22:18 -07:00 |
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mrg
|
4ec47d8ee1
|
Refactor global and local to be a bitcell_base_array
|
2020-09-01 11:59:01 -07:00 |
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mrg
|
c1c631abe1
|
Global bitcell array passes LVS/DRC
|
2020-09-01 10:57:49 -07:00 |
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mrg
|
7bdce3ca9a
|
Don't make dummy bitlines pins for simplicity
|
2020-09-01 09:55:23 -07:00 |
|
|
Hunter Nichols
|
13b1d4613c
|
Moved spice naming checking code from design to the spice base module
|
2020-08-31 14:36:13 -07:00 |
|
|
Hunter Nichols
|
73b2277daa
|
Removed dead code related to older characterization scheme
|
2020-08-27 17:30:58 -07:00 |
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|
mrg
|
c1c1535210
|
Merge branch 'wlbuffer' into dev
|
2020-08-27 15:44:29 -07:00 |
|
|
Hunter Nichols
|
42f2ff679e
|
Removed dead code from delay and base module related to characterization
|
2020-08-27 15:40:41 -07:00 |
|
|
mrg
|
11a82b7283
|
Fixed local bitcell array for single and dual port
|
2020-08-27 14:03:05 -07:00 |
|
|
mrg
|
da827d923f
|
Merge branch 'wlbuffer' into dev
|
2020-08-26 10:00:34 -07:00 |
|
|
mrg
|
c321d85595
|
Fix syntax error for dual port
|
2020-08-26 09:54:41 -07:00 |
|
|
mrg
|
e92337ddaf
|
Separate get_ and get_all for bitlines and wordlines
|
2020-08-25 17:08:48 -07:00 |
|
|
mrg
|
652f160aca
|
Merge branch 'wlbuffer' into dev
|
2020-08-25 15:50:08 -07:00 |
|
|
mrg
|
bdb18b4cab
|
Fix disconnected replica pins
|
2020-08-25 14:51:49 -07:00 |
|
|
mrg
|
bd8bf9afd8
|
Remove RBL label at top level of SRAM
|
2020-08-25 14:42:21 -07:00 |
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|
mrg
|
856cce1e62
|
Add -json for detailed LVS output
|
2020-08-25 13:58:28 -07:00 |
|
|
mrg
|
28bd93bf51
|
Still working on array refactor
|
2020-08-25 11:50:44 -07:00 |
|
|
mrg
|
8dee5520e0
|
Standardize array names independent of bitcell
|
2020-08-21 13:44:35 -07:00 |
|
|
mrg
|
b762580ee2
|
Skip global test for now
|
2020-08-19 11:36:21 -07:00 |
|
|
mrg
|
593a98e29a
|
Update local bitcell array for dual port
|
2020-08-19 11:35:55 -07:00 |
|
|
mrg
|
e215c0e016
|
Drafting global bitcell array
|
2020-08-18 16:30:55 -07:00 |
|
|
mrg
|
5776788574
|
Order of wordlines and bitlines in bank
|
2020-08-18 16:30:38 -07:00 |
|
|
mrg
|
224e359208
|
Fix pin order for replica array
|
2020-08-18 15:59:05 -07:00 |
|
|
mrg
|
f58fc6579f
|
Rename local/global tests
|
2020-08-18 15:58:44 -07:00 |
|
|
mrg
|
e3e4bac922
|
Fix replica bitcell array for right only RBL
|
2020-08-18 15:47:52 -07:00 |
|
|
mrg
|
59d65c46c3
|
Fix bug in not adding RBLs in local bitcell array
|
2020-08-18 15:11:10 -07:00 |
|
|
mrg
|
2643a96f97
|
Order inputs wordline, bitline, supply
|
2020-08-18 14:29:36 -07:00 |
|
|
mrg
|
b288bba43e
|
Add global bitcell array test
|
2020-08-18 14:29:23 -07:00 |
|
|
mrg
|
f98fbb175b
|
Merge branch 'wlbuffer' into dev
|
2020-08-18 10:06:52 -07:00 |
|
|
mrg
|
e37a9234cc
|
Update replica column call to new refactor
|
2020-08-18 09:14:50 -07:00 |
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