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OpenRAM
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3984 Commits

Author SHA1 Message Date
K.Makise bc4347eadc
Merge d4dc7e94a2 into f2db9fe2de 2026-04-21 19:28:07 +05:30
Gabriel Wicki 5cd43442b8 compiler: gdsMill: Modernize codebase. 
* compiler/gdsMill/pyx/graph/axis/tick.py: Modernize.
 2026-04-17 13:14:03 +02:00
Matthew Guthaus 9274fbd4f2 Merge branch 'stable' into dev 2026-04-08 11:26:03 -07:00
Matthew Guthaus 449781d239 Revert "Revert "Update defunct code"" 
This reverts commit d142b906ee.
 2026-04-08 11:25:48 -07:00
Matt Guthaus d142b906ee
Revert "Update defunct code" 2026-04-08 11:19:03 -07:00
Gabriel Wicki e01e6a567d compiler: gdsMill: Modernize codebase. 
The few Python 2 statements are replaced with their modern
counterparts.  These are one of the following:
 - print() function calls (instead of statements),
 - Exception and Error raising,
 - passing/receiving tuples as function/lambda arguments,
 - the L suffix for numeral constants.

* compiler/gdsMill/pyx/box.py,
  compiler/gdsMill/pyx/connector.py,
  compiler/gdsMill/pyx/deformer.py,
  compiler/gdsMill/pyx/dvifile.py,
  compiler/gdsMill/pyx/epsfile.py,
  compiler/gdsMill/pyx/font/afm.py,
  compiler/gdsMill/pyx/font/t1font.py,
  compiler/gdsMill/pyx/graph/axis/texter.py,
  compiler/gdsMill/pyx/graph/axis/tick.py,
  compiler/gdsMill/sram_examples/cell6tDemo.py,
  compiler/gdsMill/sram_examples/newcell.py: Modernize syntax.
 2026-03-31 22:44:21 +02:00
Gabriel Wicki 26e11044db compiler: multibank: Fix syntax error. 
* compiler/modules/multibank.py (multibank) [compute_sizes]: Fix
syntax error.
 2026-03-31 22:28:10 +02:00
Jesse Cirimelli-Low ab33017fe2
Merge pull request #282 from ruhai-lin/stable 
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
 2026-03-12 10:47:23 -07:00
rlin50 6d14626a75 Fix address bit ordering in sky130 1rw characterization 2026-02-23 15:32:08 -08:00
Maarten Boersma 7382ea7dda
fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene 2026-01-16 15:05:28 +01:00
FriedrichWu a0ff83c00a solve overlap of wmask in channel router 2024-12-23 23:44:21 +01:00
FriedrichWu 48a7065b31 make channel router better 2024-12-23 19:38:42 +01:00
FriedrichWu 691f7a989e speed up constructive approach in 1rw-only 2024-12-23 17:19:19 +01:00
FriedrichWu 70ed2a506e deleting spacing, add ci test, fixing merge error 2024-12-22 12:14:57 +01:00
FriedrichWu 474a240f38 move apporach select to options.py 2024-12-21 18:22:06 +01:00
FriedrichWu bda3adf9f9 more stable 2024-12-16 00:13:40 +01:00
FriedrichWu 4fe635a05f add route_outside, remove unused methods 2024-11-20 16:24:26 +01:00
FriedrichWu 86588619fd first commt 2024-11-17 10:35:01 +01:00
mrg bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev 2024-11-12 09:49:00 -08:00
FriedrichWu f56460bb94 make code clean 2024-11-12 17:02:02 +01:00
Tristan Robitaille 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard 2024-11-10 14:31:52 +01:00
FriedrichWu 1f1f064036 fix clk csb overlap problem 2024-10-31 09:44:11 +01:00
FriedrichWu 434063656f fix bugs in channel routing, which will add strange shape in m2 at dff pins 2024-10-31 09:43:34 +01:00
FriedrichWu 61f5ff6ec4 updata io_pin_placer 2024-10-30 13:24:53 +01:00
FriedrichWu ee6be23cfa first comment 2024-09-17 11:54:30 +02:00
FriedrichWu 20e454925a add io placer 2024-09-05 10:14:00 +02:00
FriedrichWu 6743049d44 clean version 2024-09-05 10:08:59 +02:00
FriedrichWu 0ae194f17c Simple version fix 2024-08-20 09:28:48 +02:00
FriedrichWu 725c4423cf fix 2024-07-30 16:11:40 +02:00
FriedrichWu e3170abd01 Simple version without lvs(rutiime problem with magic 2024-07-30 15:04:47 +02:00
FriedrichWu e6ca825157 recrusive placement of dffs-naive edition 2024-07-22 10:44:06 +02:00
FriedrichWu fb7f92394b fix the [0] problem in spare_wen 2024-07-15 14:59:25 +02:00
FriedrichWu 8ecdc939d0 temp_fix of gds/lef cell name not unique problem, not elegant 2024-07-10 13:30:23 +02:00
FriedrichWu 4efc0e688b fix the lef file problem partly, spare_wen0[0] left 2024-07-03 21:14:32 +02:00
FriedrichWu f69f8de000 first commit 2024-06-26 17:40:22 +02:00
FriedrichWu 3ee769a771 first commit 
change one sram into several single macros
 2024-06-21 13:48:42 +02:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Eren Dogan 0cf60a6a18 Give u+x permissions for rom tests 2024-01-20 17:49:52 -08:00
Eren Dogan 55e5c425e9 Fix same file error and enable passing tests 2024-01-20 08:38:18 -08:00
Eren Dogan 14c219d9f1 Enable working tests from disabled stamps 2024-01-19 15:16:30 -08:00
Eren Dogan 855139bc4e Add Makefile target to run broken tests only 2024-01-19 15:15:52 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
mole99 8032fa75a4 Add LEF output for ROM 2023-12-21 08:07:49 +01:00
Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
Eren Dogan efd43c3191 Merge branch 'dev' into issue_fix 2023-12-06 13:30:22 -08:00
Eren Dogan 7531e38cad Remove unused local variable 2023-12-05 11:18:58 -08:00
Eren Dogan 39a66fcb87 Fix some lint errors 2023-12-05 11:16:22 -08:00
Eren Dogan 6cfb22959c Remove unused imports 2023-12-05 11:08:32 -08:00
SWalker 6bd437cfa8 Fixed bug that made metal-metal vias think they were well contacts 2023-11-07 14:27:11 -08:00
SWalker b9570b8ddf removed gf180 specific code from ptx 2023-11-07 01:01:05 -08:00