mirror of https://github.com/VLSIDA/OpenRAM.git
fix the lef file problem partly, spare_wen0[0] left
This commit is contained in:
FriedrichWu
parent
f69f8de000
commit
4efc0e688b
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@ -54,20 +54,20 @@ class sram_1bank(design, verilog, lef):
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self.has_rbl = OPTS.control_logic != "control_logic_delay"
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def add_pin_bank(self):
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# do not now why need this
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# lef file use this pin name, should be same with new pin
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""" Adding pins for Bank module"""
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for port in self.read_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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self.add_pin("dout{0}_{1}".format(port, bit), "OUTPUT")
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self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
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for port in self.all_ports:
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if self.has_rbl:
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self.add_pin("rbl_bl_{0}_{0}".format(port), "OUTPUT")
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self.add_pin("rbl_bl{0}".format(port), "OUTPUT")
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for port in self.write_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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self.add_pin("din{0}_{1}".format(port, bit), "INPUT")
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self.add_pin("bank_din{0}[{1}]".format(port, bit), "INPUT")
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for port in self.all_ports:
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for bit in range(self.bank_addr_size):
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self.add_pin("addr{0}_{1}".format(port, bit), "INPUT")
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self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
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# For more than one bank, we have a bank select and name
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# the signals gated_*.
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@ -78,9 +78,9 @@ class sram_1bank(design, verilog, lef):
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for port in self.write_ports:
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self.add_pin("w_en{0}".format(port), "INPUT")
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for bit in range(self.num_wmasks):
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self.add_pin("bank_wmask{0}_{1}".format(port, bit), "INPUT")
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self.add_pin("bank_wmask{0}[{1}]".format(port, bit), "INPUT")
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for bit in range(self.num_spare_cols):
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self.add_pin("bank_spare_wen{0}_{1}".format(port, bit), "INPUT")
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self.add_pin("bank_spare_wen{0}[{1}]".format(port, bit), "INPUT")
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for port in self.all_ports:
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self.add_pin("wl_en{0}".format(port), "INPUT")
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@ -100,14 +100,14 @@ class sram_1bank(design, verilog, lef):
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self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
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def add_pin_row_addr_dff(self):
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# do not know why we need this
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# lef file use this pin name, should be same with new pin
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for port in self.all_ports:
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for bit in range(self.row_addr_size):
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#input
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self.add_pin("addr{}[{}]".format(port, bit + self.col_addr_size), "INPUT")
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print("addr{}[{}]".format(port, bit), "INPUT")
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#output
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self.add_pin("a{}_{}".format(port, bit + self.col_addr_size), "OUTPUT")
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self.add_pin("a{}[{}]".format(port, bit + self.col_addr_size), "OUTPUT")
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#clk_buf, regard as input
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self.add_pin("clk_buf{}".format(port), "INPUT")
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# Standard supply and ground names
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@ -126,13 +126,13 @@ class sram_1bank(design, verilog, lef):
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self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
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def add_pin_col_addr_dff(self):
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# do not know why we need this
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# lef file use this pin name, should be same with new pin
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for port in self.all_ports:
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for bit in range(self.col_addr_size):
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#input
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self.add_pin("addr{}[{}]".format(port, bit), "INPUT")
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#output
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self.add_pin("a{}_{}".format(port, bit), "OUTPUT")
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self.add_pin("a{}[{}]".format(port, bit), "OUTPUT")
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#clk_buf, regard as input
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self.add_pin("clk_buf{}".format(port), "INPUT")
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# Standard supply and ground names
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@ -151,13 +151,13 @@ class sram_1bank(design, verilog, lef):
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self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
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def add_pin_data_dff(self):
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# do not know why we need this
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# lef file use this pin name, should be same with new pin
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for port in self.all_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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# input
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self.add_pin("din{}[{}]".format(port, bit), "INPUT")
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# output
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self.add_pin("bank_din{}_{}".format(port, bit), "OUTPUT")
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self.add_pin("bank_din{}[{}]".format(port, bit), "OUTPUT")
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#clk_buf, regard as input
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self.add_pin("clk_buf{}".format(port), "INPUT")
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# Standard supply and ground names
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@ -176,13 +176,13 @@ class sram_1bank(design, verilog, lef):
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self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
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def add_pin_wmask_dff(self):
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# do not know why we need this
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# lef file use this pin name, should be same with new pin
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for port in self.all_ports:
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for bit in range(self.num_wmasks):
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# input
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self.add_pin("wmask{}[{}]".format(port, bit), "INPUT")
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# output
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self.add_pin("bank_wmask{}_{}".format(port, bit), "OUTPUT")
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self.add_pin("bank_wmask{}[{}]".format(port, bit), "OUTPUT")
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#clk_buf, regard as input
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self.add_pin("clk_buf{}".format(port), "INPUT")
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# Standard supply and ground names
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@ -201,13 +201,13 @@ class sram_1bank(design, verilog, lef):
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self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
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def add_pin_spare_wen_dff(self):
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# do not know why we need this
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# lef file use this pin name, should be same with new pin
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for port in self.all_ports:
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for bit in range(self.num_spare_cols):
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# input
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self.add_pin("spare_wen{}[{}]".format(port, bit), "INPUT")
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# output
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self.add_pin("bank_spare_wen{}_{}".format(port, bit), "OUTPUT")
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self.add_pin("bank_spare_wen{}[{}]".format(port, bit), "OUTPUT")
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#clk_buf, regard as input
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self.add_pin("clk_buf{}".format(port), "INPUT")
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# Standard supply and ground names
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@ -226,7 +226,7 @@ class sram_1bank(design, verilog, lef):
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self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
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def add_pin_control(self):
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#Do not know why we need this
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# lef file use this pin name, should be same with new pin
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for port in self.all_ports:
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# Inputs
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self.add_pin("csb{}".format(port), "INPUT")
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@ -1010,7 +1010,7 @@ class sram_1bank(design, verilog, lef):
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# input
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pins_to_route.append("spare_wen{}[{}]".format(port, bit))
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# output
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pins_to_route.append("bank_spare_wen{}_{}".format(port, bit))
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pins_to_route.append("bank_spare_wen{}[{}]".format(port, bit))
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#clk_buf, regard as input
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pins_to_route.append("clk_buf{}".format(port))
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@ -1040,7 +1040,7 @@ class sram_1bank(design, verilog, lef):
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# output
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self.add_io_pin(self.spare_wen_dff_insts[port],
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"dout_{}".format(port, bit),
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"bank_spare_wen{}_{}".format(port, bit),
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"bank_spare_wen{}[{}]".format(port, bit),
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start_layer=pin_layer)
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#clk_buf, regard as input
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self.add_io_pin(self.spare_wen_dff_insts[port],
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@ -1057,7 +1057,7 @@ class sram_1bank(design, verilog, lef):
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# input
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pins_to_route.append("wmask{}[{}]".format(port, bit))
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# output
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pins_to_route.append("bank_wmask{}_{}".format(port, bit))
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pins_to_route.append("bank_wmask{}[{}]".format(port, bit))
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#clk_buf, regard as input
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pins_to_route.append("clk_buf{}".format(port))
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@ -1087,7 +1087,7 @@ class sram_1bank(design, verilog, lef):
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# output
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self.add_io_pin(self.wmask_dff_insts[port],
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"dout_{}".format(bit),
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"bank_wmask{}_{}".format(port, bit),
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"bank_wmask{}[{}]".format(port, bit),
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start_layer=pin_layer)
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#clk_buf, regard as input
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self.add_io_pin(self.wmask_dff_insts[port],
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@ -1104,7 +1104,7 @@ class sram_1bank(design, verilog, lef):
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# input
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pins_to_route.append("din{}[{}]".format(port, bit))
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# output
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pins_to_route.append("bank_din{}_{}".format(port, bit))
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pins_to_route.append("bank_din{}[{}]".format(port, bit))
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#clk_buf, regard as input
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pins_to_route.append("clk_buf{}".format(port))
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@ -1134,7 +1134,7 @@ class sram_1bank(design, verilog, lef):
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# output
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self.add_io_pin(self.data_dff_insts[port],
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"dout_{}".format(bit),
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"bank_din{}_{}".format(port, bit),
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"bank_din{}[{}]".format(port, bit),
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start_layer=pin_layer)
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#clk_buf, regard as input
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self.add_io_pin(self.data_dff_insts[port],
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@ -1151,7 +1151,7 @@ class sram_1bank(design, verilog, lef):
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#input
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pins_to_route.append("addr{}[{}]".format(port, bit))
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#output
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pins_to_route.append("a{}_{}".format(port, bit))
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pins_to_route.append("a{}[{}]".format(port, bit))
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#clk_buf, regard as input
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pins_to_route.append("clk_buf{}".format(port))
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@ -1181,7 +1181,7 @@ class sram_1bank(design, verilog, lef):
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#output
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self.add_io_pin(self.col_addr_dff_insts[port],
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"dout_{}".format(bit),
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"a{}_{}".format(port, bit),
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"a{}[{}]".format(port, bit),
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start_layer=pin_layer)
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#clk_buf, regard as input
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self.add_pin(self.col_addr_dff_insts[port],
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@ -1198,7 +1198,7 @@ class sram_1bank(design, verilog, lef):
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#input
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pins_to_route.append("addr{}[{}]".format(port, bit + self.col_addr_size))
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#output
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pins_to_route.append("a{}_{}".format(port, bit + self.col_addr_size))
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pins_to_route.append("a{}[{}]".format(port, bit + self.col_addr_size))
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#clk_buf, regard as input
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pins_to_route.append("clk_buf{}".format(port))
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@ -1231,7 +1231,7 @@ class sram_1bank(design, verilog, lef):
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#output
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self.add_io_pin(self.row_addr_dff_insts[port],
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"dout_{}".format(bit + self.col_addr_size),
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"a{}_{}".format(port, bit + self.col_addr_size),
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"a{}[{}]".format(port, bit + self.col_addr_size),
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start_layer=pin_layer)
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#clk_buf, regard as input
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self.add_io_pin(self.row_addr_dff_insts[port],
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@ -1332,10 +1332,10 @@ class sram_1bank(design, verilog, lef):
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pins_to_route.append("rbl_bl{0}".format(port))
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for port in self.write_ports:
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for bit in range(self.word_size + self.num_spare_cols):
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pins_to_route.append("bank_din{0}_{1}".format(port, bit))
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pins_to_route.append("bank_din{0}[{1}]".format(port, bit))
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for port in self.all_ports:
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for bit in range(self.bank_addr_size):
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pins_to_route.append("addr{0}_{1}".format(port, bit))
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pins_to_route.append("addr{0}[{1}]".format(port, bit))
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# For more than one bank, we have a bank select and name
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# the signals gated_*.
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@ -1346,9 +1346,9 @@ class sram_1bank(design, verilog, lef):
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for port in self.write_ports:
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pins_to_route.append("w_en{0}".format(port))
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for bit in range(self.num_wmasks):
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pins_to_route.append("bank_wmask{0}_{1}".format(port, bit))
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pins_to_route.append("bank_wmask{0}[{1}]".format(port, bit))
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for bit in range(self.num_spare_cols):
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pins_to_route.append("bank_spare_wen{0}_{1}".format(port, bit))
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pins_to_route.append("bank_spare_wen{0}[{1}]".format(port, bit))
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for port in self.all_ports:
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pins_to_route.append("wl_en{0}".format(port))
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@ -1385,14 +1385,14 @@ class sram_1bank(design, verilog, lef):
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for bit in range(self.word_size + self.num_spare_cols):
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self.add_io_pin(self.bank_inst,
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"din{0}_{1}".format(port, bit),
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"bank_din{0}_{1}".format(port, bit),
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"bank_din{0}[{1}]".format(port, bit),
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start_layer=pin_layer)
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# manuel change position, so not at same y
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for port in self.all_ports:
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for bit in range(self.bank_addr_size):
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self.change_layout_pin_position(self.bank_inst,
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"addr{0}_{1}".format(port, bit),
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"addr{0}_{1}".format(port, bit),
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"addr{0}[{1}]".format(port, bit),
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start_layer=pin_layer,
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distance=bit)
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for port in self.read_ports:
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@ -1416,12 +1416,12 @@ class sram_1bank(design, verilog, lef):
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for bit in range(self.num_wmasks):
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self.add_io_pin(self.bank_inst,
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"bank_wmask{0}_{1}".format(port, bit),
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"bank_wmask{0}_{1}".format(port, bit),
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"bank_wmask{0}[{1}]".format(port, bit),
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start_layer=pin_layer)
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for bit in range(self.num_spare_cols):
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self.add_io_pin(self.bank_inst,
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"bank_spare_wen{0}_{1}".format(port, bit),
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"bank_spare_wen{0}_{1}".format(port, bit),
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"bank_spare_wen{0}[{1}]".format(port, bit),
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start_layer=pin_layer)
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if port in self.all_ports:
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self.add_io_pin(self.bank_inst,
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