Commit Graph
3965 Commits
Author SHA1 Message Date
Jesse Cirimelli-Low b2b069ce11 Merge pull request #304 from ThVerg/fix-sky130-narrow-nfet-model
sky130: use special_nfet_01v8 model for sub-0.42um nfets
2026-08-16 10:01:32 -07:00
ThVerg 5696584608 Fix nix develop invocation for verification scripts
run_script() launches the DRC/LVS scripts with

    nix develop --command <script>

from a working directory of OPTS.openram_temp. nix develop resolves its
flake from the working directory, and the temp directory has no
flake.nix, so the command fails before the script ever runs:

    path '/tmp/openram_<user>_<pid>_temp' does not contain a 'flake.nix', searching up
    error: could not find a flake.nix file

Nothing is written to the report file, so verification then dies on the
missing output rather than on the nix error itself, which makes this
confusing to diagnose:

    ERROR: file magic.py: Unable to load LVS results from
    /tmp/openram_<user>_<pid>_temp/<name>.lvs.report
    FileNotFoundError: [Errno 2] No such file or directory

Name the flake explicitly so it is resolved from the repository while
the script still runs in the temp directory, which the scripts depend on
for their relative copies.

Verified on a sky130 build with use_nix = True: before the change no
report is produced and the run asserts, after it both DRC and LVS run
through the devShell and write their reports.
2026-08-11 15:03:55 +02:00
ThVerg 1123f733bd sky130: use special_nfet_01v8 model for sub-0.42um nfets
The sky130 magic techfile splits nfet extraction on device width:

  device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet ... w>=0.42
  device msubcircuit sky130_fd_pr__special_nfet_01v8 scnfet ... w<0.42

ptx always emitted spice["nmos"], so every gate built from a
minimum-width device (drc["minwidth_tx"] = 0.36) was netlisted as
sky130_fd_pr__nfet_01v8 while magic extracted it as
sky130_fd_pr__special_nfet_01v8. netgen then reported a device class
mismatch in each such cell:

  Circuit 1: sky130_fd_pr__special_nfet_01v8 (1) | Circuit 2: (no matching element)
  Circuit 1: (no matching element)               | Circuit 2: sky130_fd_pr__nfet_01v8 (1)

The signed-off macros shipped in sky130A/libs.ref/sky130_sram_macros use
special_nfet_01v8 at this geometry, so this restores the naming those
were built with.

ptx now asks the technology for a narrow-device model, keyed by width.
Technologies that declare no such model are unaffected, and there is no
equivalent split for pfets so only the nmos is declared.

After this change pinv and pinv_dec report "Netlists match uniquely"
where they previously mismatched. Verified with ngspice that
special_nfet_01v8 resolves through sky130.lib.spice, so characterization
is unaffected.
Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>
Claude-Session: https://claude.ai/code/session_01FcKSuKSchDEd7MqT8AffpN
2026-08-11 14:56:13 +02:00
Jesse Cirimelli-Low ed369f1af4 change spare cols routing from channel to normal routing to avoid short circuits 2026-06-24 14:04:21 -07:00
Jesse Cirimelli-Low 734be5403e fix naming for spare cols 2026-06-24 11:27:28 -07:00
Jesse Cirimelli-Low cbd2bd7c2e switch from conda to nix for tooling 2026-05-11 10:44:24 -07:00
Gabriel Wicki 5cd43442b8 compiler: gdsMill: Modernize codebase.
* compiler/gdsMill/pyx/graph/axis/tick.py: Modernize.
2026-04-17 13:14:03 +02:00
Matthew Guthaus 9274fbd4f2 Merge branch 'stable' into dev 2026-04-08 11:26:03 -07:00
Matthew Guthaus 449781d239 Revert "Revert "Update defunct code""
This reverts commit d142b906ee.
2026-04-08 11:25:48 -07:00
Matt Guthaus d142b906ee Revert "Update defunct code" 2026-04-08 11:19:03 -07:00
Gabriel Wicki e01e6a567d compiler: gdsMill: Modernize codebase.
The few Python 2 statements are replaced with their modern
counterparts.  These are one of the following:
 - print() function calls (instead of statements),
 - Exception and Error raising,
 - passing/receiving tuples as function/lambda arguments,
 - the L suffix for numeral constants.

* compiler/gdsMill/pyx/box.py,
  compiler/gdsMill/pyx/connector.py,
  compiler/gdsMill/pyx/deformer.py,
  compiler/gdsMill/pyx/dvifile.py,
  compiler/gdsMill/pyx/epsfile.py,
  compiler/gdsMill/pyx/font/afm.py,
  compiler/gdsMill/pyx/font/t1font.py,
  compiler/gdsMill/pyx/graph/axis/texter.py,
  compiler/gdsMill/pyx/graph/axis/tick.py,
  compiler/gdsMill/sram_examples/cell6tDemo.py,
  compiler/gdsMill/sram_examples/newcell.py: Modernize syntax.
2026-03-31 22:44:21 +02:00
Gabriel Wicki 26e11044db compiler: multibank: Fix syntax error.
* compiler/modules/multibank.py (multibank) [compute_sizes]: Fix
syntax error.
2026-03-31 22:28:10 +02:00
Jesse Cirimelli-Low ab33017fe2 Merge pull request #282 from ruhai-lin/stable
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
2026-03-12 10:47:23 -07:00
rlin50 6d14626a75 Fix address bit ordering in sky130 1rw characterization 2026-02-23 15:32:08 -08:00
Maarten Boersma 7382ea7dda fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene 2026-01-16 15:05:28 +01:00
mrg bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev 2024-11-12 09:49:00 -08:00
Tristan Robitaille 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard 2024-11-10 14:31:52 +01:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Eren Dogan 0cf60a6a18 Give u+x permissions for rom tests 2024-01-20 17:49:52 -08:00
Eren Dogan 55e5c425e9 Fix same file error and enable passing tests 2024-01-20 08:38:18 -08:00
Eren Dogan 14c219d9f1 Enable working tests from disabled stamps 2024-01-19 15:16:30 -08:00
Eren Dogan 855139bc4e Add Makefile target to run broken tests only 2024-01-19 15:15:52 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
mole99 8032fa75a4 Add LEF output for ROM 2023-12-21 08:07:49 +01:00
Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
Eren Dogan efd43c3191 Merge branch 'dev' into issue_fix 2023-12-06 13:30:22 -08:00
Eren Dogan 7531e38cad Remove unused local variable 2023-12-05 11:18:58 -08:00
Eren Dogan 39a66fcb87 Fix some lint errors 2023-12-05 11:16:22 -08:00
Eren Dogan 6cfb22959c Remove unused imports 2023-12-05 11:08:32 -08:00
SWalker 6bd437cfa8 Fixed bug that made metal-metal vias think they were well contacts 2023-11-07 14:27:11 -08:00
SWalker b9570b8ddf removed gf180 specific code from ptx 2023-11-07 01:01:05 -08:00
SWalker ce1861f342 proper output rom bank output layer 2023-10-31 23:24:21 -07:00
SWalker d161cc55a5 fixed missing broken stamp 2023-10-31 23:24:21 -07:00
SWalker a45e16bff5 re-added rom tests to regression ignore for freepdk45 2023-10-31 23:24:21 -07:00
SWalker 26068fd2e1 more ptx fixes 2023-10-31 23:24:21 -07:00
SWalker b453aa23c2 fix ptx minwidth calculation for freepdk45 2023-10-31 23:24:21 -07:00
SWalker 5378a308c1 updated gitignore and regression make to ignore gf180. Fixed issue with rom decoder routing 2023-10-31 23:24:21 -07:00
SWalker 1f35855c6d remove old rom test 2023-10-31 23:24:21 -07:00
SWalker 9b99e6c124 bunch of cleanups to core rom classes 2023-10-31 23:24:21 -07:00
SWalker ddba3b3718 move vdd pins around to make routing nice 2023-10-31 23:24:21 -07:00
SWalker 5c22e382b5 add parameter to make routing horizonal vdd rails easier 2023-10-31 23:24:21 -07:00
SWalker 4b3af38727 change min rail to contact spacing for long gf180 contact extend 2023-10-31 23:24:21 -07:00
SWalker 565e3f6814 flatten ptx in extraction and renumber test based on importance 2023-10-31 23:24:21 -07:00
SWalker 3271c5e73c fixing drc on rom bank, mostly spacing tweaks 2023-10-31 23:24:21 -07:00
SWalker 75f7a5847f fixing contact placement for gf180 in rom 2023-10-31 23:24:21 -07:00
Sage Walker b279791762 added control buf test 2023-10-31 23:24:21 -07:00
SWalker a544abebf7 fixed contact area issue 2023-10-31 23:24:21 -07:00
Sage Walker cb8567c66f spacing tweaks for gf180 address control gate 2023-10-31 23:24:21 -07:00
Sage Walker d6cb15c82d Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean. 2023-10-31 23:24:21 -07:00
Sage Walker 0040efb86f workaround for magic drc in gf180 2023-10-31 23:24:21 -07:00