Bugra Onal
a5728cdecc
Base-verilog
2022-07-28 15:03:41 -07:00
Bugra Onal
769633a459
Base template additions
2022-07-28 15:03:41 -07:00
Bugra Onal
cda3822526
Verilog Template additions
2022-07-28 15:03:41 -07:00
Bugra Onal
28c5406075
Base verilog template init
2022-07-28 15:03:41 -07:00
Bugra Onal
2b1d0bd9f7
Template module done
2022-07-28 15:03:41 -07:00
Bugra Onal
0970095415
Bank select
2022-07-28 15:03:41 -07:00
Bugra Onal
859548f19f
Templatable verilog file
2022-07-28 15:03:41 -07:00
Bugra Onal
f08da6acc5
Fixed globals conflict
2022-07-28 15:03:41 -07:00
Bugra Onal
30f5638b9f
Replaced instances of addr_size with bank_addr
2022-07-28 15:03:41 -07:00
Bugra Onal
a0c6a0ad03
Set write_size default to word_size
2022-07-28 15:03:41 -07:00
Bugra Onal
29079bd6ac
Added conditional sections to template
2022-07-28 15:03:41 -07:00
Bugra Onal
24bb6f8c11
Multibank file generation (messy)
2022-07-28 15:03:37 -07:00
Bugra Onal
6d6063ef4e
modified template engine & sram multibank class
2022-07-21 15:56:29 -07:00
Bugra Onal
a497943be3
Template section clone method
2022-07-21 15:45:50 -07:00
Bugra Onal
b75e1fc499
Template section clone method
2022-07-21 15:45:50 -07:00
Bugra Onal
f2cd611cb8
TEmplate rework
2022-07-21 15:45:50 -07:00
Bugra Onal
988399ba73
Base-verilog
2022-07-21 15:45:50 -07:00
Bugra Onal
06c56c256e
Base template additions
2022-07-21 15:45:50 -07:00
Bugra Onal
3d3a8202fe
Verilog Template additions
2022-07-21 15:45:50 -07:00
Bugra Onal
be9fadf1bb
Base verilog template init
2022-07-21 15:45:50 -07:00
Bugra Onal
874d965edb
Template module done
2022-07-21 15:45:50 -07:00
Bugra Onal
99b517d55a
Bank select
2022-07-21 15:45:50 -07:00
Bugra Onal
54a012b574
Templatable verilog file
2022-07-21 15:45:50 -07:00
mrg
6707a93c3c
Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45.
2022-07-20 10:27:30 -07:00
mrg
ff7ceaf92d
Fix syntax error for module scope in row/col caps.
2022-07-13 17:19:09 -07:00
mrg
d92c7a634d
Use packages for imports.
...
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
2022-07-13 15:55:57 -07:00
mrg
ac86ad0e8a
Move pdk installation inside docker to use Magic from docker image.
2022-06-21 12:10:15 -07:00
mrg
dc9ae6cd1a
Increase column width in netgen LVS scripts
2022-06-16 10:30:58 -07:00
mrg
cf03454ecf
Don't add wdriver_sel_n pins which aren't used.
2022-06-10 09:18:40 -07:00
mrg
e744ffd6ea
Move mount to shared target in openram.mk
2022-06-09 06:44:23 -07:00
mrg
d30f05a1ae
Update power layer on li for sky130
2022-06-08 17:19:26 -07:00
mrg
9e3a28237f
Update port data test for sky130 single port
2022-06-08 17:18:53 -07:00
mrg
00ca2d45b6
Extract unique is option not command.
2022-06-08 15:06:06 -07:00
mrg
4814cf6eac
Merge branch 'sky130_fixes' into dev
2022-06-08 14:27:30 -07:00
mrg
280582d4d6
Add missing via in dff array
2022-06-08 14:24:17 -07:00
mrg
76bc4e1fc2
Only do one extract. Flatten transistors since bug fixed in magic.
2022-06-08 14:23:50 -07:00
mrg
ad6633ddca
Update versions of tools. Fix supply bug in predecode.
2022-06-08 13:50:25 -07:00
Jesse Cirimelli-Low
fbe3032246
add case for single spare col spare_wen_dff i/o
2022-05-26 12:18:47 -07:00
mrg
1bab395946
Merge branch 'sky130_fixes' into dev
2022-05-24 09:12:37 -07:00
mrg
cb3d7b9d5d
Add spares for sky130 unit tests.
2022-05-23 17:27:26 -07:00
mrg
b84b4dab43
Fail on pin mismatch too.
2022-05-23 16:28:28 -07:00
mrg
8c85230033
Remove experimental power option.
2022-05-23 10:08:35 -07:00
mrg
51b0f125fb
Add offset to 0,0 that was inadvertantly removed for router debug.
2022-05-23 09:59:41 -07:00
mrg
735d66c9f1
Start dff array supplies on first rather than second bit.
2022-05-17 15:54:54 -07:00
mrg
3e02a0e7df
Update column decoder and dff array supplies
2022-05-17 15:49:50 -07:00
mrg
c8905c410a
Fix case where distance is zero length comparison
2022-05-17 15:49:06 -07:00
mrg
f1f4453d14
Add column decoder module with power supply straps.
2022-05-17 13:32:19 -07:00
mrg
8217a84165
Uniquify overlap points during segment overlap computation.
2022-05-17 13:31:23 -07:00
mrg
9b592ab432
Fix missing hash recompute in vector class.
2022-05-17 13:30:41 -07:00
mrg
bed12d2a9e
pbitcell vdd/gnd are on layer m1 only.
2022-05-16 17:02:53 -07:00
Bugra Onal
mrg
Jesse Cirimelli-Low