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OpenRAM
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4273 Commits

Author SHA1 Message Date
Matt Guthaus 6d48bdf55a Merge branch 'supply_routing' into dev 2018-11-02 11:51:32 -07:00
Matt Guthaus 33bbe3fd68 Merge branch 'supply_routing' of github.com:VLSIDA/PrivateRAM into supply_routing 2018-11-02 11:51:11 -07:00
Matt Guthaus ac203d987c Merge branch 'supply_routing' into dev 2018-11-02 11:50:46 -07:00
Matt Guthaus 866eaa8b02 Add debug message when routes are diagonal. 2018-11-02 11:50:28 -07:00
Matt Guthaus 7e39150c38 Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-02 11:13:34 -07:00
Matt Guthaus 56fa274a5e Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-02 11:12:35 -07:00
Matt Guthaus 4d30f214da Add expanded blockages for paths an enclosures to handle wide metal spacing rules. 2018-11-02 11:11:32 -07:00
Matt Guthaus 4e09f0a944 Change layer text to comment to avoid glade reserved keyword 2018-11-02 10:58:00 -07:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Hunter Nichols 642dc8517c Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well. 2018-11-01 14:05:55 -07:00
Jesse Cirimelli-Low 3fa1d5522e added DRC/LVS error count to datasheet 2018-11-01 14:02:33 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus b24c8a42a1 Remove redundant pins in pin_group constructor. Clean up some code and comments. 2018-11-01 11:31:24 -07:00
Michael Timothy Grimes dc96d86082 Optimizations to pbitcell spacings 2018-11-01 07:58:20 -07:00
Matt Guthaus 2eedc703d1 Rename function in pin_group 2018-10-31 16:13:28 -07:00
Matt Guthaus c511d886bf Added new enclosure connector algorithm using edge sorting. 2018-10-31 15:35:39 -07:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Jesse Cirimelli-Low c3d7e24df9 fixed broken links when -o flag set 2018-10-31 09:34:36 -07:00
Matt Guthaus 673027ac8c Moved assert to check out_path earlier. 
Preserve temporary output directory with -d option.
 2018-10-31 09:37:47 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Jesse Cirimelli-Low 5302fd205f fixed some final typos in datasheet 2018-10-30 23:03:05 -07:00
Jesse Cirimelli-Low 70ac2e8aa4 changed css to orange and black for Halloween; fixed CSb timing table in datasheet 2018-10-30 22:56:13 -07:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Jesse Cirimelli-Low 905f6f8b43 added docstring and renamed some functions 2018-10-30 21:37:30 -07:00
Matt Guthaus fc45242ccb Allow contains to contain copy. Add connectors when pin doesn't overlap grids. 2018-10-30 17:41:29 -07:00
Matt Guthaus 7099ee76e9 Remove blocked grids from pins and secondary grids 2018-10-30 16:52:11 -07:00
Matt Guthaus 1344a8f7f1 Add remove adjacent feature for wide metal spacing 2018-10-30 12:24:13 -07:00
Matt Guthaus c4163d3401 Remove debug statements. 2018-10-29 13:50:56 -07:00
Matt Guthaus fa272be3bd Enumerate more enclosures. 2018-10-29 13:49:29 -07:00
Matt Guthaus cd87df8f76 Clean up enclosure code 2018-10-29 11:27:59 -07:00
Matt Guthaus f19bcace62 Merged in an old stash. 2018-10-29 11:18:12 -07:00
Matt Guthaus b7655eab10 Remove bug for combining pin with multiple other pins in a single iteration 2018-10-29 11:07:02 -07:00
Matt Guthaus bbffec863b Abandon connectors for now and opt for all enclosures 2018-10-29 10:59:22 -07:00
Matt Guthaus 6990773ea1 Add error check requiring non-zero area pin layouts. 2018-10-29 10:32:42 -07:00
Matt Guthaus 851aeae8c4 Add pins_enclosed function to pin_group 2018-10-29 10:28:57 -07:00
Jesse Cirimelli-Low 2da90c4b6a fixed double counting of characterization tuple permutations 2018-10-27 12:04:10 -07:00
Jesse Cirimelli-Low f1fb174b53 fixed bug where netlist_only still produced layout deliverables 2018-10-27 11:21:06 -07:00
Hunter Nichols 3bb8aa7e55 Fixed import errors with mux analytical delay model. 2018-10-26 17:37:25 -07:00
Matt Guthaus 0107e1c050 Reduce verbosity of utils 2018-10-26 13:02:31 -07:00
Matt Guthaus 7d74d34c53 Fix pin_layout contains bug 2018-10-26 10:40:43 -07:00
Matt Guthaus 4ce6b040fd Debugging missing enclosures 2018-10-26 09:25:10 -07:00
Jesse Cirimelli-Low b1ade15eaf Merge branch 'datasheet_gen' after rebase with dev 2018-10-26 07:58:29 -07:00
Jesse Cirimelli-Low fcfee649d5 moved css into a seperate file to organize and disambiguate docstrings from multiline strings 2018-10-26 07:57:54 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Matt Guthaus 9e5d78cfc2 Fix bug in duplicate remove indices 2018-10-25 14:40:39 -07:00
Matt Guthaus 3407163cf1 Combine adjacent power supply pins finished 2018-10-25 14:25:52 -07:00
Matt Guthaus 0544d02ca2 Refactor router to have pin_groups for pins and router_tech file 2018-10-25 13:36:35 -07:00