15 Commits

Author	SHA1	Message	Date
Felix Schneider	6c7c6a9fba	Fix wire capacitance unit in sky130, gf180 ... The `wire_spice_model()` expects `spice["wire_unit_c"]` in Farads per micrometer squared (F/um²). This is given correctly in the FreePDK45 tech but incorrectly in other technologies. This leads to a huge overestimation of wire capacitance in those technologies, leading to incorrect power values.	2024-01-22 17:32:00 +01:00
Hadir Khan	b65ebc6160	corrected the import statement and removed strap variant attribute which is no longer needed	2023-10-31 23:24:21 -07:00
SWalker	565e3f6814	flatten ptx in extraction and renumber test based on importance	2023-10-31 23:24:21 -07:00
SWalker	3271c5e73c	fixing drc on rom bank, mostly spacing tweaks	2023-10-31 23:24:21 -07:00
SWalker	75f7a5847f	fixing contact placement for gf180 in rom	2023-10-31 23:24:21 -07:00
SWalker	a544abebf7	fixed contact area issue	2023-10-31 23:24:21 -07:00
Sage Walker	cb8567c66f	spacing tweaks for gf180 address control gate	2023-10-31 23:24:21 -07:00
SWalker	4bb586c949	decoder nand custom cell	2023-10-31 23:24:21 -07:00
Sage Walker	d6cb15c82d	Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.	2023-10-31 23:24:21 -07:00
Hadir Khan	698020301c	updates to add the port order overwrite attribute, ignore drc/lvs attribute and pwell as a non-routing layer	2023-10-31 23:24:21 -07:00
hadirkhan10	b9fd172e44	corrected the pin mapping	2023-10-31 23:24:21 -07:00
hadirkhan10	de7a248ff0	added the cell property definitions	2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low	a904874978	passing gf180 parameterized gate tests	2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low	d18a4f8c7c	additional tech commits	2023-10-31 23:24:21 -07:00
Jesse Cirimelli-Low	a18d62c430	rename gf180 to gf180mcu	2023-10-31 23:24:21 -07:00