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OpenRAM
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255 Commits

Author SHA1 Message Date
Bugra Onal 6751442d35 account for spare cols in char 2023-07-19 16:09:28 -07:00
Bugra Onal 0ad619f04c Added bl, sen and cell format options 2023-07-10 12:32:58 -07:00
Bugra Onal 8d0c46d069 Fix import issue 2023-04-12 11:48:20 -07:00
Bugra Onal f7f61fee27 Format fixes 2023-02-22 12:38:47 -08:00
Bugra Onal 4436c61a39 discard if precharge delay is captured 2023-02-17 14:35:09 -08:00
Bugra Onal 7a62ec0030 Fixed typo 2023-02-16 19:36:14 -08:00
Bugra Onal 9002a8ac70 Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
Bugra Onal 39104fa9d8 Delay measure always measure from clk neg edge 2023-02-06 14:13:56 -08:00
Bugra Onal da86d50766 Guess the bitcell name format 2023-01-31 13:08:40 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
Bugra Onal 817dc8a063 Guess the bl format 2023-01-20 12:50:09 -08:00
Bugra Onal a7cbf254be Merge branch 'dev' into char 2023-01-19 12:18:38 -08:00
Bugra Onal 7fdc5cc782 modify char to work with older macro 2023-01-19 11:39:16 -08:00
Bugra Onal db85e8ecd6 standalone char and func 2022-12-13 07:53:58 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Bugra Onal 816eff711d Recover function for measures 2022-11-29 14:48:35 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Bugra Onal 2b79646b8f Merge branch 'dev' into char 2022-10-04 09:09:52 -07:00
Bugra Onal c6440dc16d restore netlist on memchar 2022-09-27 13:44:28 -07:00
Bugra Onal 214f55f8d7 Save trimmed spice and stimulus 2022-09-14 14:34:22 -07:00
Bugra Onal b1e4c83373 Move measure functions from stimuli to measure 2022-09-09 12:51:53 -07:00
Bugra Onal b9dbad4750 Separate measure statements from stimulus 2022-09-09 11:48:13 -07:00
Bugra Onal fcfb9391f6 Code formatting 2022-09-01 16:19:14 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 76f5578cc1 Removed path delays from characterization output to not disturb the current testing flow. 2021-05-25 15:19:27 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
Hunter Nichols 16904496ac Made path delays write out to the extended OPTS file. 2021-05-05 01:14:54 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 90cb9f581f Fixes to get hspice delay test to pass. 2021-03-02 09:28:41 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
ota2 9a2987ad07 Add spectre simulator 2021-02-27 19:25:00 -05:00
Hunter Nichols b5516865f1 Added option to allow specific load/slew combinations in config file. 2021-02-24 16:43:34 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
Hunter Nichols 56c4c89720 Adjusted error margin for period in analytical model and added check in model test. 2020-12-17 01:34:53 -08:00
Hunter Nichols 25544c3974 Added similar interface to linear regression as elmore 2020-12-14 13:59:31 -08:00
Hunter Nichols 77d7e3b1cf Merge branch 'dev' into automated_analytical_model 2020-12-07 14:24:04 -08:00
Hunter Nichols d111041385 Refactored analytical model to be it's own module with shared code moved to simulation 2020-12-02 14:06:39 -08:00