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OpenRAM
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865 Commits

Author SHA1 Message Date
mrg 67877175b2 Fix error in no spare column verilog 2021-06-18 08:41:26 -07:00
Jesse Cirimelli-Low 7b7c72706a merge in dev 2021-06-17 09:49:32 -07:00
Jesse Cirimelli-Low 1ce6b4d41a fix freepdk45 2021-06-17 03:21:01 -07:00
mrg afe0902547 Enable small short func tests 2021-06-16 19:13:50 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
Hunter Nichols da67edbde8 Changed input format for delay module in xyce delay test. 2021-05-26 20:11:30 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
mrg d51ec4fe45 Add Xyce tests 2021-05-21 12:04:26 -07:00
mrg d43edd95e4 Update golden tests for verilog 2021-05-06 19:56:22 -07:00
mrg 789a8a1cf0 Update golden verilog results 2021-05-05 15:37:27 -07:00
mrg 5b556e6ef5 Update unit test results with new Verilog models. 2021-04-15 15:48:20 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
mrg 7610f23fc7 Sub temp directory. Add github archive. 2021-02-10 15:39:12 -08:00
Bob Vanhoof 3dfc039f6f add technology option passtrough in test 30 2021-02-09 09:32:35 +01:00
mrg b83d93cc9a GitHub Actions CI flow. 2021-02-08 15:46:02 -08:00
mrg e043aaffb3 Don't print DRC/LVS/PEX run stats in regress.py 2021-02-03 15:17:28 -08:00
mrg 19e99d1c7b Enable parallel regression testing. 2021-02-03 14:19:11 -08:00
Hunter Nichols df8d59f32e Merge branch 'dev' into automated_analytical_model 2021-02-01 01:49:45 -08:00
mrg bc8fd4a882 Merge branch 'supply_router' into dev 2021-01-25 11:01:48 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg db142bcd5a Rename pins to original names 2021-01-21 15:22:54 -08:00
Hunter Nichols cd84cf1973 Merged and addressed conflict in delay.py 2021-01-06 01:37:16 -08:00
Hunter Nichols 48baf3ab4e Updated test to use new analytical class 2021-01-06 01:34:44 -08:00
mrg 9ef4cf14c5 Check for drc/lvs aux scripts in test 30 2020-12-23 07:25:24 -08:00
mrg e59333a232 Change options to use route perimeter pins and supply as tree by default. 2020-12-23 07:25:07 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg 3a3ecb27d2 Merge branch 'dev' into supply_router 2020-12-17 15:53:31 -08:00
Hunter Nichols 56c4c89720 Adjusted error margin for period in analytical model and added check in model test. 2020-12-17 01:34:53 -08:00
mrg d5ed45dadf Make default router tree router 2020-12-16 16:42:19 -08:00
mrg fd118c62e5 Default zom is None not negative. 2020-12-15 13:27:36 -08:00
Hunter Nichols 942675051a Added test for linear regression model. 2020-12-14 14:37:53 -08:00
mrg 87493e1e30 Disable pex tests. 2020-12-11 11:47:10 -08:00
mrg 38bf12771b Make DRC/LVS scripts use relative paths 2020-12-11 10:06:00 -08:00
mrg 9717794400 Remove extra debug statement 2020-12-08 11:59:14 -08:00
mrg 0008de3e59 Change test 14 to odd sizes for use in sky130. 2020-12-08 10:32:23 -08:00
mrg e134e07522 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-20 16:57:14 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
mrg 7512aa6e70 Skip test 50 which is too slow 2020-11-16 08:59:25 -08:00