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OpenRAM
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3396 Commits

Author SHA1 Message Date
Hunter Nichols 53503f40d2 Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. 2021-05-24 12:03:26 -07:00
Hunter Nichols a4cb539f72 Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction. 2021-05-24 10:44:46 -07:00
Hunter Nichols 4e40017fdc Added model configs adapted from OpenRAM Library 2021-05-20 15:26:24 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00
Hunter Nichols 269b698b0a Fixed issues with csv generation. Added regex parsing to determine corners from datasheet. 2021-05-18 23:41:16 -07:00
Hunter Nichols 36b1bc1284 Added script to extract data from datasheet output and store in CSV. 2021-05-17 14:04:20 -07:00
Hunter Nichols 0434e57609 Added target in makefile to run configs and store results in tech directory. 2021-05-17 14:03:32 -07:00
Hunter Nichols 16904496ac Made path delays write out to the extended OPTS file. 2021-05-05 01:14:54 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg 5b556e6ef5 Update unit test results with new Verilog models. 2021-04-15 15:48:20 -07:00
Matt Guthaus 8ffe8501ff
Merge pull request #102 from dpetrisko/patch-1 
Minor typo in README.md
 2021-04-15 14:49:40 -07:00
mrg aa5e1fd168 Merge remote-tracking branch 'olofk/verilog_model_features' into dev 2021-04-15 14:41:56 -07:00
Olof Kindgren 688a1f1e60 Add HOLD_DELAY parameter for dout in verilog model 
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:39:49 +02:00
Olof Kindgren 1d657abebc Add VERBOSE parameter to generated verilog model 
This allows disabling the $display commands that are generated for every
read and write access to the model. The verilog output has been tested
with the following example script

from compiler.base.verilog import verilog

v = verilog()

v.num_words = 256
v.word_size = 32
v.write_size = 8
v.name = "sky130_sram_1kbyte_1rw1r_32x256_8"
v.all_ports = [0,1]
v.readwrite_ports = [0]
v.read_ports = [0,1]
v.write_ports = [0]
v.addr_size=8

v.verilog_write("mymodule.v")

Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
 2021-04-15 22:33:57 +02:00
mrg 41226087ba Use separate mXp pin layer if it exists 2021-04-14 13:55:21 -07:00
mrg 3eed6bb8ff Check for None before checking DRC tool 2021-04-14 11:07:38 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg 0e48e020c1 Use pins in computing bbox offsets 2021-04-13 16:24:28 -07:00
mrg e706f776eb Offset macro to 0,0 which was accidentally comented by a PR 2021-04-13 16:24:13 -07:00
mrg b510925bdb Enable pruning by default (except on unit tests) 2021-04-07 16:08:29 -07:00
mrg 61b1b90dd3 Use built in binary conversion. Improve spare debug output. 2021-04-07 16:08:29 -07:00
mrg 229b0059c4 Add perimeter margin to expand pins outside perimeter for OpenRoad router. 2021-04-07 16:08:29 -07:00
mrg 5843aa037c Update functional test to use spare columns separately. 
Fix no spare columns data width error.
 2021-04-07 16:08:24 -07:00
mrg 0a02f635ad Remove lvs_write from sram 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 31d3e6cb26 Change LWL layers 2021-04-07 16:07:56 -07:00
mrg e0024fa79a Add verbosity to error output 2021-04-07 16:07:56 -07:00
mrg bd28a7a93b Merge branch 'sky130_fixes' into dev 2021-04-01 16:48:22 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
mrg 7e29dd7ff2 Reduce verbosity of routing info 2021-03-31 09:38:06 -07:00
mrg b9086dbbe5 Add unit test times to output. 2021-03-26 06:56:58 -07:00
mrg e681806f0d Update to 24 threads. 2021-03-25 10:02:34 -07:00
mrg 6e2f60353c Add wells to driver stages. Remove unnecessary height/center in control logic. 2021-03-25 10:00:24 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg e144f03b23 Add status for supply routing. 2021-03-24 11:15:59 -07:00
mrg fae72ca993 Test new archive options for github actions. 2021-03-23 13:06:36 -07:00
mrg 7b270514e1 Update multithreaded regression. 
Only do 2 threads for 30 tests.
Don't archive results since they are purged anyways.
16 threads for regression.
Purge temp during regression.
 2021-03-23 10:45:56 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
Hunter Nichols 6f01ab4792 Added simulation time modeling to regression model. 2021-03-22 12:55:29 -07:00
Hunter Nichols 208586a8e8 Added simulation time in the datasheet 2021-03-22 12:21:10 -07:00
mrg b6f3fbdd1f Use OPTS.precharge instead of hard coded precharge. 2021-03-15 09:44:14 -07:00
mrg db118beeba Zoom parameter should be optional in tech files. 2021-03-02 13:38:09 -08:00
Hunter Nichols 2cd3d28add linear regression model coefficients are now written to the extended config file 2021-03-02 13:14:56 -08:00
mrg da3a100301 Try new wildcard for archive path. 2021-03-02 09:28:59 -08:00
mrg 90cb9f581f Fixes to get hspice delay test to pass. 2021-03-02 09:28:41 -08:00
mrg fb953c19e8 Remove option that causes errors and is unused. 2021-03-01 16:36:27 -08:00
mrg 13bdae2e30 Merge remote-tracking branch 'private/dev' into control-logic-pull 2021-03-01 15:47:33 -08:00
mrg 049d3ffcaf Remove extra test file 2021-03-01 15:25:39 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00