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OpenRAM
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1173 Commits

Author SHA1 Message Date
Hunter Nichols 50f13eabce Added better port selection to bitline measurements. 2018-12-12 15:59:20 -08:00
Hunter Nichols 0a26e40022 Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
Hunter Nichols 6ac474d642 Added bitline measures with hardcoded names. 2018-12-12 00:43:08 -08:00
Hunter Nichols 82e074ebf0 Added initial structure for bitline measurements. 2018-12-11 14:06:11 -08:00
Hunter Nichols 4d84731c34 Edited heuristic delay chain and delay model to account for read port differences. 2018-12-07 15:39:53 -08:00
Hunter Nichols b157fc58a1 Moved feasible period search from functional.py to tests. 2018-12-05 23:23:40 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 448e8f4cfd Merged with dev 2018-12-05 17:49:42 -08:00
Matt Guthaus 7645a909eb Merge branch 'supply_routing' into dev 2018-12-05 17:24:51 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Matt Guthaus 2cd1322071 Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
Matt Guthaus fa3bf2915a Remove commented code 2018-12-05 09:56:19 -08:00
Matt Guthaus 0c0a23e6eb Cleanup code. Add time breakdown for SRAM creation. 2018-12-05 09:51:17 -08:00
Hunter Nichols 0c3c58011b Fixed delay test values. 2018-12-05 00:13:23 -08:00
Matt Guthaus f1c74d6bfb Merge branch 'dev' into supply_routing 2018-12-04 17:57:18 -08:00
Matt Guthaus d95b34caf2 Round output to look pretty 2018-12-04 17:08:47 -08:00
Matt Guthaus e750d446dc Fix syntax error. Enable skipped test. 2018-12-04 17:08:22 -08:00
Matt Guthaus 126d4a8d10 Fix instersection bug. Improve primary and secondary pin algo. 2018-12-04 16:53:04 -08:00
Matt Guthaus 7ce75398a8 Change warning to info 2018-12-04 09:42:47 -08:00
Matt Guthaus 7fce6f06ca Expand grids to maximal pin before removing blockages 2018-12-04 09:35:40 -08:00
Matt Guthaus 389bb91af4 Simplifying supply router to single grid track 2018-12-04 08:41:57 -08:00
Matt Guthaus 2a68b57215 Changed psram info to sram 2018-12-03 15:59:31 -08:00
Matt Guthaus c6f03e70d4 Convert supply to wider DRC rules 2018-12-03 11:09:17 -08:00
Matt Guthaus bcc6b95564 Add coverage exclusions. Add subprocess coverage. 2018-12-03 09:13:57 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 49f7022416 Skip failing tests with comments for bugs. 2018-11-30 12:33:43 -08:00
Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 2018-11-30 12:32:13 -08:00
Matt Guthaus 7e054a51e2 Some techs don't need m1 power pins 2018-11-29 18:47:38 -08:00
Matt Guthaus 0af4263edb Remove extra rotated vias in bitcell array to simplify power routing 2018-11-29 18:13:15 -08:00
Matt Guthaus 0e7301fff8 Update unit test golden results. Skip two tests. 2018-11-29 17:28:57 -08:00
Matt Guthaus e98f7075e2 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-29 16:29:17 -08:00
Matt Guthaus 33a7683473 Remove used gated_clk instead of cs for read-only control logic. 2018-11-29 16:28:37 -08:00
Matt Guthaus a7be60529f Do not rotate vias in horizontal channel routes 2018-11-29 13:57:40 -08:00
Matt Guthaus 3c4d559308 Fixed syntax error referring to column mux 2018-11-29 13:29:16 -08:00
Matt Guthaus 3d3f54aa86 Add col addr line spacing for col addr decoder 2018-11-29 13:22:48 -08:00
Matt Guthaus 4df862d8af Convert channel router to take netlist of pins rather than names. 2018-11-29 12:12:10 -08:00
Matt Guthaus a7bc9e0de0 Use module height not instance uy for sram placement 2018-11-29 10:34:25 -08:00
Matt Guthaus 0a16d83181 Add more layout and functional port tests. 2018-11-29 10:28:43 -08:00
Matt Guthaus 14fa33e21d Remove 4 bank code and test for now. 2018-11-29 10:28:09 -08:00
Matt Guthaus 7054d0881a Fix col address dff spacing from bank. 2018-11-29 09:54:29 -08:00
Matt Guthaus 02a67f9867 Missing gap in port 1 col decoder 2018-11-28 18:07:31 -08:00
Matt Guthaus d041a498f3 Fix height of port 1 control bus. Adjust column decoder names. 2018-11-28 17:48:25 -08:00
Matt Guthaus f8513da162 Remove local temp dir 2018-11-28 17:04:53 -08:00
Matt Guthaus a2a9cea37e Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
Matt Guthaus 3cfe74cefb Functional simulation uses threshold for high and low noise margins 2018-11-28 16:55:04 -08:00
Matt Guthaus 25ae3a5eae Fix error of no control bus width 2018-11-28 15:42:51 -08:00
Matt Guthaus d99dcd33e2 Fix SRAM level control routing errors. 2018-11-28 15:30:52 -08:00
Matt Guthaus 143e4ed7f9 Change hierchical decoder output order to match changes to netlist. 2018-11-28 14:09:45 -08:00
Matt Guthaus b5b691b73d Fix missing via in clk input of control 2018-11-28 13:20:39 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00